IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
7, JULY 2010
Impact of Scaling on Neutron-Induced Soft Error in
SRAMs From a 250 nm to a 22 nm Design Rule
Eishi Ibe, Fellow, IEEE, Hitoshi Taniguchi, Yasuo Yahagi, Ken-ichi Shimbo, and Tadanobu Toba
Abstract—Trends in terrestrial neutron-induced soft-error in
SRAMs from a 250 nm to a 22 nm process are reviewed and
predicted using the Monte-Carlo simulator CORIMS, which is
validated to have less than 20% variations from experimental
soft-error data on 180–130 nm SRAMs in a wide variety of neutron
fields like field tests at low and high altitudes and accelerator tests
in LANSCE, TSL, and CYRIC. The following results are obtained:
1) Soft-error rates per device in SRAMs will increase x6-7 from
130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller
size, soft-error rate is dominated more significantly by low-energy
neutrons (< 10 MeV); and 3) The area affected by one nuclear
reaction spreads over 1 M bits and bit multiplicity of multi-cell
upset become as high as 100 bits and more.
Index Terms—Bit multiplicity, cosmic ray impact simulator
(CORIMS), multi-cell upset (MCU), multi-node upset (MNU),
scaling, single event upset (SEU), static random access memories
(SRAMs).
I. I NTRODUCTION
S CALING down of semiconductor devices to sub-100 nm
technology encounters a wide variety of technical chal-
lenges like Vth variation [1], negative bias temperature insta-
bility (NBTI) [2], short-channel effect [3], gate leakage [4],
and so on. Terrestrial neutron-induced single event upset (SEU)
is one key issue that can be a major setback in scaling. In
particular, “multi-cell upsets (MCUs),” which are defined as
simultaneous errors in more than one memory cell induced
by a single event, have been under close scrutiny [5]–[9]. The
concept of the MCU, therefore, contains both upsets that can
be corrected by error detection/correction code (EDAC/ECC)
as well as those which cannot. The latter is called “multiple
bit upset” or “multi-bit upset” (MBU) of memory cells in the
same word, and can lead, for example, to hang-ups of computer
systems. Though MBUs can be avoided by a combination of
ECC and the interleaving technique [9], MCUs that can be
corrected by EDAC/ECC can still be problematic in high-
performance devices such as contents addressable memories
(CAMs) [10] used in network processors and routers. In the
case of system design, it is therefore very important to evaluate
MCUs as well as soft-error rates (SERs) of the device in
design phase.
Manuscript received October 20, 2009; revised March 18, 2010; accepted
March 24, 2010. Date of publication May 20, 2010; date of current version
June 23, 2010. The review of this paper was arranged by Editor G.-T. Jeong.
The authors are with the Production Engineering Research Labora-
tory, Hitachi, Ltd., Yokohama 244-0817, Japan (e-mail: hidefumi.ibe.hf@
hitachi.com; hitoshi.taniguchi.dn@hitachi.com; yasuo.yahagi.rg@hitachi.com;
kenichi.shimbo.tu@hitachi.com; tadanobu.toba.ee@hitachi.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2047907
0018-9383/$26.00 © 2010 IEEE
1527
In addition, MCU can be a threat in mission-critical systems
with an extreme number of logic devices that are mainly pro-
tected by spatial or time redundancies. Typically redundancy
circuits such as triple module redundancy (TMR) [11], dupli-
cation [12], replication [13], and redundant-nodes latches/FFs
[14]–[18] like the dual interlocked storage cell (DICE) [19]
cannot be effective when relevant nodes are corrupted simulta-
neously by an MCU [20], [21]. Since such redundancy systems
in electronic systems are strictly relevant to the international
standard IEC61508 [22] that defines the functional safety of
electrical/electronic/programmable electric safety related sys-
tems, protection technologies against MCUs may have to be
consistent with the scope of the standard.
Historically MCUs are understood as taking place as a
result of the collection of charges produced by secondary
ions from nuclear spallation reaction in a device. As de-
vice scaling down proceeds, novel MCU modes are being
reported as “charge sharing among memory storage nodes in
the vicinity [8], [23] or bipolar effects in p-well [9], [24],
[25]. Ibe et al. have proposed multi-coupled bipolar interac-
tion (MCBI) for one of the bipolar MCU mechanisms that is
regarded as a parasitic thyristor effect triggered by a single
event snapback (SES) in the p-well and causes MCU mul-
tiplicity of more than 10 bits [9]. It is also reported that
MCU physical address pattern differs depending on written
data patterns typically between the groups ALLX (All “1”
or All “0”) and Checkerboard (CB or its complement CBc).
In this paper, the statistics in SEUs and MCUs in static
random access memories (SRAMs) are predicted down to
22 nm process by using the Monte-Carlo simulator CORIMS
[26]. In the present paper, the bipolar effects may be much
more fatal in practical applications but are not included into
the physical model in CORIMS because of their complexity.
The effects of the bipolar actions will be modeled and reported
elsewhere.
In Section II, the physical model, major algorithms, and
statistical parameters are reviewed. In Section III, simulation
results are presented and discussed in conjunction with impacts
on logic devices. Section IV concludes the insights from the
simulation results.
II. M ODEL D ESCRIPTION
A. Overall Microscopic Soft-Error Model
Fig. 1 depicts a schematic of a microscopic soft-error model
for a SRAM cell, which has two n+ nodes in the p-well and two
p+ storage nodes in the n-well. Two sets of adjacent n+ and p+
nodes correspond to two potential states: “high” or “low.” The
1528 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010

Fig. 2. Neutron energy spectrum at sea level in New York City under medium
Fig. 1. Macroscopic mechanism of neutron-induced soft-error in static ran-
solar activity [32].
dom access memory (SRAM). Physical sequences proceeds from  1 to  5 .

memory data “1” or “0” is assigned to the side (right or left) that
has high potential. Once a ballistic neutron penetrates into the
SRAM, nuclear spallation reaction may take place between the
neutron and the nucleus (mostly Si) in the device. As a prompt
reaction, nucleons (protons and neutrons) collide with each
other in the nucleus. Some of the nucleons may escape from the
nucleus when they have enough kinetic energies. This process
is called Intra-Nuclear Cascade (INC) [27]. After this prompt
process, light nuclei may be “evaporated” from the residual
excited nucleus [28]. As a consequence nucleons, light nuclei,
and the residual nucleus run inside the SRAM cell producing
electron-hole pairs along with the ion track. Energy necessary
to produce one pair of electron and hole is 3.6 eV in Si. When
one of such secondary ions hit the storage nodes, some of
the charges are collected to the storage node mainly through
the funneling effect [29] and the drift/diffusion process. If the Fig. 3. Calculated energy spectra of secondary ions produced in Si substrate
at sea level in New York City.
amount of the charges exceeds the critical charge that can flip
the logical state of the SRAM, a soft-error takes place in the
SRAM. energy, and direction of each secondary ion produced in a
spallation reaction are thus determined and reaction locations
are randomly set in the device model.
B. Nuclear Spallation Reaction Models The accuracy of the nuclear reaction model is validated
Monte-Carlo single event CORIMS [26] is equipped with though the comparison of nuclear reaction data of high-energy
numerical solutions for nuclear spallation reactions of silicon, proton and aluminum [31]. SER in the device under any neutron
ion track analysis in an infinite layout of memory cells in a spectra can be simulated. In the case of a simulation at a
semiconductor device, and charge collection to the diffusion specific location at ground level on Earth, the terrestrial neutron
layer of the device. The model of the nuclear spallation re- spectrum at the location is corrected in accordance with the
action is based on the intra-nuclear cascade (INC) model and geomagnetic latitude and the altitude based on the standard
the evaporation model by Weisskopf and Ewing [28]. The neutron spectrum at sea level in New York City as shown in
INC model is applied to the prompt collision process, where Fig. 2 [32].
many-body collisions among nucleons (neutron and proton) are Fig. 3 shows an example of outputs from CORIMS for the
treated numerically as cascades of relativistic binary collisions energy spectra of secondary ions produced directly from Si
between two nucleons in the target nucleus. The evaporation substrate with the neutron spectrum in Fig. 2. It is noteworthy
model of light particles from excited nucleus is also applied for that:
a delayed nuclear reaction process, where nucleons (n and p), (i) light particles such as proton and helium (or alpha parti-
deuterons (2 H or D), tritons (3 H or T), helium, and residual cle) have high production rates and high energies up to a
nucleus are released into the substrate. The inverse reaction few hundreds to 1000 MeV; while
cross section necessary for the determination of an evaporation (ii) heavier particles such as Mg and Al also have relatively
channel (a set of evaporated light particle and residual nucleus) high production rates but do not have high energies with
is calculated based on the GEM model [30]. Nucleus type, maximum energies 10–100 MeV.
IBE et al.: IMPACT OF SCALING ON NEUTRON-INDUCED SOFT ERROR IN SRAMs
Fig. 4. Calculated charge production density of electron-hole pairs in Si
substrate.
Fig. 5. Calculated ranges of ions in Si substrate.
C. Charge Deposition Model
Fig. 4 shows thr calculated charge deposition density for the
relevant ions based on the SRIM tables [33].
It is also important to take note of the following:
(i) The charge production density by proton and alpha
becomes lower when the energy is higher beyond
0.1–1 MeV. This implies that protons and alpha particles
with high energy demonstrated in Fig. 3 do not have high
contributions to soft-error in SRAMs.
(ii) The charge production density by heavier ions becomes
larger when the ion energies increase in the relevant
energy range as shown in Fig. 3.
Fig. 5 shows the average range of ions as a function of kinetic
energy also based on the SRIM tables.
It can be seen that
(i) light particles have as long ranges as 10–100 mm in Si
substrate in the relevant energy range in Fig. 3; while
(ii) heavier particles have much shorter ranges of 1–100 μm.
D. SRAM Device Model
The model layout of the MOSFET SRAM cell is illustrated
in Fig. 6. Since the active regions are isolated by STI oxide
1529
Fig. 6. Simplified structure of the CMOS SRAM unit cell for the single event
simulator CORIMS. (a) Top view. (b) A-A’ cross section.
in a lateral direction and wells line up across the word lines,
charge collection in the lateral direction is tightly limited in
the present device. Bits in a word are aligned along a word
line so that MBUs in this device are tightly limited eventually.
When an ion passes through the depletion layer under the
storage node, the funneling model is applied to calculate the
charge collected to the storage node. When the ion passes
through the p-n junction in the bottom of the p-well, funneling
also takes place so that the charge deposited in the p-well is
distributed to the storage node and the p-substrate below the
p-well. The funneling effect becomes larger when the ion track
runs along with the p-well (BL direction) because there is less
probability that the ion will pass through the other p-n junction
in the p-well. A drift-diffusion layer with a thickness 100 nm is
assumed to be located under the storage node. When an ion
passes through only the drift-diffusion layer, the amount of
charges in the layer is assumed to be collected to the storage
node. The charge deposited inside the storage node and oxide
is assumed to recombine and not to contribute to soft-error.
Any 3-D device model, including SRAMs, can be constructed
automatically from the device layout data in GDS2 files [34] by
using a specially designed tool. Ion tracks though components
in a device are analyzed with the help of computer geometry
techniques in CORIMS.
E. Charge Collection Model
As indicated in Fig. 1, the funneling model proposed by
Hu et al. is applied [29] when the secondary ion penetrates into
the depletion layers under the p+ and n+ storage nodes. No
charge collection is assumed to take place when the secondary
ion penetrates into the STIs, into the storage nodes themselves,
and into the upper regions (5 μm thickness Si layer is given in z
1530 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010

plus direction but not shown in Fig. 6) where the recombination

of electrons and holes is dominant.
The funneling length xc , within which the deposited charge
is collected to the storage node from the bottom of the storage
node, is expressed as follows:
 
μn W
xc = 1 + (1)
μe | cos ω|
where
μn is the mobility of the hole;
μe is the mobility of the electron;
W is the thickness of the depletion layer, and (μm);
ω is the zenith angle.
When the secondary ion penetrates two p-n junctions at the
bottom of the n+ diffusion layer and at the wall of the p-well,
the funneling grows toward both p-n junctions and it is assumed
that eventually only half of the deposited charge is collected to
the n+ node. Fig. 7. DCS method which enables simulation in an infinite memory cell
Equation (1) gives a very large maximum funneling length matrix array.
when ω approaches π/2. A more realistic picture is that the
When an ion crosses a memory cell matrix along the line
ratio of collected charge to the n+ node would be decreased
A-B-C-D, the track of the ion may be traced as long as the ion
as the distance from the n+ node becomes longer along with
has a possibility to hit the sensitive components. This method
the funneling path due to recombination effect of electrons and
requires a cell matrix that is wide enough compared to the
holes. Assuming that such decrease is an exponential function,
ion range. The proposed method does not need an actual cell
the following equation is given to correct the collected charge
matrix. Instead, it utilizes only one physical cell model. When
Qcollect :
  an ion reaches the boundary at B, for example, the track is
xc virtually shifted to B -C by using a shift in the Y -coordinates
Qcollect = Qall exp − (2)
Lmax and the physical address of Y direction Yad is incremented by
1 bit. Similarly when the actual ion crosses C-D, the virtual
where track is shifted to C -D and the physical addresses of X and Y
Qall all deposited charge in the funneling length xc cal- direction are incremented by 1 bit from the original address. In
culated from (1); this way, any ion track can be traced until it stops, regardless
Lmax effective maximum funneling length (assumed to be of the length of the ion’s range. In the present device, the
4 μm to give better fit to experimental data). condition of data “1” or “0” corresponds to the position (left or
Together with the funneling model, a drift-diffusion model is right) of the “high” node in one bit of SRAM and the layout of
also applied when the secondary ion does not penetrate the n+ the SRAM is in symmetry to its center. Also all “1” and all “0”
node but passes very close to the n+ node. The drift diffusion have the same feature and susceptibility to neutron impacts.
box, with a thickness of 0.1 μm, is assumed below the n+ node. To save the area penalty, some nodes connected to Vdd or Vss
All deposited charge is assumed to be collected to the n+ node. are commonly shared between adjacent bits. In this case, the
As for the p+ node in the n-well, only the charge in the bit layout is folded symmetrically along the boundary between
depletion layer is assumed to be collected to the node. Neither the two bits. This technique is sometimes called “mirroring.”
funneling nor drift diffusion effect is not applied to pMOSFET The DCS method implemented in CORIMS is applicable in this
because of the low mobility of the holes. type of mirroring.
The physical device model may be too simplified com- Any cyclic data pattern in a rectangular zone can be imple-
pared to full TCAD models [5], [9], but such simplification mented in CORIMS. The basic idea is illustrated in Fig. 8. Once
is unavoidable for Monte-Carlo simulations, where more many the data “1” or “0” pattern is set in a unit rectangular zone, the
nuclear reactions are incorporated in order to obtain satisfactory units are close-packed infinitely in the WL and BL directions.
statistics. Interleaving effects with any bit layout in the same word can
also be analyzed with CORIMS, which is desirable for ECC
F. Cell Matrix Model design.
Naturally a model with a fixed number of physical cell
models may be applied to investigate MCU effects [35], [36]. G. MCU Classification
Such a method, however, has an inherent limitation on the
memory and speed of the simulations. As proposed in the MCBI experimental analyses [9], the fol-
We have developed a dynamic cell-shift (DCS) method to lowing MCU classification rules are also applied in CORIMS.
overcome such limitations. 1) MCU pattern is classified into three basic categories like
Fig. 7 shows the basic idea of the DCS method. a single line along BL (category “b”), a single line along
IBE et al.: IMPACT OF SCALING ON NEUTRON-INDUCED SOFT ERROR IN SRAMs
Fig. 8. Data pattern implementation in CORIMS. (a) Prepare a unit data
pattern matrix. (b) Spread the unit data pattern matrices onto the device.
Fig. 9. Examples of MCU categories and codes.
WL (category “w”), and cluster (an MCU that has two
or more bits along with both BL and WL directions;
category “c”).
2) MCU code that can be almost uniquely relevant to a
physical address pattern in an MCU is given as:
C_N1 _N2 _N3 _N4 _P
where
C category (b/w/c);
N1 MCU size(= N3 × N4 )
N2 bit multiplicity in an MCU;
N3 width in the BL direction (bits);
N4 width in the WL direction (bits);
P parity (A1: initial data in an MCU bits are all “1”; A0:
initial data are all “0”; MX: initial data are a mixture
of “0” and “1.”
Fig. 9 depicts examples of MCU categories and codes. An
MCU code can be almost uniquely assigned to a specific error
bit pattern as long as the MCU size is not too large. MCU
categories or codes can be very effective hints to identify the
underlying mechanism. As for MCBI, all “high”(data “1”)
nodes in the vicinity of the MCBI in the p-well fail so that very
specific error bit patterns appear depending on the data pattern
(A) FF or (B) CB as illustrated in Fig. 9.
1531
TABLE I
ASSUMED ROADMAP OF SCALING IN SRAM
H. Recycle Simulation Method
In extreme cases, CPU time may exceed several days. This
makes parametric survey study difficult in a wide scope. To
cope with this problem, CORIMS saves the virtual single events
with extremely low critical charge with certain input conditions
and reruns later to recycle them for parametric survey on the
effects of different critical charge, data pattern, and interleaving
within one hour CPU time.
I. Roadmap
Table I summarizes the typical roadmap parameters in
20–130 nm SRAM, assumed based on ITRS2007 [37]. Lateral
2-D scaling is assumed to reduce the area by a factor of 2
by each generation. Depth profile is assumed to be constant
due to something lacking in the roadmap information and
also because of the difficulty in making a shallow profile. As
parasitic capacitance is basically in proportion to a device area,
critical charge is also assumed to decrease by a factor of 2
by each generation. Although reduction in the supply voltage
Vdd is preferable for reducing power consumption, it is actually
being limited in order to ensure enough margin from the upper
bound of Vth variation [1] and therefore assumed to be constant.
The critical charge will decrease more rapidly if the Vdd is
reduced by generation, leading to an increase in SER.
J. Validation of SRAM Model
SRAM models in CORIMS have been validated to have less
than 20% variations from experimental data of 250–130 nm
SRAMs in a wide variety of neutron fields like field tests [38]
and accelerator tests in LANSCE [39], TSL [40], CYRIC [41],
and FNL [42]. Figs. 10 and 11 demonstrate such examples
of justification of 130 and 180 nm SRAM simulations with
measured data in quasi-monoenergetic neutron facilities and
three locations with different altitudes in Japan [38].
III. R ESULTS AND D ISCUSSIONS
A. Overall Trends
Major simulation results are summarized in Tables II and III
for the data pattern of CB and all “1,” respectively. The
maximum MCU size expands to the order of as many as
a million bits with the maximum MCU multiplicity of over
1532 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010

TABLE III
MAJOR SIMULATION RESULTS FOR THE DATA PATTERN ALL “1”

Fig. 10. Comparison of measured and simulated SER in 130 and 180 nm
SRAM with quasi-monoenergetic neutron facilities [26].

Fig. 11. Comparison of measured and simulated SER in 180 nm SRAM at

three different locations in Japan [26]. Fig. 12. Predicted trends in SER in SRAM.

TABLE II
MAJOR SIMULATION RESULTS FOR THE DATA PATTERN CB

100 bits in 22–32 nm generations. The ratio of MCU to SEU

will increase up to as high 50%.
It is noteworthy that the maximum MCU size and multiplic-
ity are statistically very rare, showing only rough trends with
Fig. 13.
generation.
Typical trends for SER/device and SER/Mbit are plotted for
the data patterns CB and FF in Fig. 12. Trends in MCU ratio
and the maximum MCU multiplicity are also plotted in Fig. 13
for the data patterns CB and FF. It is seen that:
(i) SER/Mbit increases drastically from 250 nm to 180 nm.
This is quite consistent with the observation that SER
in 4 Mbit SRAM increases drastically beyond that in
DRAMs, whose SER have been problematic until the
Predicted trends in MCU in SRAM.
late 1980s [43]. SERs in SRAMs decrease mildly from
130 nm down to 22 nm. The decrease is also quite
consistent with the recent experimental data [44].
(ii) Although SER/Mbit decreases beyond 130 nm,
SER/device increases by a factor of as much as 6 to 7 both
for CB and all “1” due to an intense increase in density.
(iii) MCU ratio and multiplicity increase exponentially as
scaling proceeds.
IBE et al.: IMPACT OF SCALING ON NEUTRON-INDUCED SOFT ERROR IN SRAMs
TABLE IV
PREDICTED TRENDS IN MCU CATEGORIES AND MCU CODES
(iv) There are only minor differences between CB and FF
data patterns.
Table IV summarizes the trends in MCU categories for data
patterns (a) CB and (b) FF. Typical MCU codes and the number
of unique codes are also shown in the table. The figures in
the cells are the ratio to the total MCUs in percentage. Most
MCU error patterns for MCU codes are shown in Fig. 9. Some
substantial differences can be seen between the data patterns:
(i) The ratios of the category W (on single WL) for CB
patterns are higher than those for FF patterns by a factor
of about 2. This is due to the two “high” nodes located in
the same p-well of two adjacent bits in the WL direction
for CB patterns so that two adjacent bits in WL direction
are easily corrupted. This is also seen in the ratios of the
MCU code W_2_2_1_2_any parity.
(ii) The ratios of the code C_4_2_2_2_A1 for FF patterns are
substantially higher than those for CB patterns.
(iii) The differences between the ratios of categories seem to
be clear for larger generations (180 and 130 nm). This
has been clearly observed in our former work for 180 nm
SRAMs [45]. The differences are getting unclear for
smaller generations. The reason for this, perhaps, is that
SRAM cells are easily corrupted by the charge deposited
only in the depletion layer as the critical charge becomes
1533
smaller and the memory cells are more tightly packed in
the smaller generations. The directional effects become
weak for smaller generations since the contribution from
charge collection by the directional funneling effects
become smaller.
When MCU bits align along with a single word line, multi-bit
upset (MBU), which corrupts error correction by ECC and thus
corrupts the reliability of electronic systems, may take place.
Such alignment can take place in the MCU categories (W) and
(C). Table V summarizes the ratio of such alignment in MCU to
the total SEU. In Table V, “Total” includes both the categories
(W) and (C), and the ratios are shown for bit widths of 2, 3,
4–8, and more than 8 bits in the (W) MCUs. It is seen that
almost all word line alignments take place in the category (W)
MCUs, and the bit widths for almost all (W) MCUs are less
than 8 bits. This means that an ECC with an 8-bit interleave can
eliminate MBUs with only a slight risk in 22 and 32 nm design
rules. Results for AllX are not shown here because they are
similar to those for CB.
The fact that MCU ratio drastically increases as scaling
proceeds means that multi-node upset (MNU), in which mul-
tiple logical nodes of sequential or combinational logic devices
are corrupted, must increase as well. This may cause serious
effects in the reliability design of logic devices since MNUs
1534 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010

TABLE V
PERCENT RATIO OF POSSIBLE MBU TO TOTAL SEU (CHECKER BOARD)

Fig. 15. Total charge deposition spectra for 22 nm and 130 nm SRAMs.

Fig. 14. Charge deposition density spectrum.

would make error detection impossible. This would make the

redundancy SER mitigation techniques extremely vulnerable
to MNU.

B. Charge Deposition Density for Secondary Ions

The frequencies of charge deposition density per unit track
length at the boundary of the storage node by secondary ions
are shown in Fig. 14 for proton, alpha particle, heavier particles
(atomic number is 10 or more), and total particles. Basically
there are no differences in the shape of spectra with generation Fig. 16. Distribution of distances of failed bits from nuclear reaction
positions.
with the maximum deposition density of about 110 fC/μm.
This means that any device which can tolerate the density of
110 fC/μm can be perfectly soft-error immune. Heavy ions 10 fC improves the susceptibility by one order of magnitude for
cause high-density (10–110 fC/μm) charge deposition, but each step for 22 nm SRAM since protons and alpha particles
their frequencies are relatively low. Lighter particles (proton play a major role when the critical charge is relatively low.
and alpha particle) play major roles for the deposition density The range in the collected charge becomes lower as scaling
below 10 fC/μm. proceeds.

C. Total Charge Collected to Storage Node

Fig. 15 shows the spectra of the total charge collected to the
storage nodes for 22 nm and 130 nm SRAMs. When the col-
lected charge exceeds the critical charge, SER takes places. In
contrast to the charge deposition density, there are differences
among different generations. The maximum collected charge
decreases from 130 nm SRAM (36 fC) to 22 nm SRAM (20 fC),
though the difference may not be that significant (16 fC).
By contrast, the soft-error susceptibility improves only
slightly when the critical charge increases from 5 fC to 10 fC for
130 nm, but the change in the critical charge of 1 → 2 → 4 →
D. Distance Distribution of Failed Bits
Fig. 16 summarizes the distance distributions of failed bits
from nuclear reaction locations. It is seen that:
(i) The maximum distance becomes longer as scaling pro-
ceeds, causing a decrease in the critical charge. As the
critical charge decreases, the contribution of light particle
increases, resulting in lon ager distance of failed bits.
(ii) The minimum distance becomes shorter as scaling pro-
ceeds. This is simply understood by the fact that the
distance can be shortened due to SRAM size shrinkage.
IBE et al.: IMPACT OF SCALING ON NEUTRON-INDUCED SOFT ERROR IN SRAMs
Fig. 17. Failed bit map for each generation with CB pattern.
Fig. 18. Changes in an SEU cross section in SRAM with scaling.
E. Failed Bit Map (FBM)
Fig. 17 shows the distribution of total failed bits in the BL
(perpendicular axis) and WL (vertical axis) address space when
about 58 000 nuclear reactions take place in the four bits near
the origin for the data pattern CB. It is seen that the area
densely affected drastically increases from 130 nm (about 50 ×
50 bits) to 22 nm (about 500 × 500). The automatic MCU
classification tool MUCEAC has been introduced to make the
statistic calculations from a number of MCUs and demon-
strated for mainly 130 nm SRAM test results [9]. The ex-
tremely widened range of FBMs, however, would make the
statistic calculations for MCU in neutron accelerated testing for
45–22 nm SRAM very painful or almost impossible unless an
ultra-high-speed automatic classification tool is developed.
F. Energy Dependency of SEU/MCU Cross Section
SEU and MCU cross sections for each generation are shown
as a function of neutron energy in Figs. 18 and 19, respectively.
As scaling proceeds, the contribution of neutrons with energy
lower than 10 MeV drastically increases due to an increase
in the contribution of lighter particles as the scaling proceeds.
Recent experimental results with low-energy protons showed
quite consistent trends with the predicted trends, where an SEU
cross section has a sharp peak for protons with energies lower
1535
Fig. 19. Changes in an MCU cross section in SRAM with scaling.
Fig. 20. Changes in the SBU cross section with scaling and neutron energy.
than 10 MeV [46]–[48]. This implies that two essential changes
may be needed in the standard methods, including JESD89A,
to estimate SER from accelerator-based testing. These two
changes are the following:
1) Include the contribution of neutrons with energy lower
than 10 MeV to avoid large errors in SER estimation
when the spallation neutron sources are us.
2) Modify the ordinary excitation function with the saturated
cross section to have a sharp peak at low neutron energy
when the (quasi-) monoenergetic neutron sources are
used.
By contrast, there are no essential changes in the MCU cross
section shapes. This can be attributed to the relatively low
contributions of lighter particles to the MCU. The sharp peak,
meanwhile, is understood to originate from single bit upset
(SBU), as shown in Fig. 20. The cross section curve for SBU
can be obtained by subtracting the MCU cross section in Fig. 16
from the SEU cross section in Fig. 14.
G. Trends in MCU Ratio
Fig. 21 shows the trends in MCU ratio to the total SEU.
The ratio generally increases as neutron energy increases and
scaling proceeds. When the neutron energy increases, heavy
ions with higher energy are produced, flipping multiple memory
cells. If the memory cells are packed more densely, the number
of flipped MCU bits is naturally increased. The maximum ratio
1536
Fig. 21. Changes in MCU ratio with scaling and neutron energy.
Fig. 22. Changes in MCU multiplicity distributions with scaling.
exceeds 0.5 for 22 nm SRAM, indicating that the impact of
MCU and MNU has become more serious.
H. Trends in MCU Multiplicity Distribution
Fig. 22 shows the changes in MCU multiplicity distributions.
It is seen that the multiplicity shifts to a larger number of bits
as scaling proceeds. The ratios of SBU and lower multiplic-
ity MCUs reduce correspondingly. As mentioned before, the
maximum multiplicity is well beyond tens of bits when scaling
proceeds beyond 32 nm.
I. Validity of Simulated Results
In the present model, the depth profile of impurities and the
maximum funneling length are fixed for all generations. But in
reality the depth profile will be shallower. The funneling length
will also be shorter as the concentration of impurities become
higher. These effects would work for suppressing SER. On the
other hand, the operation voltage may be reduced in reality as
scaling proceeds. This works for worsening SER.
Changes in the material in the device would make wider
variations in the prediction. If the high-k material is used for
gate oxides like HfO, the critical charge is increased to result
in lower SER. Meanwhile if the low-k material is used for
interlayer oxide, parasitic capacitance is reduced to result in
lower critical charge and higher SER.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 7, JULY 2010
The bipolar effects, which are not implemented in CORIMS
at present, are somewhat in the tradeoff relationship with the
charge collection mode. When the operation voltage is reduced,
the bipolar mode would decrease. When the p-well’s size is
shrunk, the charge collection mode would be minor, but the
bipolar mode would be activated due to the shrinkage of the
distance of the p-n junctions. Even when the bipolar effects are
implemented in the CORIMS model, the total trends may not
differ that significantly. This point will be more clearly shown
in future works.
J. Insights in the Impact on Logic Devices and
Approaches for Mitigation Design
It is reported by several researchers that SER in logic devices
will have serious impacts on components, including the PLL
[49], clock line [8] or global control line (SET/RESET) [50] in
electronic systems. As mentioned before, MNU is apparently a
major setback in reliability design of logic devices and systems,
in particular, with redundancy cells and modules.
In order to establish any valid countermeasures for logic
systems, the following approaches should first be established
first:
(i) Techniques to identify vulnerable components. Neutron
irradiation tests in system or component level [51], [52]
would be useful. Identification of vulnerable parts can
also be done by using high-energy ion beams [53].
Broad-beam neutron irradiation facilities such as FNL,
ANITA [54], and TRIUMF [55] can be utilized for such
system/component-level tests.
(ii) Techniques to quantify the vulnerability in gate (flip
flops, latches, AND, NAND, NOR, OR, etc.) level. Gate
chain irradiation tests [56], [57] would be useful. Simu-
lation and design tools like CORIMS, in which realistic
device structures are implemented, can also be applied.
With this kind of knowledge, intrinsic immune devices or
more effective redundancy techniques with low power and costs
have to be established before 32–22 nm eras.
IV. C ONCLUSION
Trends in terrestrial neutron-induced soft-errors in SRAMs
down to 22 nm process are predicted by using the Monte-
Carlo simulator CORIMS, which is validated to have less than
20% variations from experimental data in a wide variety of
neutron fields like the low- and high-altitude field tests and the
accelerator tests in LANSCE, TSL, and CYRIC.
The following results are obtained:
1) Soft-error rates per device in SRAMs will increase x6-7
from 130 nm to 22 nm process.
2) As SRAM is scaled down to a smaller size, SEU is dom-
inated more significantly by low energy neutrons (< 10
MeV). The MCU, however, does not change drastically.
3) The area affected by one nuclear reaction spreads well
beyond 1 M bits area and the multiplicity of multi-cell
upset become as high as 100 bits and more.
The discussions are extended to the MNUs of logic devices/
systems and countermeasures to them.
IBE et al.: IMPACT OF SCALING ON NEUTRON-INDUCED SOFT ERROR IN SRAMs
ACKNOWLEDGMENT
We would like to thank Profs. Emeritus T. Nakamura and
M. Baba of Tohoku University for helpful discussions and for
their support for the database on nuclear reactions.
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Source for Accelerated SEE Testing at The Svedberg Laboratory,” in ing standards and validate simulation results by us-
Proc. IEEE Radiation Effects Data Workshop, Quebec City, QC, Canada, ing worldwide accelerater facilities. He contributed
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and mitigation in ultra-deep submicron technologies,” in Proc. ICICDT, Electronics and Information Technology Industries Association. His current
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estimated from SET pulse-width measurements,” IEEE Trans. Nucl. Sci., Ken-ichi Shimbo is currently a Researcher in
vol. 56, no. 6, pp. 3180–3184, Dec. 2009. the Production Engineering Research Laboratory,
Hitachi, Ltd., Yokohama, Japan. He studies fault
diagnosis technology and terrestrial neutron-
induce soft-error analysis in FPGAs and network
components.

Eishi Ibe (M’99–SM’06–F’08) received the B.S. de-

gree in physics from Kyoto University, Kyoto, Japan,
in 1975, and the Ph.D. degree in nuclear engineering
from Osaka University, Osaka, Japan, in 1985.
He joined the Atomic Energy Research Labora-
tory, Hitachi, Ltd., Yokohama, Japan, in 1975. He
is currently a Chief Researcher in the Production
Engineering Research Laboratory, Hitachi, Ltd. He
was a Research Fellow of the California Institute of
Technology from 1986 to 1987. He has contributed
to a number of IEEE Journals and conferences as a
Tadanobu Toba is currently a Senior Researcher
program committee member or as a reviewer and/or an author in the fields of
neutron-induced error. He has authored more than 50 international technical in the Production Engineering Research Labora-
tory, Hitachi, Ltd., Yokohama, Japan. He studies
papers and presentations, including 17 in the field of terrestrial neutron-induced
fault diagnosis technology and terrestrial neutron-
soft-error of semiconductor devices.
induce soft-error analysis. He belongs to the Insti-
Dr. Ibe was a member of the advisory committee of the MIT nuclear reactor
laboratory from 1990 to 1993. He is the Asia/Pacific Chair of the JESD89 Task tute of Electronics, Information and Communication
Engineers (IEICE).
Group by which new standard testing methods on neutron-induced soft-error of
semiconductor devices are issued based on international consensus. In 2008 he
was elected as an IEEE Fellow for contributions to neutron-induced soft-error
analysis for semiconductor memory devices.