430 Document

Design:

The Architecture includes various components :

1. Program Counter
2. PC Adder
3. Instruction memory
4. Registers
5. Data memory
6. Arithmetic Logic Unit
7. ALU Control
8. Control Unit
9. Sign Extend
10. Shift Left – 2
11. Adders
12. Multiplexers
13. Concatenation unit
14. Logic gates

At reset the PC is initialized to 0x00400000 value.

ALU Design:

The different ALU operations depend on the Control inputs from the ALU control.
1. 0000 – AND operations
2. 0001 – OR Operation
3. 0010 – ADD Operation – as in Load and Store instructions
4. 0110 – SUB Operation – as in BEQ and BNE instructions
5. 1100 – NOR Operation
6. 0111 – SLT – Set if less than
7. 1000 – Shift left Operation
8. 1001 – Shift right Operation

When the ouput is zero the Zero output bit is set to '1'.

ALU Control : The functionality of the ALU Control depends on the ALUop from the
Control Unit and/or on the Function Code (bits 5 – 0) of the instruction and the
corresponding ALU Control output bits are set.

ALUop has been set to 3 bits to support for many instructions.

When ALUop – 000 it is a Load or a Store (LW or SW) instruction and ALU Control
lines are set to 0000.

When ALUop – 001 it is a BEQ / BNE instruction and the ALU Control lines are set to
001

When ALUop – 010 then it is a R-Format instruction, hence the ALU Control lines
depend on the function code ( bits 5 – 0) of the instruction. R-Format instructions include
add(32), sub(34), and(36), or(37), slt(42), sll(0), srl(2), jr(8). According to these function
codes the ALU control lines are set.

When ALUop – 011 then it is an ANDI operation and the control lines are set to 0000.

When ALUop – 100 then it is an ORI operation and the control lines are set to 0001.

When ALUop – 101 then it is an SLTI operation and the control lines are set to 0111.

We have used another output called the alujr from the ALU Control unit the use of which
is described in the next topic (Control Unit). The Alujr bit is set to '1' only if the
instruction is “jr” .

Control Unit:

The design of the control unit is the most important part of designing the architecture.
The control unit takes the bits 31-26 of the instruction( the output of the instruction
memory) and depending on those bits it sets the output signals.

The control unit has 10 outputs.

1. RegDst – chooses the destination register to write into.
2. Jump – signals a jump instruction.
3. Branch – signals a Branch instruction
4. MemRead – is set is there is any data to be read from the Memory Unit.
5. MemtoReg – chooses the data to be written to the destination register.
6. ALUop – 3 bit output to the ALU Control Unit to signal which instruction it is.
7. MemWrite – is set if there is any data to be written into the memory.
8. ALUSrc – choose the source of data to the ALU
9. RegWrite – is set if there is any data to be written into a register.
10. Branchne – is set only if the instruction is BNE. ( The use of which is described
later )

Depending on the input ( OpCode ) to the Control Unit these above bits are set to 0s and
1s.

If the instruction Opcode is – 000000 – it is of R-Format (add,sub,or,srl,sll,jr,slt,and).

MemtoReg is 00
If the instruction Opcode is – 001000 – it is an ADDI instruction ( I Format). ALUop is
000. MemtoReg is 00

If the instruction Opcode is – 001100 – it is an ANDI instruction ( I Format). ALUop is

011.
MemtoReg is 00

If the instruction Opcode is – 001101 – it is an ORI instruction ( I Format). ALUop is

100.
MemtoReg is 00

If the instruction Opcode is – 001111 – it is an LUI instruction. ie. Load Upper

Immediate. At this point a small change has to be made to the design. The component
added is a Concatenation unit. This allows us to concatenate 16 zeros to the 16bits ( 15 –
0 ) of the instruction and make it a 32 bit value. This is when the Multiplexer to choose
the data to be written to a register becomes 3x1. Hence the signal MemtoReg is = '10' (2).

If the instruction Opcode is – 100011 – it is LW – I Format. ALUop is 000. MemWrite is

0.

If the instruction Opcode is – 101011 – it is SW – I Format. ALUop is 000. MemWrite is

1.

If the instruction Opcode is - 000100 – it is BEQ – I Format. Branch is 1, Branchne is 0.

ALUop is 001.
Branch signal is set to 1 and the ALU operation is SUB. So if the values are same the
ZERO output bit from the ALU is set to 1 and the AND of Branch and ZERO is a 1.

If the instruction Opcode is – 000101 – it is BNE – I Format. Branch is 0. Branchne is 1.

ALUop is 001.
For a BNE instruction also the operation performed in the ALU is Subtract, as a result the
ZERO output bit is set to 0 and no 1. Hence a separate component has to be designed to
support both BEQ and BNE. This is when the signal Branchne from the Control Unit is
used. According to out design when BNE instruction is given the Branchne signal is set
to 1 and even though ZERO bit is 0, Branch takes place.

If the instruction Opcode is – 000010 – it is J instruction – J Format.

If the instruction Opcode is – 000011 – it is JAL – J format but PC+4 has to be written
into $ra. Hence for this there is a small modification in the design. To write into $ra we
give another input to the multiplexer that chooses the register to be written into. Hence
the multiplexer is now 3x1 and RegDst signal is 2 bits - 10. To select PC+4 to be written
into the destination we make the Multiplexer which chooses the data to be written into
the register as 4x1 and the forth input to it is the value PC+4 and MemtoReg = 11.
If the instruction Opcode is – 001010 – it is SLTI – I Format. ALUop is 101.

The final change that is to be made in the design is for JR instruction – R Format. In this
instruction the address to jump to is chosen from $ra. That is 'rs' in the instruction. Hence
to choose this we need to give another input to the multiplexer and hence made 3x1 and
to choose this at the multiplexer another output line from ALU Control is given – alujr
and is set to 1 for a JR instruction and 0 for all other instructions.

Changes to multiplexers :

Few changes to the multiplexers have been made.

1. The multiplexer to choose the Write data has been made a 4x1 multiplexer.
The inputs are Data read from Data Memory, ALU output, PC+4(for JAL)
and the output of the concatenation unit.
2. The Multiplexer which chooses the Register Destination has been made 3x1.
The inputs are rt, rd and 31($ra).
3. One of the multiplexer which chooses the value to be written into the PC has
been made 3x1. The inputs are PC+4, rs(for jr instruction) and Branch target
address.

ALU :

The implementation in the ALU depends on the ALU Control Lines from the ALU
control Unit.

The complete Architecture, State Tables and the simulation results have been provided.
Test Benches for each module/component have been used to check the functionality of
the component.

A Sample MIPS Code has been used as a test input.