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 IEEE 2018 -2019 VLSI PROECT TITLES & ABSTRACTS
IGTV01 TITLE: Design and Implementation of Low Power and High Performance
Network Interface for 2x2 SDM based NoC

Abstract -As VLSI technology growing exponentially, silicon chips can

accommodates more cores on chip this will lead to very high computational
power but poor communication among on-chip processors and memory. To
overcome this we proposed spatial division multiplexing based network-on-chip
with modified network interface. Proposed network interface provide high
throughput with optimized area and consume very low power. We have evaluated
proposed SDM based NoC (Network-On-Chip) with high performance network
interface for 2x2 network which occupied only 4% of resources on Xilinx
spartan6 SP605 FPGA. We modeled the network interface using VHDL and
multicore platform is prepared by using Xilinx EDK and verified
computationally complex application at 88.6MHz processor frequency but
achieved high throughput.

IGTV02 TITLE: Asynchronous Interface FIFO Design on FPGA for High-

throughput NRZ Synchronisation

Abstract—Networks-on-chip (NoCs) have become a new chip design paradigm

as the size of transistors continues to shrink. Globally-asynchronous locally-
synchronous (GALS) on-chip networks are proposed for solving issues such as
large clock tree distribution and signal delay variations. More interestingly, for
the GALS networks using m-of-n delay-insensitive interconnect,
The asynchronous interconnect not only can be used for on-chip interconnection,
but also provides a simple, direct and power saving solution for off-chip
interconnection. This paper presents an asynchronous interface FIFO design to
improve throughput over asynchronous inter-chip links using2-of-7 Non-Return-
to-Zero (NRZ) encoding in an existing many core system. The proposed design is
suitable for implementation on commodity FPGAs without using the limited
global clock buffer resources, but involves using the FPGA to implement
Asynchronous circuits. The interface FIFO is constructed from the transition
detectors themselves rather than by employing a separate buffer in the more
conventional fashion. The proposed Solution has been demonstrated in an existing
system and is suitable for adaptation to other asynchronous m-of-n NRZ coding
protocols for high-throughput communication.

IGTV03 TITLE: An Efficient Logic Obfuscating Strategy for Hardware Security

Using SIC Generator
Abstract- The fast increment of ICs configuration has brought an historical change
in the industry. A numerous attacks such as counterfeiting, reverse engineering
and IP theft occurs in ICs. For the security of ICs, a logic obfuscating method is
implemented. Logic obfuscation conceals the functionality by embedding extra
keys into the original design. The keys embedded for the obfuscation are called
key-gates. The extra gates ought to display its right performance (i.e. produces
correct yields), so substantial key must be provided to the obfuscated design.
Single Input Changing Generator (SICG) is utilized to produce the sequence of
key values. The SICG is additionally associated with the contribution to create the
info values for Built In Self-Testing (BIST testing).
IGTV04 TITLE: A Binary High Speed Flooting Point Multiplier

Abstract— Objective: To implement an improving the speed of Floating Point

MultiplicationMethods/Statistical analysis: Recursive Dada alogiritham is used
for implementing the floating point multiplier IEEE 754 single precision binary
floating point representation used for representing Floating Point number for
multiplication of mantissa Carry Save multiplier used is replaced by by Dadda
multiplier for improving the speed. using verilog HDL multiplier is implemented
and it is targeted to xilinx vertex-5 FPGA.
Improvements:The speed of operation is increased by compared with Carry Save
Multiplier. The multiplier which we developed handled both overflow and
underflow cases.

IGTV05 TITLE: Implementation of Power Efficient 8-bit Reversible Linear Feedback

Shift Register for BIST

Abstract--Built-in Self Test (BIST) is more appropriate for testing any VLSI
circuits as it provides a larger range for low power applications. Test pattern
generator is the vital module in BIST. Linear Feedback Shift Registers
(LFSR) is broadly used in BIST for generating test vectors as it produces
highly random test pattern. This paper mainly aims at design and
implementation of power efficient LFSR using reversible logic for low power
applications. Pareek Gate is used to implement reversible D Flip Flop (DFF).
8 bit reversible LFSR is implemented using 8 DFFs, 8 Feynman Gates (FG)
and 3 Double Feynman Gates (DFG).It is found from the analysis that, the
proposed approach of designing reversible LFSR reduces the power by 10%
when compared to conventional design. Thus the proposed design can be
used for designing BIST in low power applications.

IGTV06 TITLE: Design of Radix 2 Butterfly Structure using Vedic multiplier and
CLA on Xilinx

Abstract- FFT (Fast Fourier Transform) and IIFT (Inverse Fast Fourier
Transform) structure plays very critical role in designing of digital signal
processing. These structures are most commonly implemented on Application
Specific Integrated Circuit (ASIC) for high performance. Butterfly structure is the
basic unit of FFT and IIFT implementation. Each butterfly unit consists of
complex multiplication and addition. Efficient implementation of these
component plays very critical role in design of butterfly structure. Vedic
Multipliers is one of the fastest and low power multiplier over corresponding other
multiplier such as array and booth multipliers. This paper describes the design of
butterfly structure using Vedic multiplier and CLA (Carry look Ahead adder) on
Xilinx ISE Design suite 14.7 (FAMILY SPATAN 3E AND DEVICE
XC3S1200E) platform and compared the same with other technique such as with
RADIX-4 booth multiplier, RCA (Ripple Carry Adder).

IGTV07 TITLE: Design of an area-efficient multiplier

Abstract—The extensive improvement in the VLSI technology results in

optimization of various factors, at the same time causing overhead in area, delay
etc. Multipliers being the integral part of major application systems like Digital
Signal Processor (DSP), Microprocessor and Application Specific Integrated
Circuits (ASIC'S) plays a major role in the overall area, power consumption and
 performance of the processor. Multipliers consuming less power, occupying less
area, with high processing Speed are in demand. This paper proposes an 8*8
hybrid tree multiplier by combining Booth-encoding, Wallace and Dadda
methods. The design is simulated in Xilinx ISE 14.7 and analyzed in Cadence
Virtuoso software. The result shows that the proposed multiplier occupies 10.4%
less area than the existing multiplier.

IGTV08 TITLE: A Survey Paper on Modern Technologies in Fixed-Width Multiplier

Abstract—The vital element of the DSP processor is Multiplier unit. The main
objectives of the DSP processor are speed, power, delay and area. These goals
have been realized with fixed-width multiplier whose output bits equal to input
bits. The fixed-width multiplier implemented DSP processors can be applied for
audio signal processing, video signal processing, VLSI signal processing, speech
recognition, digital communication, medical imaging, MRI, MP3 and so on..
Many researchers are optimizing, the performance of the multiplication process.
In this review paper, the technologies to achieve the objectives of the DSP
processor have been studied. And also the most recent developments in the
multiplier circuit have been discussed. In this paper, first, the brief background of
the fixed-width multiplier is outlined. Then, several multiplier architectures
proposed for MAC (multiplier-accumulator) presented, narrating their functioning
principles and key features. To provide a perception into future research
directions, open research issues are discussed at the completion of this paper.

IGTV09 TITLE: A Novel Design of Low power and High speed Hybrid Multiplier

Abstract -This paper presents the design of a rounded, truncated hybrid multiplier.
The maximum absolute error is ensured to be less than one unit of least position.
The proposed strategy includes deletion, reduction of partial product bits of
multiplier in order to reduce the number of full adders and half adders used during
partial product reduction. The high speed computing system requires high-speed
and low-power multipliers. This paper proposes a high performance hybrid tree
multiplier by using both Wallace and Dadda methods in partial product reduction.
The partial products are separated into four groups. Dadda reduction is used in
group1 and group4, whereas Wallace tree reduction method is used in the
remaining groups. Additionally, the Ling adder is incorporated in the proposed
hybrid multiplier in the final stage, to reduce the final carry propagation delay.
The design is implemented, simulated and evaluated using H-SPICE tool with
32nm CMOS predictive technology model(PTM).

IGTV10 TITLE: Robust High Speed ASIC design of a Vedic Square Calculator using
ancient Vedic Mathematics

Abstract—This paper proposed a design of a new square calculator using the

ancient Vedic mathematics for Application Specific Integrated Circuit (ASIC).
This is a robust and novel approach to design the Vedic calculator. The squaring
of a number is the procedure of self-multiplication. The ancient Vedic
mathematics has a set of 16 sutras & 13 sub sutras. In this paper, the sutra ‘Urthava
Triyakbhym’ and ‘Nikhilam Navatascaramam Dasatah’ is used to find out the
square of an integer number quickly. The circuit design in this regard has been
proposed here and is possibly the simplest one yet so far. Simulation of the circuit
has been carried out using Xilinx ISE software.
IGTV11 TITLE: Implementation of the LZMA Compression Algorithm on FPGA

Data compression technology is the necessary technology in the age of big data.
Compared with software compression techniques, hardware compression
techniques can improve speed and reduce power consumption. LZMA is a lossless
compression technology, and its hardware implementation has broad application
prospects. This paper proposes a novel high-performance implementation of the
LZMA compression algorithm capable of processing up to 125Mbps on a Virtex-
6 FPGA chip. Then presents a typical application and its compression
performance for a specific data sample.

IGTV12 TITLE: Methodology for Design of Optimum NOC Based On IPG

Abstract - High performance embedded applications are developed using system-

on-chips (SoCs) which in turn include silicon intensive, integrated application
processors. These SoCs integrate multi-core processor (i.e., ARM Cortex9 or
A15) with variety of memory interface controllers, communication interface
controllers and special purpose accelerators. Traditionally bus matrix is used for
integrating these intellectual properties - cores (IPs). Bus based architectures are
not scalable and consume more area and power, which has fueled design of
network on chip (NOC). A customized NOC is further more efficient. In this
paper, a methodology for customized NOC architecture is introduced considering
various aspects of NOC as well as the SoC. Policies for optimizing Bandwidth
requirement, size of the IP (area or gate count), lP location for optimum path
lengths are discussed. Policies in turn form methodology for optimum NOC.As
IPs in SOC increase in numbers, NOC for interconnecting every IP may result in
over networking. Sometimes, performance of router is underutilized. On the other
hand, for closely coupled IPs direct port to port connections are suitable than NOC
as they communicate heavily. IPs which talk one at a time are grouped together
and common local bus architecture is suitable for them. Outside group they talk
through NOC. Or routers with less number of ports gives better results. Proper
grouping and layout will reduce complexity. Here I am proposing a methodology
for handcrafting NOC among Intellectual property core groups (IPGs), inside and
outside of the groups. Final outcome is, reduced number of routers required and
optimized physical design of SoC.

IGTV13 TITLE: Testing of FIFO Buffer of NoC Router using Bist

Abstract: Systems on-Chip (NoC) has created as a promising answer for on-chip
interconnection in SoC because of its adaptability, reusability, adaptability and
parallelism. It is important to identify and rectify the fault in the Network on Chip.
Testing is an important process to find and rectify the fault in Network on Chip.
In testing, FIFO buffers produce high throughput gain as well as reduce latency.
BIST (Built in Self-Test) is used for testing the routing process. BIST strategy is
used for testing the NoC interconnect network and investigates if the strategy is a
suitable approach for the task. The intention is to custom BIST to detect faults and
to be able to pinpoint the location of each defect and finally use this information
to reconfigure the architecture. Periodic testing of buffers avoid accumulation of
faults and also allows test of each location of the buffer. The periodic testing of
FIFO buffers do not have much effect on the overall throughput of the NoC,
except when buffers are tested also frequently and this implementation is done in
Xilinx.
IGTV14 TITLE: A Novel Logic Locking Technique for Hardware Security

Abstract- Due to globalization of IC, hardware is defenseless to new sorts of

assaults, for example, counterfeiting, figuring out and IP piracy. Logic locking
technique is used for the hardware security. Logic locking conceals the
functionality and implementation of a design by inserting additional gates into the
original design. The gates inserted for the locking are called keygates. To display
its correct functionality (i.e. produces correct outputs), valid key has to be
provided to the locked design. Pseudo Random Number Generator (PRNG) is
utilized to randomly generate the sequence of key values. The PRNG is also
connected with the input to randomly generate the input values for automatic
testing (BIST testing). This approach increases security level and hence applied
in a cryptographic algorithm. Montgomery algorithm is the cryptographic
algorithm which will be tested by the logic locking technique.

IGTV15 TITLE: Design of Efficient Programmable Test-per-Scan Logic BIST

Modules

Abstract—This paper focus on the design of Programmable Logic BIST structures

for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The
advancements happening in VLSI technology day by day have made chip testing
more complicated. This has paved way for the increased popularity of Logic Built
In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST
allows self testing of chips with the help of an additional built-in hardware
structure inside the circuit. Test-per-scan Logic BIST structure includes Test
pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role
of test pattern generator in Logic BIST since it is more efficient than binary
counters. MISR is commonly used as an output response analyzer which acts as
an alternative to n-parallel LFSRs. Comparator compares the responses stored in
ROM and MISR output. Reconfigurability is added to every structural element in
BIST to improve the fault coverage of IC testing. The proposed structural
architecture is simulated in Modelsim RTL simulator. The different sized (16, 32,
48) programmable structures in Logic BIST were synthesized in Xilinx Spartan
3E and Spartan 6 for implementing them on FPGA. Four structural representations
such as Modular, Standard, Hybrid and Complete form were implemented for
PRPG and MISR design. All the designs were synthesized in ASIC in RTL
compiler using 90nm standard cell technology library. The results of the proposed
programmable PRPG and MISR designs were analyzed for speed, power and area
with the equivalent modules generated by third party sign-off tool.

IGTV16 TITLE: Design of Optimized MAC Unit using Integrated Vedic Multiplier

Abstract— Multipliers are core components of most of the digital signal

processing algorithms which lie in critical delay path and decide performance of
any algorithm. Over the years various approaches have been proposed to reduce
the computational overhead of conventional multipliers. Vedic mathematics has
been one among them. In this paper, a novel multiplier unit is proposed which
integrates the advantage of each of the sutras. “Sampoornam” alias “Absolute
vedic” multiplier is designed to have a specialized logic unit that decides which
multiplier is to be used for optimum results based on the types of input, improving
efficiency. The proposed multiplier Sampoornam is used for designing a 4-bit
Multiplier accumulator unit (MAC) unit and is extended up to 64-bit using Vedic
scaling technique. Sampoornam is comparatively time efficient than the present
day multipliers such as (a*b) algorithm, Booth and Wallace. The 4-bit MAC unit
 developed using sampoornam has 25 % reduction in time delay compared to MAC
developed using Wallace multiplier. Similar trend is observed as the number of
bits is increased.

IGTV17 TITLE: Implementation of BIST Technology for Fault Detection and Repair
of the Multiported Memory using FPGA

Abstract-The problem of faults is growing exponentially due to embedded

memory area on-chip is increasing and memory density is growing. There are two
types of memory single port and multiported comparing these two memories
multiported memory have ability to support more efficient execution of operation
and high speed performance. Built-in self test is used to detect and repair the faults
in multiported memory. The microcode based Asynchronous p-MBIST is
implemented using FPGA and compared with similar feature Synchronous P-
MBIST.

IGTV18 TITLE: High Speed Vedic Multiplier Used Vedic Mathematics

Abstract— Multiplier is main building block of all processor, which improves the
speed of Digital Signal Processor (DSP). In special application in which we need
to reduce the time delay. In proposed method, we design a Vedic multiplication
algorithm by using Vedic mathematics formula Urdhava Tiryakbhyam method
means vertically and cross wise. Vedic mathematics is mainly based on 16 Sutras
and was rediscovered in early 20th century. In ancient time in India, people used
this Sutra for decimal number multiplications effectively. The same basic concept
of Vedic mathematics is applied to multiplication of binary number to make usable
in the digital hardware system. The speed of the computation process is increased
and the processing time is reduced due to decrease of combinational path delay
compared to the existing multipliers. In our proposed multiplication algorithm, we
get less time delay compared to other algorithms.

IGTV19 TITLE: An Efficient Built-In Self-Repair Scheme for Multiple RAMs

Abstract— Vast advancements in the semiconductor domain, approach of

integrated chip design, availability of many integrated circuit (IC) packaging
strategies and efficient IC test techniques have efficiently contributed towards the
incorporation of entire system on one chip (SOC). The increasing trend of SoC
technology, highly reliable embedded memories having high density and good
yield are required for effective implementation of the system. While
manufacturing a chip, yield improvement of the memories is one important aspect
that one has to consider. In todays SoCs, a huge percent of the chips area is utilized
by memories. So memories as they are designed and optimized as per the limits
of the technology, are often prone to failures. It is crucial for the SoC products
that the memory cores should be reliable and should provide a reasonable level of
yield. This is the reason why a Built-In Self-Repair Technology is earning
importance. Built in self repair (BISR) methodology is an efficient self repair
technique that can be used in the repair process of the memories (RAMs).
Repairing of memories is necessary, because just detecting errors is no longer
sufficient for SoCs, therefore both diagnosis and repair techniques are required. If
each RAM in an SOC possess its own dedicated BISR (DeBISR) circuit, results
in large area consumption. Such a dedicated in built repair technology for each
RAMs in SOC also leads to high cost. In that case it is significant to have a Re-
Configurable Built in Self Repair (ReBISR) circuitry which can be shared by
 multiple RAMs and hence the total area and cost of BISR circuits in an SOC can
be drastically reduced. In this work a Re-configurable Built in Self Repair
(ReBISR) that can repair multiple RAMs by incorporating both 2-D and selectable
redundancy is presented . TPG used for generating memory address is the
complete linear feedback shift register (CLFSR) which consumes much less area
compared to any other address generation unit. March C- algorithm is used as the
testing algorithm as it provides sufficient fault coverage with minimum test length.
The defective RAMs are allocated to non-defective redundant elements using an
effective algorithm called redundancy allocation algorithm. The three basic
building blocks are; A Repairable RAM, BIST module and a BIRA module.
Xilinx ISE 14.2 is used to implement.

IGTV20 TITLE: VLSI Design of Fixed Width 2’s Compliment Multiplier

Abstract— This paper focus on fixed width, parallel multiplier design in which 8
least significant columns of the partial product array are truncated. It takes the two
n-bit numbers as input and generates a n-bit product as the output. Baugh-Wooley
multiplier is preferred for 2’s complement multiplication. In the design, three
multiplication modules are used to generate the desired output. All these modules
use the combinational blocks. The parallel operation reduces delay effectively.
The high performance of the circuit is achieved by replacing the designing
components with the more efficient one. The performance evaluation of 2’s
complement fixed width multiplier using Spartan-3, Spartan-6 and Virtex-5
families available from Xilinx is made. Simulation is done to check the
functionality of the design.

IGTV21 TITLE: Implementation of AES algorithm using VHDL

Abstract — The Advanced Encryption Standard (AES) postulates a cryptographic

procedure approved by FIPS to safeguard data in electronic form. AES algorithm
is a symmetric block cipher that can be used for encrypting (encipher) and
decrypting (decipher) data. The Advanced Encryption Standard was accepted as
an up gradation after the previously used Data Encryption Standard (DES) was
found to be weak due to its small key size and technical advances in processor
power. Out of the fifteen algorithms in contention Rijndael was selected as the
new standard for encryption. Two Belgian inventors, Joan Daemen and Vincent
Rijmen collaborated to establish the name of Rijindael. It being a block cipher, its
mechanism is on permanent length group of bits, called blocks. An input block of
a assured size, usually 128 bits, is taken and an equivalent output block of the
same size is produced. A secret key acts as second input of lengths of 128, 192 or
256 bits. Basically AES adopts a substitution-permutation set-up, which
concatenates a series of mathematical operations that use substitutions with
known values and combination of transformation in a permuted iteration in such
a way that each input bit manipulates every output bit. Here we explore the steps
in AES and its implementation on FPGA using VHDL.FPGA is the best platform
which specializes in fast iterative process using least devices.
IGTV22 TITLE: Design and Performance Analysis of modified Unsigned Braun and
Signed Baugh-Wooley Multiplier

Abstract –Adders and Multipliers play a vital role in the functioning of various
systems used in communication and signal processing. Baugh Wooley and Braun
multipliers employ parallel architecture and hence they are the most frequently
used multipliers for signed and unsigned operations. In any system design, the
three main constraints which determine the performance of the system are speed,
area and power requirement. This work involves design and implementation of
modified Baugh-Wooley and Braun multipliers for signed and unsigned number
multiplication respectively and analysis with respect to speed and power
consumption of the designed multipliers. The adder is designed using three
different logics, namely, Basic CMOS, Domino and Split Path Data Driven
Dynamic Logic (SPD3L). The designed adder is then used to construct the
multipliers. An improvement in power and reduction in delay is observed for both
the designed multipliers.

IGTV23 TITLE: An AES-GCM Authenticated Encryption Crypto-Core for IoT

Security

This paper describes a design of AES-GCM authenticated encryption (AE)

crypto-core suitable for IoT security applications. The AES-GCM core provides
confidentiality by Counter (CTR) mode of block cipher AES, and it also provides
integrity and authenticity by GHASH. AES encryption supports two key lengths
of supports key length of 128 and 256-bit. In order to optimize the overall
performance, GHASH block was designed to perform Galois field multiplication
in 11 clock cycles, resulting in the number of clock cycles between AES
encryption and Galois field multiplication are matched. The AES-GCM core was
verified by FPGA implementation, and it occupies 35,352 gate equivalents (GEs).
The estimated throughput is 332 Mbps with maximum clock frequency of 140
MHz.

IGTV24 TITLE: Optimized BIST Architecture for Memory Cores and Logic Circuits
using CLFSR

Abstract— Built-In Self-Test is a design for testability method for testing

embedded circuits. It provides simple automated test procedures to detect faults
in Memory Cores and logic circuits in a system. This paper describes a model of
BIST structure that can be used as Memory BIST or Logic BIST. For testing a
logic circuit we need test vectors. In the case of memory testing, addressing
sequences in addition to the test vectors are required. In this paper an alternative
method is used for the generation of both address and test data with less hardware
complexity. This is achieved by modifying Linear Feedback Shift Register to a
structure known as Complete Linear Feedback Shift Register (CLFSR). With
CLFSR, all possible combinations of ones and zeros can be generated. This feature
enables it for using in Memory BIST and Logic BIST structures. Hence, a CLFSR
structure can be used to develop less complex BIST architecture. Functionality of
CLFSR and BIST structures are verified using Xilinx ISE 14.2.
IGTV25 TITLE: Fault Aware Adaptive Routing Algorithm for Mesh based NoCs

Abstract — In this paper, we present a modified fault aware routing algorithm for
on-chip communication that detects precise locations of the faulty nodes and
faulty links on the network and routes the data by bypassing the faults. The
proposed routing method is based on recursive error detection mechanisms and
provides adaptive routing path from source tile to destination tile in the dynamic
NoCs environment where the position and number of faulty nodes/links alter
during runtime. We also compare our proposed routing algorithm with other
existing fault-tolerant routing algorithms such as XY, fault tolerant XY and
dynamic adaptive, considering latency, throughput and number of packets lost as
performance metrics. The results show that the proposed routing algorithm results
in lesser packet loss and higher throughput in case of node or link failures.

IGTV26 TITLE: Efficient Design-for-Test Approach for Networks-on-Chip

Abstract—To achieve high reliability in on-chip networks, it is necessary to test

the network continuously with Built-in Self-Tests (BIST) so that the faults can be
detected quickly and the number of affected packets can be minimized. However,
BIST causes significant performance loss due to data dependencies. We propose
EsyTest, a comprehensive test strategy with minimized influence on system
performance. EsyTest tests the data path and the control path separately. The data
path test starts periodically, but the actual test performs in the free time slots to
avoid deactivating the router for testing. A reconfigurable router architecture and
an adaptive fault-tolerant routing algorithm are proposed to guarantee the access
to the processing core when the associated router is under test. During the whole
test procedure of the network, all processing cores are accessible, and thus the
system performance is maintained during the test. At the same time, EsyTest
provides a full test coverage for the NoC and a better hardware compatibility
comparing with the existing test strategies. Under the PARSEC benchmark and
different test frequencies, the execution time increases less than 5% at the cost of
9.9% more area and 4.6% more power in comparison with the execution where no
test procedure is applied.

IGTV27 TITLE: A Dual-Clock Multiple-Queue Shared Buffer

Abstract—Multiple parallel queues are versatile hardware data structures that are
extensively used in modern digital systems. To achieve maximum scalability, the
multiple queues are built on top of a dynamically-allocated shared buffer that
allocates the buffer space to the various active queues, based on a linked-list
organization. This work focuses on dynamically-allocated multiple-queue shared
buffers that allow their read and write ports to operate in different clock domains.
The proposed dual-clock shared buffer follows a tightly-coupled organization that
merges the tasks of signal synchronization across asynchronous clock domains
and queueing (buffering), in a common hardware module. When compared to
other state-of-the-art dual-clock multiple-queue designs, the new architecture is
demonstrated to yield a substantially lower-cost implementation. Specifically,
hardware area savings of up to 55 percent are achieved, while still supporting full-
throughput operation.
IGTV28 TITLE: Energy-Efficient VLSI Realization of Binary64 Division With
Redundant Number Systems

Abstract—VLSI realizations of digit-recurrence binary division usually use

redundant representation of partial remainders and quotient digits. The former
allows for fast carry-free computation of the next partial remainder, and the latter
leads to less number of the required divisor multiples. In studying the previous
relevant works, we have noted that the binary carrysave (CS) number system is
prevalent in the representation of partial remainders, and redundant high radix
representation of quotient digits is popular in order to reduce the cycle count. In
this paper, we explore a design space containing four division architectures. These
are based on binary CS or radix-16 signed digit (SD) representations of partial
remainders. On the other hand, they use full or partial precomputation of divisor
multiples. The latter uses smaller multiplexer at the cost two extra adders, where
one of the operands is constant within all cycles. The quotient digits are
represented by radix-16[−9, 9] SDs. Our synthesis-based evaluation of VLSI
realizations of the best previous relevant work and the four proposed designs show
reduced power and energy figures in the proposed designs at the cost of more
silicon area and delay measures. However, our energy-delay product is 26%–35%
less than that of the reference work.

IGTV29 TITLE: An Area- and Energy-Efficient FIFO Design Using Error-Reduced

Data Compression and Near-Threshold Operation for Image/Video
Applications

Many image/video processing algorithms require FIFO for filtering. The FIFO
size is proportional to the length of the filters and input data width, causing large
area and power consumption. We have proposed an energy- and area-efficient
FIFO design for image/video applications through FIFO with error-reduced data
compression (FERDC) and near-threshold operation. On architecture level,
FERDC technique is proposed to reduce the size and power consumption of the
FIFO by utilizing the spatial correlation between neighboring pixels and
performing error-reduced data compression together with quantization to
minimize the mean square error (MSE). On circuit level, near threshold operation
is adopted to achieve further power reduction while maintaining the required
performance. To demonstrate the proposed FIFO, it has been implemented using
a 0.18-μm CMOS process technology. The implementation covers different FIFO
length, including 128, 256, 512, and 1024. The experimental results show that the
proposed FIFO operating at 0.5 V and 28.57 MHz achieves up to 99%, 65%, and
34.91% reduction in dynamic power, leakage power, and area, respectively, with
a small MSE of 2.76, compared with the conventional FIFO design. The proposed
FIFO can be applied to a wide range of image/video signal processing applications
to achieve high area and energy efficiency.

IGTV30 TITLE: FPGA-based High-Throughput and Area-Efficient Architectures of

the Hummingbird Cryptography

In today‘s modern life, there is evermore care is needed to protect information. So

it is necessary to study the cryptographic algorithm. The various cryptographic
methods like AES, DES have been failed to meet the requirements of low level
devices especially in control system, this leads to the innovation of ultra
lightweight cryptography. Lightweight cryptography is the new area in the field
 of cryptography. These lightweight cryptographic algorithms try to reduce area
and power requirement, with less time for processing. Thus leads to low cost
implementation. Hummingbird cryptography is one of such method. Some time it
is treated as FSM because it is developed by using the feature of both ‗block and
stream cipher‘. Thus easy to understand and leads to better security for control
system application. Various lightweight cryptographic algorithms are discussed
briefly, these algorithm uses either block cipher or stream cipher but the
hummingbird is the special lightweight cryptography because it uses the features
of both block cipher and stream cipher. Thus it provides the better security to less
resourced devices in comparison with the other lightweight algorithms. The
hummingbird algorithm is already designed and developed on different platforms
like microcontroller, ASIC implementation etc, and it is discussed briefly. Three
different designs of hummingbird algorithms (TE, AR and proposed hybrid
design) are developed by modifying the block cipher used in the algorithm and
their performance is compared in terms of area occupation and throughput using
Xilinx ISE design tool with verilog language it has advantages than using C
language because the design is easily synthesized without the need of any external
compiler. If the code is written in C language, it requires conversion of code into
HDL before synthesis and then only it is translated into a hardware device, like
FPGA. Analysis of the simulation results obtained shows that TE design gives
high throughput, AR design gives less area requirement and hybrid design has less
area and more throughput than TE and AR designs respectively.

IGTV31 TITLE: MIHST: A Hardware Technique for Embedded Microprocessor

Functional On-Line Self-Test

Testing processor cores embedded in systems-on-chip (SoCs) is a major concern

for industry nowadays. In this paper, we describe a novel solution which merges
the SBST and BIST principles. The technique we propose forces the processor to
execute a compact SBST-like test sequence by using a hardware module called
MIcroprocessor Hardware Self-Test (MIHST) unit, which is intended to be
connected to the system bus like a normal memory core, requesting no
modification of the processor core internal structure. The benefit of using the
MIHST approach is manifold: while guaranteeing the same or higher defect
coverage of the traditional SBST approach, it reduces the time for test execution,
better preserves the processor core Intellectual Property (IP), does not require the
system memory to store the test program nor the test data, and can be easily
adopted for non-concurrent on-line testing, since it minimizes the required system
resources. The feasibility and effectiveness of the approach were evaluated on a
couple of pipelined processors.
IGTV32 TITLE: Remedying the Hummingbird Cryptographic Algorithm

In today‘s modern life, there is evermore care is needed to protect information. So

it is necessary to study the cryptographic algorithm. The various cryptographic
methods like AES, DES have been failed to meet the requirements of low level
devices especially in control system, this leads to the innovation of ultra
lightweight cryptography. Lightweight cryptography is the new area in the field
of cryptography. These lightweight cryptographic algorithms try to reduce area
and power requirement, with less time for processing. Thus leads to low cost
implementation. Hummingbird cryptography is one of such method. Some time it
is treated as FSM because it is developed by using the feature of both ‗block and
stream cipher‘. Thus easy to understand and leads to better security for control
system application. Various lightweight cryptographic algorithms are discussed
briefly, these algorithm uses either block cipher or stream cipher but the
hummingbird is the special lightweight cryptography because it uses the features
of both block cipher and stream cipher. Thus it provides the better security to less
resourced devices in comparison with the other lightweight algorithms. The
hummingbird algorithm is already designed and developed on different platforms
like microcontroller, ASIC implementation etc, and it is discussed briefly. Three
different designs of hummingbird algorithms (TE, AR and proposed hybrid
design) are developed by modifying the block cipher used in the algorithm and
their performance is compared in terms of area occupation and throughput using
Xilinx ISE design tool with verilog language it has advantages than using C
language because the design is easily synthesized without the need of any external
compiler. If the code is written in C language, it requires conversion of code into
HDL before synthesis and then only it is translated into a hardware device, like
FPGA. Analysis of the simulation results obtained shows that TE design gives
high throughput, AR design gives less area requirement and hybrid design has less
area and more throughput than TE and AR designs respectively.

IGTV33 TITLE: Argo: A Real-Time Network-on-Chip Architecture With an

Efficient GALS Implementation

In this paper, we present an area-efficient, globally asynchronous, locally

synchronous network-on-chip (NoC) architecture for a hard real-time
multiprocessor platform. The NoC implements message-passing communication
between processor cores. It uses statically scheduled time-division multiplexing
 (TDM) to control the communication over a structure of routers, links, and
network interfaces (NIs) to offer real-time guarantees. The area-efficient design is
a result of two contributions: 1) asynchronous routers combined with TDM
scheduling and 2) a novel NI microarchitecture. Together they result in a design
in which data are transferred in a pipelined fashion, from the local memory of the
sending core to the local memory of the receiving core, without any dynamic
arbitration, buffering, and clock synchronization. The routers use two-phase
bundled-data handshake latches based on the Mousetrap latch controller and are
extended with a clock gating mechanism to reduce the energy consumption. The
NIs integrate the direct memory access functionality and the TDM schedule, and
use dual-ported local memories to avoid buffering, flow-control, and
synchronization. To verify the design, we have implemented a 4 × 4 bitorus NoC
in 65-nm CMOS technology and we present results on area, speed, and energy
consumption for the router, NI, NoC, and postlayout.

IGTV34 TITLE: Low Power Multiplier Architectures Using Vedic Mathematics in

45nm Technology for High Speed Computing

Speed and the overall performance of any digital signal processor are largely
determined by the efficiency of the multiplier units present within. The use of
Vedic mathematics has resulted in significant improvement in the performance of
multiplier architectures used for high speed computing. This paper proposes 4-bit
and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low
power designs are realized in 45 nm CMOS Process technology using Cadence
EDA tool.

IGTV35 TITLE: Reliable Router Architecture with Elastic Buffer for NoC
Architecture

Router is the basic building block of the interconnection network. In this paper,
new router architecture with elastic buffer is proposed which is reliable and also
has less area and power consumption .The proposed router architecture is based
on new error detection mechanisms appropriate for dynamic NoC architectures. It
considers data packet error detection, correction and also routing errors. The
uniqueness of the reliable router architecture is to focus on finding error sources
accurately. This technique differentiates permanent and transient errors and also
protects diagonal availabilities. Input and output buffers in router architectures are
replaced by elastic buffers. Routers spend considerable area and power for router
buffer. In this paper the proposed router architecture replaces FIFO buffers with
the elastic buffers in order to reduce area, and power consumption and also to have
better performance.
IGTV36 TITLE: DESIGN AND ANALYSIS OF 10 PORT ROUTER FOR
NETWORK ON CHIP (NoC)

Network on chip is an emerging technology which provides data reliability and

high speed with less power consumption. With the technological advancements a
large number of devices can be integrated into a single chip. So the
communication between these devices becomes vital. The network on chip (NoC)
router is used for such communication. This paper focuses on the design analysis
of 10 port router. The delay (2.571ns) and power (80.98mW) is minimized by
using crossbar switch. The proposed architecture of 10 port router is simulated
and synthesized in Xilinx ISE 14.4 software.
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