CUTROW.

TCL:

Number of ports: 237

Number of nets: 1446

Number of cells: 822

Number of combinational cells: 810

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 607

Number of references: 50

Combinational area: 125558.573401

Buf/Inv area: 14283.401248

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135152.398052

Total cell area: 439700.525245

Total area: 574852.923297

LIBRARY.TCL:

Number of ports: 237

Number of nets: 1446

Number of cells: 822

Number of combinational cells: 810

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 607

Number of references: 50

Combinational area: 125558.573401

Buf/Inv area: 14283.401248

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135152.398052

Total cell area: 439700.525245

Total area: 574852.923297

PHYSICALCELL.TCL:

Number of ports: 237

Number of nets: 1446

Number of cells: 822

Number of combinational cells: 810

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 607

Number of references: 50

Combinational area: 125558.573401

Buf/Inv area: 14283.401248

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135152.398052

Total cell area: 439700.525245

Total area: 574852.923297

PG ROUTING.TCL

Number of ports: 237

Number of nets: 1446

Number of cells: 822

Number of combinational cells: 810

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 607

Number of references: 50

Combinational area: 125558.573401

Buf/Inv area: 14283.401248

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135152.398052

Total cell area: 439700.525245

Total area: 574852.923297

INSERTIOBUFFER.TCL

Number of ports: 237

Number of nets: 1683

Number of cells: 1059

Number of combinational cells: 1047

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 844

Number of references: 51

Combinational area: 126160.894684

Buf/Inv area: 14885.722531

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135210.381322

Total cell area: 440302.846527

Total area: 575513.227849

ENABLE OF ALL METAL LAYERS:

Number of ports: 237

Number of nets: 1683

Number of cells: 1059

Number of combinational cells: 1047

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 844

Number of references: 51

Combinational area: 126160.894684

Buf/Inv area: 14885.722531

Noncombinational area: 49257.682312

Macro/Black Box area: 264884.269531

Net Interconnect area: 135210.381322

Total cell area: 440302.846527

Total area: 575513.227849

PLACE.TCL:

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

PRECTS:

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

Number of ports: 237

Number of nets: 1677

Number of cells: 1045

Number of combinational cells: 1033

Number of sequential cells: 2

Number of macros/black boxes: 40

Number of buf/inv: 830

Number of references: 52

Combinational area: 124011.853157

Buf/Inv area: 13332.394425

Noncombinational area: 49216.511184

Macro/Black Box area: 264884.269531

Net Interconnect area: 137762.457473

Total cell area: 438112.633872

Total area: 575875.091344

CLOCK_OPT:

Point Incr Path

--------------------------------------------------------------------------

clock v_PCI_CLK (rise edge) 0.00 0.00

clock network delay (ideal) 0.50 0.50

input external delay 4.00 4.50 r

pidsel (in) 0.00 4.50 r

io_buff_195_0/Y (NBUFFX4_RVT) 0.07 * 4.58 r

I_PCI_TOP/pidsel (PCI_TOP) 0.00 4.58 r

I_PCI_TOP/U710/Y (NBUFFX4_HVT) 0.13 * 4.71 r

I_PCI_TOP/U893/Y (INVX1_HVT) 0.05 * 4.76 f

I_PCI_TOP/U452/Y (NAND2X0_HVT) 0.07 * 4.83 r

I_PCI_TOP/U1845/Y (OR2X1_HVT) 0.10 * 4.93 r

I_PCI_TOP/U443/Y (OR2X1_LVT) 0.06 * 4.98 r

I_PCI_TOP/U1851/Y (NAND3X0_HVT) 0.12 * 5.10 f

I_PCI_TOP/U884/Y (OAI21X2_HVT) 0.24 * 5.34 r

I_PCI_TOP/U835/Y (AO21X2_HVT) 0.20 * 5.54 r

I_PCI_TOP/U650/Y (NBUFFX2_HVT) 0.14 * 5.68 r

I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/D (SDFFARX1_LVT)

0.00 * 5.68 r

data arrival time 5.68

clock PCI_CLK (rise edge) 7.50 7.50

clock network delay (propagated) 0.81 8.31

clock uncertainty -0.30 8.01

I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/CLK (SDFFARX1_LVT)

0.00 8.01 r

library setup time -0.11 7.89

data required time 7.89

--------------------------------------------------------------------------

data required time 7.89

data arrival time -5.68

--------------------------------------------------------------------------

slack (MET) 2.21

Startpoint: I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]

(rising edge-triggered flip-flop clocked by SDRAM_CLK)

Endpoint: I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch
 (gating element for clock SDRAM_CLK)

Path Group: SDRAM_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SDRAM_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 0.90 0.90

I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/CLK (SDFFX2_HVT)

0.00 0.90 r

I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/Q (SDFFX2_HVT)

0.29 1.19 r

I_SDRAM_TOP/I_SDRAM_IF/U3968/Y (AND2X1_LVT) 0.04 * 1.23 r

I_SDRAM_TOP/I_SDRAM_IF/U87/Y (AND4X1_LVT) 0.05 * 1.29 r

I_SDRAM_TOP/I_SDRAM_IF/U86/Y (NAND4X0_LVT) 0.08 * 1.37 f

I_SDRAM_TOP/I_SDRAM_IF/U3714/Y (OR2X1_HVT) 0.15 * 1.52 f

I_SDRAM_TOP/I_SDRAM_IF/U20113/Y (AND3X1_LVT) 0.07 * 1.59 f

I_SDRAM_TOP/I_SDRAM_IF/U90/Y (OA21X1_HVT) 0.10 * 1.68 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/EN
(SNPS_CLOCK_GATE_LOW_SDRAM_IF)

0.00 1.68 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/U1/Y (NBUFFX8_HVT)

0.11 * 1.80 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/EN (CGLNPRX2_HVT)

0.02 * 1.82 f

data arrival time 1.82

clock SDRAM_CLK (fall edge) 2.05 2.05

clock network delay (propagated) 0.40 2.45

clock uncertainty -0.20 2.25

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/CLK (CGLNPRX2_HVT)

0.00 2.25 f

clock gating setup time -0.11 2.14

data required time 2.14

--------------------------------------------------------------------------

data required time 2.14

data arrival time -1.82

--------------------------------------------------------------------------

slack (MET) 0.32

Startpoint: I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]

(rising edge-triggered flip-flop clocked by SDRAM_CLK)

Endpoint: sd_DQ_out[17]

(output port clocked by SD_DDR_CLK)

Path Group: SD_DDR_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SDRAM_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 0.90 0.90

I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/CLK (SDFFARX1_HVT)

0.00 0.90 r

I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/Q (SDFFARX1_HVT)

0.28 1.18 r

I_SDRAM_TOP/I_SDRAM_IF/U29/Y (NBUFFX4_HVT) 0.10 * 1.28 r

I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_17/Y (MUX21X1_HVT)

0.15 * 1.43 r

I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[17] (SDRAM_IF) 0.00 1.43 r

I_SDRAM_TOP/sd_DQ_out[17] (SDRAM_TOP) 0.00 1.43 r

U92/Y (NBUFFX8_HVT) 0.11 * 1.54 r

io_buff_93_0/Y (NBUFFX4_RVT) 0.08 * 1.62 r

sd_DQ_out[17] (out) 0.00 * 1.62 r

data arrival time 1.62

clock SD_DDR_CLK (fall edge) 2.05 2.05

clock network delay (ideal) 0.79 2.84

clock uncertainty -0.10 2.74

output external delay -0.75 1.99

data required time 1.99

--------------------------------------------------------------------------

data required time 1.99

data arrival time -1.62

--------------------------------------------------------------------------

slack (MET) 0.37

Startpoint: I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]

(rising edge-triggered flip-flop clocked by SYS_2x_CLK)

Endpoint: I_RISC_CORE/R_31

(rising edge-triggered flip-flop clocked by SYS_2x_CLK)

Path Group: SYS_2x_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SYS_2x_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 1.13 1.13

I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/CLK (SDFFARX1_LVT)
 0.00 1.13 r

I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/Q (SDFFARX1_LVT)

0.18 1.31 r

I_RISC_CORE/U855/Y (NBUFFX16_LVT) 0.05 * 1.36 r

I_RISC_CORE/U781/Y (INVX2_HVT) 0.05 * 1.41 f

I_RISC_CORE/U109/Y (AND2X1_LVT) 0.06 * 1.47 f

I_RISC_CORE/U112/Y (AND4X1_LVT) 0.07 * 1.53 f

I_RISC_CORE/U130/Y (MUX21X2_LVT) 0.08 * 1.61 f

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_3_1/CO (FADDX1_LVT)

0.07 * 1.68 f

I_RISC_CORE/U111/Y (AND3X1_LVT) 0.06 * 1.74 f

I_RISC_CORE/U131/Y (MUX21X1_HVT) 0.15 * 1.89 f

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_2_2/CO (FADDX1_LVT)

0.08 * 1.97 f

I_RISC_CORE/U110/Y (AND2X2_LVT) 0.06 * 2.03 f

I_RISC_CORE/U137/Y (MUX21X1_HVT) 0.14 * 2.17 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_2/CO (FADDX2_LVT)

0.08 * 2.26 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_3/CO (FADDX1_LVT)

0.06 * 2.32 r

I_RISC_CORE/U948/Y (AND2X2_LVT) 0.06 * 2.38 r

I_RISC_CORE/U113/Y (MUX21X1_HVT) 0.14 * 2.52 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_1/CO (FADDX1_HVT)

0.17 * 2.69 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_2/CO (FADDX1_HVT)

0.15 * 2.83 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_3/CO (FADDX1_LVT)
 0.08 * 2.91 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_4/CO (FADDX1_LVT)

0.06 * 2.97 r

I_RISC_CORE/U653/Y (AO21X1_HVT) 0.11 * 3.09 r

I_RISC_CORE/U652/Y (NOR4X0_LVT) 0.08 * 3.17 f

I_RISC_CORE/R_31/D (SDFFARX1_LVT) 0.00 * 3.17 f

data arrival time 3.17

clock SYS_2x_CLK (rise edge) 2.40 2.40

clock network delay (propagated) 1.05 3.45

clock uncertainty -0.20 3.25

I_RISC_CORE/R_31/CLK (SDFFARX1_LVT) 0.00 3.25 r

library setup time -0.08 3.17

data required time 3.17

--------------------------------------------------------------------------

data required time 3.17

data arrival time -3.17

--------------------------------------------------------------------------

slack (MET) 0.00

Startpoint: I_BLENDER_0/s3_op2_reg[18]

(rising edge-triggered flip-flop clocked by SYS_CLK)

Endpoint: I_BLENDER_0/s4_op2_reg[28]

(rising edge-triggered flip-flop clocked by SYS_CLK)

Path Group: SYS_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SYS_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 1.14 1.14

I_BLENDER_0/s3_op2_reg[18]/CLK (SDFFARX2_HVT) 0.00 1.14 r

I_BLENDER_0/s3_op2_reg[18]/QN (SDFFARX2_HVT) 0.25 1.39 r

I_BLENDER_0/U447/Y (INVX2_HVT) 0.12 * 1.50 f

I_BLENDER_0/sub_x_26/U137/Y (NAND2X0_LVT) 0.10 * 1.60 r

I_BLENDER_0/sub_x_26/U127/Y (OAI21X1_HVT) 0.18 * 1.78 f

I_BLENDER_0/U6644/Y (AO21X1_HVT) 0.13 * 1.91 f

I_BLENDER_0/U6480/Y (NAND4X0_LVT) 0.07 * 1.98 r

I_BLENDER_0/U1505/Y (NAND3X0_HVT) 0.30 * 2.28 f

I_BLENDER_0/U6647/Y (AO21X1_LVT) 0.13 * 2.41 f

I_BLENDER_0/U948/Y (XNOR2X1_HVT) 0.19 * 2.60 r

I_BLENDER_0/U1834/Y (INVX4_HVT) 0.08 * 2.68 f

I_BLENDER_0/U1159/Y (OR2X1_LVT) 0.05 * 2.73 f

I_BLENDER_0/U1158/Y (INVX1_LVT) 0.03 * 2.76 r

I_BLENDER_0/U1402/Y (XOR3X1_HVT) 0.31 * 3.07 f

I_BLENDER_0/U734/Y (XOR3X1_HVT) 0.31 * 3.38 f

I_BLENDER_0/U723/Y (XOR3X1_HVT) 0.29 * 3.67 f

I_BLENDER_0/U582/Y (XOR3X1_HVT) 0.31 * 3.98 f

I_BLENDER_0/U1390/Y (OR2X1_HVT) 0.12 * 4.10 f

I_BLENDER_0/U1213/Y (NAND3X0_LVT) 0.05 * 4.15 r

I_BLENDER_0/U1212/Y (NAND2X0_LVT) 0.03 * 4.18 f

I_BLENDER_0/U4989/Y (AND3X1_HVT) 0.14 * 4.32 f

I_BLENDER_0/U575/Y (OR2X1_HVT) 0.17 * 4.49 f

I_BLENDER_0/U4792/Y (INVX1_HVT) 0.06 * 4.54 r

I_BLENDER_0/U2263/Y (OR2X1_LVT) 0.04 * 4.59 r

I_BLENDER_0/U2257/Y (NAND3X0_LVT) 0.03 * 4.62 f

I_BLENDER_0/U2654/Y (NAND4X0_LVT) 0.06 * 4.68 r

I_BLENDER_0/U1727/Y (NAND3X0_HVT) 0.28 * 4.96 f

I_BLENDER_0/s4_op2_reg[28]/D (SDFFX1_LVT) 0.00 * 4.96 f

data arrival time 4.96

clock SYS_CLK (rise edge) 4.80 4.80

clock network delay (propagated) 1.14 5.94

clock uncertainty -0.20 5.74

I_BLENDER_0/s4_op2_reg[28]/CLK (SDFFX1_LVT) 0.00 5.74 r

library setup time -0.19 5.55

data required time 5.55

--------------------------------------------------------------------------

data required time 5.55

data arrival time -4.96

--------------------------------------------------------------------------

slack (MET) 0.59

Startpoint: I_PCI_TOP/R_687

(rising edge-triggered flip-flop clocked by PCI_CLK)

Endpoint: pserr_n_out

(output port clocked by v_PCI_CLK)

Path Group: v_PCI_CLK

Path Type: max

Point Incr Path

-----------------------------------------------------------

clock PCI_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 0.79 0.79

I_PCI_TOP/R_687/CLK (SDFFASX1_LVT) 0.00 0.79 r

I_PCI_TOP/R_687/Q (SDFFASX1_LVT) 0.15 0.94 r

I_PCI_TOP/U614/Y (NAND3X0_HVT) 0.31 * 1.25 f

I_PCI_TOP/pserr_n_out (PCI_TOP) 0.00 1.25 f

U744/Y (INVX4_HVT) 0.17 * 1.42 r

U743/Y (INVX8_HVT) 0.15 * 1.57 f

io_buff_158_0/Y (NBUFFX4_RVT) 0.11 * 1.69 f

U32/Y (NBUFFX32_HVT) 0.10 * 1.78 f

pserr_n_out (out) 0.00 * 1.78 f

data arrival time 1.78

clock v_PCI_CLK (rise edge) 7.50 7.50

clock network delay (ideal) 0.50 8.00

output external delay -3.00 5.00

data required time 5.00

-----------------------------------------------------------

data required time 5.00

data arrival time -1.78

-----------------------------------------------------------

slack (MET) 3.22