Application Note 1020

Green Mode PWM Controller AP3101

-- Function Description and Design Consideration

Prepared by Wu Quanqing
System Engineering Dept.

Introduction
With the development of power technology, the
demand for low standby power in power systems has
increased. The AP3101 is a green current mode PWM
controller. Its input power can be less than 0. 3W in
265V AC input at no load condition. The target
AP3101 application fields consists of LCD Monitor/
TV and other off-line AC-to-DC adapters.
This application note includes a general description,
detailed description of major functions, and provides
notes for typical applications in SMPS.
1. General Description
The AP3101 acts as a programmable fixed frequency
PWM control during normal operation, and an external
resistor is used to set the osillating frequency. When
output power of a SMPS falls below the given level,
the IC automatically enters the skip cycle mode to
reduce power consumption.
Owing to low start-up current of 30µA and low oper-
ating current of 3mA, the AP3101 can reduce standby
power dissipation of the startup resistor, and improve
operating efficiency. In addition, totem driver output
stage with 0. 6A current capacity is helpful for driving
MOSFET directly.
With the built-in limited power control, the AP3101
can turn off the PWM output after 23 ms in overload or
short circuit conditions, and the input power of a
SMPS can drop close to zero. Also, the perfect protec-
tion against over-temperature is automatically per-
formed. Furthermore, leading edge blanking (LEB)
technology is included in the AP3101 for noise immu-
nity; built-in slope compensation ensures the stability
of peak current mode control.
Figure 1 is the functional block diagram of AP3101.
Figure 2 is AP3101's Pin Configuration.

VCC
1
GND
ON/OFF
Driver 8
Q D GATE

CLK OSC
RB Short circuit
Protection
4 6V
RI
OTP Skip Cycle 4R
5 ADJ
R
6V
PWM
3 Internal Bias 2
VIN FB
2R
7 R
VCC Slope
UVLO Current Limit
Compensation

16V/10V 6
LEB SENSE
0.85V

Figure 1. Functional Block Diagram of AP3101

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 Application Note 1020
rent. When load power drops to a lower level, the VFB
decreases as well as the peak switch current. If peak
current drops to a given set point where the non-invert-
GND 1 8 GATE
ing voltage of the skip cycle comparator (VFB-0. 9V) is
FB 2 7 VCC lower than its inverting input (VADJ), the AP3101 will
VIN 3 6 SENSE enter skip cycle mode and start to blank its output
pulse.
RI 4 5 ADJ
144 RADJ 24 RADJ
VADJ = ( 96 + （V
) ）
24 + RADJ 24 + RADJ
Figure 2. Pin Configuration of AP3101

ADJ
2. Pin Descriptions
GND (pin 1) The combined control circuitry and
power ground. AP3101 RADJ

FB (pin 2) The feedback voltage pin is connected to

GND
the external opto-coupler, and its typical source current
is 1. 3mA. This FB pin together with the current sense
pin will determine the PWM duty cycle.
Figure 3. RADJ(KΩ) Sets The Skip Cycle Point
VIN (pin 3) The pin is shorted to the VCC internally. It
can be pulled high to the rectified line input through a
resistor for startup.

RI (pin 4) Frequency set pin. A resistor between the RI

and GND will generate a constant current source, and
the current source will determine the oscillating fre-
quency by charging an internal capacitor.

ADJ (pin 5) An external resistor from this pin to

ground can adjust the voltage level when the system
enters the skip cycle mode.

Sense (pin 6) It is used for current mode control and

pulse-pulse current limit. A voltage proportional to the
inductor current is connected to this pin. Figure 4. The Skip Cycle Waveform

VCC (pin 7) The power supply for the device.
GATE (pin 8) The PWM output directly drives the
gate of MOSFET.
3. Function Descriptions
3. 1 Green Mode
In normal operation with heavy load, the AP3101
works at a fixed switching frequency, and the voltage
on the FB pin (VFB) corresponds to a larger peak cur-
Figure 4 illustrates the actual skip cycle waveform at
the gate pin. The power transfer now depends upon the
length of the pulse bunches. Suppose we have the fol-
lowing component values:
LP, primary inductance: 1mH;
fS, oscillating frequency: 65kHz;
IP: 200 mA.
At light load, the converter will enter the DCM
mode. And the theoretical power transfer is therefore:
0. 5*LP*IP2*fS=1. 3W.

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 Application Note 1020
If the device enters the skip cycle mode with a bunch
length of 15 ms over a recurrent period of 100 ms,
then the total power transfer is: 1. 3*15/100= 195 mW. 120

Oscillator Frequency (kHz)

3. 2 Start-up 100
For low standby power, the high resistance value of
the startup resistor is selected. However, it will cause
80
longer startup time. To reduce the startup time, we can
use a speedup startup circuit. The value of capacitor
C1 should be less than capacitor C2. (see Figure 5) 60

Moreover, the value of C1 and C2 should be selected 40

carefully in the actual design. Once the AP3101 starts 15 18 21 24 27 30 33 36 39 42

to work, the C2 will be charged by the transformer but Timing Resistor (kΩ)

the voltage for C1 will reduce rapidly because startup

current can't maintain the IC operation current. So, the
C2 should also be charged as quickly as possible. Thus
the power of C2 through a transformer can take over
the C1 smoothly and the output voltage will not drop
or repeat many times during the startup process.
At last, the design of RSTART should meet the limi-
tation of IC startup condition and maximum voltage
operation condition with its maximum load, which
always indicates the maximum and minimum equiva-
lent resistor of IC (V/I).
Line VDC
RSTART
VCC
D1 D2 R1
Figure 6. Frequency vs. Timing Resistor
The recommended oscillation range frequency is 50
kHz to 100 kHz. (see Figure 6)
A small capacitor (not over 50pF) connected in par-
allel with resistor RI can be utilized to avoid noise.
4. 4 Output Driver
Totem-pole output stage can directly drive MOS-
FET, and its maximal output voltage is clamped at
22V. In addition, typical rise and fall time of output
pulse is 250ns and 50ns respectively.
4. 5 The Compensation.
The normal compensation mode is illustrated as
Figure 7. Its feedback compensation network transfer
function can be deduced as :

AP3101 C1 C2 VF B(s) RB 1 1 + s(R1 + RC )C1

GFB(s) = = ⋅ ⋅
VO(s) C1 R1 RD s 1 + sRB C B
GND

1
fP =
2πRB C B
Figure 5. Speedup Start-up Circuits
1
fZ =
4. 3 Oscillator 2π ( R1 + RC )C1
A resistor RI between RI and GND will generate a
constant current source, and the current source will In general design, the crossover frequency fC of the
determine the oscillating frequency by charging an power system can be determined with the main power
internal capacitor. parameter design. Then, we can place a compensator
zero (fZ) around fC/3 and place a compensator pole
The oscillating frequency can be expressed as: (fP) above 3fC. Thus, we can obtain a good response
feature and stability margin. In addition, the output LC
1690
f ≈ （kHz )
RI [kΩ]

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filter should enable to bring some amount of phase
shift and should be considered for real application.
VO
Vref
RD
RB
VFB
AP3101 R1
FB
Rbias
CB
GND RC
C1
R2
Figure 7. AP3101 Normal Compensator with AZ431
4. 6 Over Temperature Protection
The AP3101 will automatically turn off the PWM
output when junction temperature rises up to a given
value; the typical value is 150oC, with hysteresis of
25oC.
5. Adapter Application
5. 1 How to Reduce Standby Power
First, a high value for the startup resistor is selected
to lower loss. In Figure 8, a start-up resistor R1 of
1.5MΩ is selected to ensure that VCC hold up capaci-
tor C3 is charged up to 16V even under low line volt-
age of 85VAC, and the maximum power loss on R1 is
90mW. Once the AP3101 begins to work, an auxiliary
winding of the transformer T1 will provide operating
current for the IC.
Second, adjusting the skip cycle level can reduce
switching loss on MOSFET. The resistor RADJ on pin
ADJ is used to adjust the skip cycle frequency; a
larger resistor corresponds to a lower skip cycle fre-
quency, so lower input power can be obtained. How-
ever, with the larger resistor it also needs a larger VCC
hold-up capacitor and the peak switching current will
also become larger correspondingly. Also, a low-value
capacitor can't provide enough energy to the AP3101
at light load condition or less.
5. 2 How to Avoid Audio Noise
The transformer T1 is the main noise source. Under
light or no load, the AP3101 will operate in skip cycle
mode with lower switching frequency, and audio noise
from the transformer T1 will probably be heard.
Jan. 2008 Rev. 1. 3
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Application Note 1020
Therefore, 0. 5 to 1kHz of skip cycle frequency is pre-
ferred to compromise between standby power and
audio noise. In addition, the adhesives in the trans-
former construction are required.
The snub capacitor C2 is another noise source.
Polypropylene capacitor can greatly reduce this noise.
(see Figure 8)
5. 3 PCB Layout
PCB layout is a critical portion of switching power
supply. Improper layout will adversely affect RFI radi-
ation, component reliability, efficiency and stability.
Within an adapter, there are four major current
loops. Two of the loops conduct the high-level AC
currents needed by the supply. They are the power
switch AC current loop and the output rectifier AC
current loop. The currents are the typical trapezoidal
current pulses with very high peak current and very
rapid di/dt. The other two current loops are the input
source and the output load current loops, which carry
low frequency current being supplied from the voltage
source to and from the load respectively.
For the power switch AC current loop, current flows
from the input filter capacitor through the transformer
winding and the power switch then back to the nega-
tive terminal of the input capacitor. Similarly, the out-
put rectifier current loop's current flows from the
secondary transformer winding, through the rectifier
to the output filter capacitor and back to the winding.
The filter capacitors are the only components that can
source and sink the large levels of AC current in the
time needed by the switching power supply. The PCB
traces should be made as wide and as short as possible,
which can minimize parasite resistive and inductive
effects. These traces should be laid out fistly. As for
the input source and output load current loops, both of
these loops must be connected directly to their respec-
tive filter capacitor's terminals. All the current path
loops, particularly with high frequency switching,
should be as short as possible. Thus it will reduce the
so-called conduction or radiation interference.
The grounds are extremely important to the proper
operation of the switching power supply. The analog
control ground should be connected first and then
connected to other circuitry. "One point grounding"
must be used. Single-point grounding keeps the noise
sources separated from the sensitive control circuits.
BCD Semiconductor Manufacturing Limited
 Application Note 1020
Care must be taken that pin ADJ and pin RI are placed
away from noise sources which are sensitive or may
disturb the signal.

NTC R9
BD1

C5
R1 C1 R2 C2 J2
J1 T D3 L2

D1 C7
C6
C3 12V/3A

R3 D2

R4
Q1
7N60

R10
C8

R6
R7 0.5 R11

8 7 6 5
GATE VCC SENSE ADJ R12 Q2
AZ431
U1
AP3101
R13
620
GND FB VIN RI
1 2 3 4
R8 U2 p521
4 1
3 2
Cb

Figure 8. Typical Application of AP3101

Jan. 2008 Rev. 1. 3 BCD Semiconductor Manufacturing Limited