952
4, APRIL 2003
Extension and Source/Drain Design for
High-Performance FinFET Devices
Jakub Kedzierski, Member, IEEE, Meikei Ieong, Senior Member, IEEE, Edward Nowak, Thomas S. Kanarsky,
Ying Zhang, Ronnen Roy, Diane Boyd, David Fried, and H.-S. Philip Wong, Fellow, IEEE
Abstract—Double gate devices based upon the FinFET archi-
tecture are fabricated, with gate lengths as small as 30 nm. Partic-
ular attention is given to minimizing the parasitic series resistance.
Angled extension implants and selective silicon epitaxy are investi-
gated as methods for minimizing parasitic resistance in FinFETs.
Using these two techniques high performance devices are fabri-
cated with on-currents comparable to fully optimized bulk silicon
technologies. The influence of fin thickness on device resistance and
short channel effects is discussed in detail. Devices are fabricated
with fins oriented in the 100 and 100 directions showing dif-
ferent transport properties.
Index Terms—(110) transport, double gate, extension doping
gradient, extension resistance, external resistance, FinFET, orien-
tation dependent transport, raised source drain, silicon epitaxy,
thin body, transistor scaling, ultra-thin body, undoped body.
I. INTRODUCTION
T HE difficulties in shrinking the size of the traditional bulk
transistor have prompted the development of a new de-
vice architecture in which two gates, one on each side of the
body, are used per device. Such double-gate transistors have
higher scalability than their single gate counterparts since both
gates help to control the potential in the body [1]. From sev-
eral double-gate device architectures the FinFET [2]–[5] has
emerged as a promising device structure. It combines the critical
elements of superior scalability found in all double-gate devices
with the manufacturability of conventional transistors. The body
of a FinFET device, shown in Fig. 1, consists of a vertical crystal
silicon wall, called a fin. The gate wraps around both sides of the
fin, creating a channel on each side. The main advantage of the
FinFET structure over other double-gate device designs is that
the self-aligned gates can be fabricated using a single lithog-
raphy and etch step.
One of the central challenges in making FinFETs competitive
with conventional transistors is enabling high current drive
by reducing parasitic series resistance. The device regions
that contribute to series resistance: the extension region, the
source/drain region, and the silicide are geometrically dif-
Manuscript received July 17, 2002; revised December 12, 2002. The review
of this paper was arranged by Editor R. Shrivastava.
J. Kedzierski, Y. Zhang, R. Roy, and H.-S. P. Wong are with the IBM
T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail:
jakub@us.ibm.com).
M. Ieong, T. S. Kanarsky, and D. Boyd are with the IBM Microelectronics
Semiconductor Research and Development Center (SRDC), Hopewell Junction,
NY 12533 USA.
E. Nowak and D. Fried are with the IBM Microelectronics Division, Essex
Junction, VT 05452 USA.
Digital Object Identifier 10.1109/TED.2003.811412
0018-9383/03$17.00 © 2003 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO.
ferent in a FinFET and therefore require modified integration
schemes. For example, the extension region in a FinFET has
a normal that lies in the wafer plane, orthogonal to the wafer
normal, and the conventional extension implant vector. This
geometric difference suggests that highly angled implants
would be effective in forming uniform extension regions.
The source/drain region also requires re-engineering. In the
simplest form, as shown in Fig. 1, the FinFET lacks the equiv-
alent of a deep source/drain region that makes the formation of
low resistance silicide contacts possible. Low resistance con-
tacts are still possible by using low barrier silicides [6], or by
thickening the fin outside of the gate region with a selective de-
position, such as silicon epitaxy. However, both silicon epitaxial
regrowth of the source/drain regions and low barrier silicides
ideally require well-formed spacers, which separate the fin from
the gate but leave the side of the fin accessible.
In this paper, highly angled extension implants together
with epitaxial raised source/drain (RSD) are shown to yield
high performance FinFET devices. Issues relevant to high
performance FinFET design including: extension resistance,
fin epitaxy, spacer formation, silicide, fin orientation, and
short-channel effects are discussed.
II. PROCESS CONSIDERATIONS
The critical steps in the FinFET fabrication process included
sequentially: fin formation, gate stack formation, extension
implant, spacer formation, epitaxial raised source/drain, deep
source/drain implantation, and silicide. The fin can be formed
using spacer image transfer (SIT) [7], [8], or by using trimming
techniques such as resist ashing to define fins using optical
lithography. In this work the latter approach was used due
to its simplicity and the ability to yield a wide range of fin
thickness on a wafer. However it is likely that in order to
achieve the fin thickness tolerances and pitch values required
for manufacturing a SIT process would be required. It is
possible to form FinFETs with the (100) oxide orientation on
a (100) wafer with the notch in the direction, but such
a process requires the fin be rotated by 45 from the standard
lithographic orientation. If no such rotation is performed the
gate oxide forms on the (110) plane. In both orientations the
current carrying direction is a normal to a plane in the same
family as the gate oxide surface. Both and directed
FinFETs were fabricated in this study. Fins were formed by
reactive ion etch (RIE) using a silicon dioxide hard-mask, from
a 65 nm thick silicon on insulator (SOI) layer.
Gate oxide growth was preceded by a sacrificial oxidation
to repair the RIE damage to the fin [3]. In this study the gate
KEDZIERSKI et al.: EXTENSION AND SOURCE/DRAIN DESIGN FOR HIGH-PERFORMANCE FINFET DEVICES 953

Fig. 1. On right, the diagram of the skeleton FinFET structure with gate, source, and drain pads. On left, the 3-D view of one quarter of the FinFET structure
after spacer etch but before raised source/drain.

h i
Fig. 2. Electron micrographs of a 110 FinFET perpendicular to current flow. The most zoomed out image is a SEM micrograph, it is followed by two TEM
micrographs showing the Fin cross section and gate oxide thickness, respectively. Measurements: T = 20 nm, T = 1:6 nm, T = 150 nm, and W =
2
130 nm (2 Fin Height).

oxynitride was thermally grown to a thickness of 1.6 nm, and a
polysilicon gate was deposited to a thickness of 150 nm. Fig. 2
is a cross section taken through the fin perpendicular to the cur-
rent flow that shows the gate stack dimensions on a 20 nm thick
fin. In this experiment the gate was doped with ion implanta-
tion prior gate lithography. Gate predoping allows lower thermal
budgets to be used for extension and source/drain activation.
Following the lithography and gate etch the extension regions
were implanted. High tilt angle, low energy implants were used
to uniformly dope the extension regions. The extension resis-
tance in a FinFET is not only a function of implant energy, dose,
and angle but also of the fin thickness . In order to deter-
mine the dependence of the extension sheet resistance on ,
two sets of FinFET devices were fabricated with a wide range
954
Fig. 3. A graphical demonstration of the R extraction method. Two devices
with different extension lengths, L , but the same T are measured. The total
series resistance, R , is obtained for each device as the resistance limit with
V !1 . The extension resistance per square is given by the formula, with the
R test structures having L of 2 m, and R pad structures having L of
200 nm. H is the fin height.
Fig. 4. Extension resistance, R in Ohms/Square of extension, as a function
of dopant type and Fin thickness. Extension resistance is calculated as twice the
fin resistance in Ohms/Square. The factor of 2 is used to account for the fact that
each fin has to carry twice the current of an extension in a bulk device; therefore
in effect there are two extensions per fin, one for each channel. The previous
figure shows the exact method used for R extraction.
of values. One set had 2 m long extension regions on ei-
ther side of the gate (Test Set), while the other had only 200 nm
long extensions (Pad Set). Both sets were gated identically, with
gates less than 150 nm in length, and shared identical contacts.
Extension resistance was extracted as difference in the limits of
the total device resistance as , between a device in the
test set and the pad set with a matched , normalized by the
difference in their extension lengths. The resistance extraction
process is shown in Fig. 3, on a sample test structure. Fig. 4
shows the extension resistances for both NMOS and PMOS de-
vices as a function of , the fin thickness. The measured ex-
tension resistance was found to increase sharply for smaller
especially in the nFET. This increase is likely due to the combi-
nation of dopant loss and increased amorphization extent.
Following extension formation, spacers were formed using 70
nm of deposited nitride. To increase the effectiveness of raised
source/drain the spacers were etched completely away from the
sides of the fin. Such a spacer process sets a limit on fin height.
In order to remove the spacer from the fin and still leave an
effective spacer between the fin and the gate the fin height must
be significantly smaller than the gate height. In this experiment,
the polysilicon gate height was roughly twice the fin height.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003
h i
Fig. 5. SEM cross section profile of the RSD region of a 110 FinFET.
Regions are delineated with lines due to poor contrast. The unusual faceting is
likely due to the slow growth rate of the (113) planes. Chrome is deposited on
RSD to provide SEM contrast.
Fig. 6. Selective silicon epitaxy growth rates as a function of fin doping
and orientation. Growth rates were measured on fins approximately 25 nm in
thickness.
Fig. 1 shows a 3-D process simulation of the completed spacer
after the etch.
Selective epitaxy was used to increase the fin thickness in
the regions outside of the spacer. These thickened source/drain
regions, often called raised source/drain (RSD) [9], [10], help
to decrease overall parasitic resistance by providing more sil-
icon for the source/drain silicide formation. In our experiment,
the silicon deposition rate during selective epitaxy was a func-
tion of the crystal orientation of fin as well as the fin doping.
Some of the complexities in the epitaxy process can be seen
from the cross section of the source/drain areas after RSD of a
directed Fin, shown in Fig. 5. Due to the crystallographic
deposition rate dependencies the RSD region is not square but
trapezoidal. Fig. 6 shows the dependencies of the lateral silicon
growth rate on doping for both and directed fins.
Growth rates are always higher on surfaces, and are typ-
ically slower on As doped fins. Fig. 7 shows a FinFET
before and after selective epitaxy, the before inset also shows
the top down view of the spacer.
Deep source/drain implants were performed at 0 tilt, doping
the RSD regions. After source/drain activation, CoSi was
formed on the gate, and the source/drain areas. Co thickness was
KEDZIERSKI et al.: EXTENSION AND SOURCE/DRAIN DESIGN FOR HIGH-PERFORMANCE FINFET DEVICES 955

Fig. 9. V of FinFET NMOS devices in terms of L =T ratio. T varies

from 20 nm to 90 nm; L varies from 30 nm to 120 nm. Long channel V is
shown on the right.

Fig. 7. Top down SEM micrograph, of h100i FinFET before and after selective
Si epitaxy. Device measurements: T = 20 nm, L = 30 nm, 55 nm of
silicon was grown selectively on each side of the fin.

Fig. 10. Swing of FinFET NMOS devices in terms of L =T ratio. T

varies from 20 nm to 90 nm; L varies from 30 nm to 120 nm. Minimum
swing for V = 0:1 V and 1.5 V is shown.

and a certain . This can be used to define the ,

Fig. 8. Swing contours for FinFET NMOS devices, V = 0:1 V. Fin thickness the extension region overlap with the gates. A natural coordinate
T varies from 20 nm to 82.5 nm in steps of 12.5 nm, physical gate length, L
varies from 70 nm to 157.5 nm in steps of 12.5 nm. Contours are extrapolated system for short channel effects (SCE) of double gate devices
with dotted lines to a common origin, at (L ; T ) = (0; 0). can be constructed by defining

adjusted so that the final CoSi thickness was approximately

half the RSD region. In order to investigate the performance
Devices with a similar will have similar SCE pro-
impact of the extension resistance, RSD, and silicide devices
vided that , and the junctions are abrupt.
were probed at each of these steps.
The relation can be obtained rigorously by expanding the
modified scale length [11]
III. ELECTRICAL RESULTS AND DISCUSSION to the second order; the higher order corrections were small
To facilitate a fair comparison with single-gate MOSFETs, for devices presented in this study. Figs. 9 and 10 show
FinFET currents were normalized by the effective device width roll off and swing characteristics of devices with different
using fin height . The normalization by and in terms of their ratio. In order to maintain
2 accounts for the fact that a FinFET, being a double-gate must be larger than 1.3.
device, has two channels per fin, each contributing to the device and curves of devices with
capacitance. Due to the use of an undoped body and polysilicon nm, nm are shown in Figs. 11–13.
gates the of the FinFET devices fabricated in this experiment Fig. 11 shows characteristics of NMOS and PMOS
was approximately 0.5 V lower than desirable for CMOS appli- devices without RSD. Devices with of 10 nm and 20 nm
cations. To compensate for the low the gate voltage range is show linear swings of 75 mV/dec and 90 mV/dec respectively.
shifted by 0.5 V in the plots and when reporting and Thinner fins show lower due to higher external resistance.
, but is kept at 1.5 V. Fig. 12 shows the characteristics of devices with
Fig. 8 shows the subthreshold swing contours of 48 NMOS and without RSD. Reducing the devices external resistance
devices with six different fin thickness and eight different with RSD increases without increasing . In this ex-
physical gate lengths . Due to the boundary conditions at periment the RSD devices had a slightly modified activation
the gates and the extensions, the extrapolated contours merge at anneal to help reduce boron diffusion and produce symmetric
a point. As expected that point occurs at , PFET/NFET . Fig. 13 shows the characteristics of
956 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003

Fig. 11. I 0 V plot for L = 30 nm T = 20 nm, and 10 nm, FiIIFET h i h i

Fig. 14. Transconductance (G ) of 100 and 110 directed fins. Long
devices. N-poly gate was used for NMOS, P-poly for PMOS. Devices shown in h i h i
channel NMOS 100 FinFETs have higher G than 110 FinFETs. Long
this figure have no RSD. h i h i
channel PMOS 100 FinFETs have lower G than 110 FinFETs. Similar
trends persist for short channel devices.

Fig. 12. I 0 V plot for L = 30 nm T = 20 nm, FinFET devices with

and without RSD. The source/drain formation process was modified for devices
with RSJ) to reduce boron diffusion from the source/drain areas into the body.
Fig. 15. Contour plot of I at V = 1:5 V for PMOS FinFETs as a function
of fin thickness (T ) and gate length (L ). Gate voltage range was shifted
for each device so that I is fixed at 200 nA=m.

Fig. 14 shows the extrinsic transconductance of

and devices. In general, the performance of de-
vices is lower for the NFET and higher for the PFET, and the
performance difference in long channel devices is larger than
the difference in short channel ones. Due to the presence of sili-
cide in these devices the values of reported here are more
reflective of inherent differences between the two orientations
than values published without silicide [4].
Both and increase as increases, increases be-
Fig. 13. I 0 V plot for short channel, L = 30 nm, T = 20 nm, 100 h i cause extension resistance and the threshold voltage decrease,
directed FiIIFET devices without RSD, with RSD, and with RSD and suicide. increases because of the increased short channel effects.
0
NFET V varies from 0.5 V to 1.0 V in steps of 0.25 V. One way of comparing different devices is to compare the
for the same . For FinFETs with different and the
devices with and without RSD, and with and without silicide. can be selected so that it gives a constant , for ex-
At V ( for PMOS,—for NMOS) and ample, 200 nA m at , then can be extracted with
V, m, for both the NFET and V and V. A contour plot can be con-
PFET. At V and V, is 1460 structed comparing extracted in such a way for devices with
A m for NFET and 850 A m for PFET, in devices different and . Fig. 15 shows such a plot for directed
with RSD and silicide. This to our knowledge is the highest PMOS devices. The maximum for nA m oc-
current reported for NMOS and PMOS double-gate devices, curs at nm and nm, and is equal to 930
and is competitive with state-of-the-art bulk silicon and SOI A m. falls when is too large due to short channel ef-
technology [12], [13]. Without RSD current levels are lower, fects, and when is too small due to parasitic resistance, for
with of 675 A m for NFET and 370 A m for PFET. long channel devices falls off due to increased channel resis-
Silicide makes a much larger difference in NFETs performance tance. The maximum occurs when channel resistance, parasitic
probably because the RSD thickness on N-doped fins is resistance, and short channel effects are balanced to give the
significantly thinner. highest performance. Decreasing parasitic resistance, in partic-
KEDZIERSKI et al.: EXTENSION AND SOURCE/DRAIN DESIGN FOR HIGH-PERFORMANCE FINFET DEVICES 957

with fins in the direction have higher NMOS transcon-

ductance than FinFETs with directed fins, and tend to
have higher selective silicon epitaxy growth rates. FinFETs with
fins in the direction, have higher PMOS transconduc-
tance. Short channel effects of undoped body FinFET devices
can be easily expressed in terms of an electrical channel length
and electrical fin thickness , devices with a similar
ratio were found to have similar short channel effects.

ACKNOWLEDGMENT
The authors would like to acknowledge the fabrication
Fig. 16. I 0 I plot for L = 30 nm PMOS FinFETs, without extension
support received from the facilities of the Semiconductor Re-
implants. T is varied. Source/drain junctions were annealed repeatedly to until
a maximum I for a fixed I was reached. search and Development Center (SRDC), as well as the support
received from the Advanced Semiconductor Technology Lab
ular the extension resistance, would increase the maximum (ASTL) for critical steps, in particular ion implantation support
and lower the and at which it occurs. from P. Saunders, and epitaxy support from J. Newbury. The
When a similar contour plot is constructed for the authors would also like to thank W. Haensch and J. Warlaumont
NMOS devices the maximum for nA m for their management support, and R. Young for his process
occurs at nm and nm, and is equal to 1200 simulation support.
A m. This maximum is further from the design point of
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Jakub Kedzierski (M’02) received the M.S. and
Ph.D. degrees in electrical engineering from the
University of California at Berkeley in 1999 and
2001, respectively. His Ph.D. research focused on
implementation of low barrier metal contacts on
highly scaled FDSOI devices, using complementary
silicides PtSi and Er Si .
He is currently a Research Staff Member at
the IBM T. J. Watson Research Center, Yorktown
Heights, NY. His research interests include the
investigation of new thin-body device structures
such as the double-gate FinFET and the fully depleted SOI device. Recently
his efforts have been focused on the use of metal-gates through total gate
silicidation, silicide workfunction engineering, and source/drain resistance
control methods utilizing selective silicon epitaxy, in thin-body structures.
While at the University of California at Berkeley, he worked within the
group that implemented the FinFET double-gate structure. He also worked on
solid-state epitaxy and its application to transistor integration, high-resolution
electron beam lithography, and wrap-around-gate devices. He has over 20
published papers.
Meikei Ieong (SM’01) received the B.S. degree in
electrical engineering from the National Taiwan Uni-
versity, Taiwan, R.O.C., and the M.S. and Ph.D. de-
grees in electrical and computer engineering from the
University of Massachusetts, Amherst, in 1993 and
1996, respectively.
He started his career with IBM in 1995, where
he developed the mixed-mode capability in IBM’s
device simulator, Fielday. He was the Architect of
IBM’s third generation device simulator, Fielday3.
He is currently Manager of the Exploratory Device
and Integration Department in the Semiconductor Research and Development
Center (SRDC) and T. J. Watson Research Center, Yorktown Heights, NY. His
team has made several important contributions in advanced CMOS devices,
including strained-silicon, ultra-thin channel single- and double-gate devices,
3-D integrated circuits, and silicon-based optical detectors. In 2001, he held
an Adjunct Associate Professor position in the Department of Electrical
Engineering of Columbia University, New York.
Dr. Ieong received an IBM Outstanding Technical Achievement award and
an IBM Corporate award.
Edward Nowak received the S.B. degree in physics
from the Massachusetts Institute of Technology,
Cambridge, and the M.S and Ph.D. degrees in
theoretical physics from the University of Maryland,
College Park.
He joined IBM in 1981 to work on DRAM devel-
opment. In 1985, he joined the CMOS logic device
group at IBM where he continues work on high-per-
formance CMOS. His current research interests in-
clude CMOS power/energy efficiency and scaling of
CMOS technology to below 10 nm.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003
Thomas S. Kanarsky received the B.S. degree in bi-
ology from St. Bonaventure University in 1979.
He joined IBM in 1979 and initially worked
on solder bump interconnect technology. He is
presently working in the Advanced Semiconductor
Technology Center, East Fishkill, NY, as a Staff
Development Engineer. He specializes in advanced
integration for exploratory devices and has worked
on such notable projects as vertical DRAM, strained
Si, FinFET, and ultra-thin SOI. He has authored
seven papers and holds nine patents.
Ying Zhang received the B.S. and M.S. degrees in physics from the Wuhan
University, China, in 1982 and 1984, respectively. He received the Ph.D. degree
in physics from the State University of New York at Albany in 1990.
From 1990 to 1993, he worked on plasma-surface interactions and processing
in IBM T. J. Watson Research Center, Yorktown Heights, NY, as his postdoctoral
work. From 1993 to 1996, he was with Tegal Corp. working on developing high-
density plasma processing tools and processes. Since 1996, he has been with
IBM as a Research Staff Member working at T. J. Watson Research Center on
plasma processing for advanced microelectronics applications.
Ronnen Roy, photograph and biography not available at time of publication.
Diane Boyd joined IBM Research in 1982. Over
the years, she has worked on both bipolar and
CMOS technologies. Currently, she is a member
of the Exploratory Devices Department at IBM
Microelectronics. She has been instrumental in
coordinating the fabrication of FinFET, damascene
gate, metal replacement gate, and strained silicon
devices. She has coauthored 16 papers and patents.
David Fried, photograph and biography not available at time of publication.
H.-S. Philip Wong received the Ph.D. degree in
electrical engineering from Lehigh University,
Bethlehem, PA, in 1988.
He joined the IBM T. J. Watson Research Center,
Yorktown Heights, NY, in 1988, as a Research Staff
Member. He is now Senior Manager of the Nanoscale
Materials, Processes, and Devices Department. His
department is responsible for defining and executing
IBM’s nanoscale science and technology roadmap.
Prior to this appointment, he was Senior Manager of
the Exploratory Devices and Integration Technology
Department. His department was responsible for defining and executing IBM’s
exploratory devices and technology roadmap for silicon technology. While he
has managed a wide range of technical activities from e-beam lithography, sil-
icon materials and devices, molecular electronics and assemblies, nanotech-
nology, to quantum device modeling, he maintains an active personal research
career that centers on solid-state devices, device physics and fabrication tech-
nology, system applications of nano- and microelectronic devices, and solid-
state image sensors.
Dr. Wong serves on the IEEE Electron Devices Society (EDS) as elected
AdCom member. He serves on the IEDM committee from 1998 to 2002 and
serves on the ISSCC program committee from 1998 to 2003. He is a Distin-
guished Lecturer of the IEEE Electron Devices Society. He has taught several
short courses at the IEDM, ISSCC, SOI, and SPIE conferences.