IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO.
11, NOVEMBER 2003
Sensitivity of Double-Gate and FinFET
Devices to Process Variations
Shiying Xiong and Jeffrey Bokor, Fellow, IEEE
Abstract—We investigate the manufacturability of 20-nm
double-gate and FinFET devices in integrated circuits by pro-
jecting process tolerances. Two important factors affecting the
sensitivity of device electrical parameters to physical variations
were quantitatively considered. The quantum effect was computed
using the density gradient method and the sensitivity of threshold
voltage to random dopant fluctuation was studied by Monte Carlo
V
simulation. Our results show the 3 value of T variation caused
by discrete impurity fluctuation can be greater than 100%. Thus,
engineering the work function of gate materials and maintaining a
nearly intrinsic channel is more desirable. Based on a design with
an intrinsic channel and ideal gate work function, we analyzed
the sensitivity of device electrical parameters to several important
physical fluctuations such as the variations in gate length, body
thickness, and gate dielectric thickness. We found that quantum
effects have great impact on the performance of devices. As a
result, the device electrical behavior is sensitive to small variations
of body thickness. The effect dominates over the effects produced
by other physical fluctuations. To achieve a relative variation of
electrical parameters comparable to present practice in industry,
we face a challenge of fin width control (less than 1 nm 3 value
of variation) for the 20-nm FinFET devices. The constraint of the
1 2 A
gate length variation is about 10 15%. We estimate a tolerance
of 3 value of oxide thickness variation and up to 30%
front-back oxide thickness mismatch.
Index Terms—Double gate, FinFET, Monte Carlo simulation,
process variations, quantum effect, sensitivity.
I. INTRODUCTION
A S THE GATE length of MOSFET devices shrinks down
below 20 nm, double-gate device structures are emerging
as strong candidates despite the added process complexity
needed to build such devices. Compared with conventional
single gate bulk MOSFETs, double-gate devices may be more
easily scaled down to 20 nm. This is because double-gate struc-
tures have better control of the short-channel effect and near
ideal turn-off slope, thus lower leakage level can be maintained
even with very short gate length. Double-gate MOSFETs are
thus more appropriate for low-power or high-performance ap-
plication in the future. The FinFET devices, which are actually
vertical double-gate MOSFET devices, have experimentally
demonstrated such potential capability [1].
Manuscript received February 21, 2003; revised August 12, 2003. This work
was supported by the UC-SMART program under Grant 97-03. The review of
this paper was arranged by Editor R. Shrivastava.
The authors are with the Department of Electrical Engineering and Com-
puter Sciences, University of California, Berkeley, CA 94720 USA (e-mail:
xiongsy@eecs.berkeley.edu).
Digital Object Identifier 10.1109/TED.2003.818594
0018-9383/03$17.00 © 2003 IEEE
2255
However, there are several challenges in building such
devices in CMOS technology. For a double-gate MOSFET
device with 20 nm or shorter gate length, in order to get
nearly ideal subthreshold swing and small drain induced
barrier lower (DIBL) effect, the silicon body must be very thin
( , where is the body thickness,
is the effective channel length, and is the oxide thickness)
and fully depleted [2]. The threshold voltage is insensitive to
channel doping except at very high concentration. We observed
less than a 50–mV shift of the threshold due to the channel
doping up to cm for a double-gate device with 20–nm
gate length and 5-nm body thickness. On the other hand,
excessive impurity concentrations can significantly degrade
the mobility of carriers, and we will see in the next section
that the statistical spread of the threshold voltage could be
very large due to random placement of discrete impurities
in the channel. Another choice is to have a nearly intrinsic
channel but engineer the work function of the gate materials
for control. According to the ITRS roadmap, the absolute
value of threshold voltage will be about 0.2 0.3 V for 20-nm,
low-power MOSFET devices. This means that we should have
a gate work function such that the Fermi energy lies between
the conduction band edge and midgap of silicon for NMOS
devices, and between midgap and the valence band edge of
silicon for pMOS devices. Polysilicon with dual type doping
(N and P ) has conventionally been used as highly conduc-
tive gate materials for bulk MOSFETs. However, there are no
handy gate materials with the required work functions for us
to do similar things for fully depleted double-gate MOSFET
devices with ultrashort channel length. Because of this reason,
there has recently been much research attempting to engineer
the work function of existing materials. There is more freedom
to adjust the threshold voltage of an asymmetric double-gate
device (e.g., we can choose two different types of materials for
its front and back gates [3], or use two different gate dielectric
thicknesses), but its manufacture will involve greater process
complexity. The large parasitic resistance between the channel
and source/drain (S/D)is another challenge to the performance
of FinFET devices [4].
In general, the fabrication process of double-gate MOSFET
devices (e.g., FinFET) is more complicated than that of single
gate devices, which will potentially bring more nonuniformity
during fabrication. For example, in FinFET devices, the gate
oxide is on the etched sidewall of the fin, and its uniformity
is more difficult to control. The channel-oxide interface con-
dition is determined by the sidewall roughness of the fin. In
this paper we first investigate the random and discrete nature
of dopant atoms in affecting the threshold voltage of symmetric
2256
TABLE I
NOMINAL PARAMETERS OF 20-nm SYMMETRIC DOUBLE-GATE DEVICES WITH INTRINSIC CHANNEL
Fig. 1. NMOS V shift due to channel doping.
double-gate devices. Then we study the sensitivity of electrical
parameters to several physical variations for the devices de-
signed with nearly intrinsic channel cm . The relative
changes of device electrical parameters under a given amount
of physical variations were calculated, from which we can find
the tolerable process variations that produce electrical varia-
tions comparable to those presently practiced in industry. The
simulators used are the TCAD tools from ISE1 . As a specific
example, we report the results for a device with 20-nm nom-
inal gate length and 5-nm nominal silicon body thickness. The
nominal physical and electrical parameters are listed in Table I,
where we define the electrical width as twice the fin height. The
gate of the device is ideal metal with adjustable work function.
The thickness of the spacers is small and parasitic resistance is
minimized. The device is calibrated for low power application
according to the ITRS roadmap with off-state current nearly 1
nA/ m for both NMOS and pMOS.
II. EFFECT OF DOPING FLUCTUATION ON THRESHOLD VOLTAGE
If heavily doped polysilicon is used as the gate material
of the double-gate devices, an intrinsic body gives a negative
threshold ( 0.19 V) for NMOS and a positive threshold (0.18
V) for pMOS devices. The threshold has to be shifted to the de-
sired values by channel implantation. Device simulation results
show that the threshold is not sensitive to channel doping when
the concentration is below cm (Fig. 1). Accordingly,
the required body doping concentration for NMOS devices
1ISE TCAD Software: A Package of Tools in Lithography, Process, Device
and Circuit Simulations From Integrated System Engineering (ISE). DESSIS is
the Tool for Multi-Dimensional Device Simulations
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 11, NOVEMBER 2003
Fig. 2. Random placement of impurities in device channel (N =
2e19=cm . Open circles: Channel dopants; Solid dots: S/D dopants).
will be over cm . Such large impurity concentration can
significantly degrade the mobility of carriers. In addition, if the
width of the device is also not large, the small volume of the
device channel region will just hold a few hundred or fewer
impurity atoms. For instance, a FinFET device has a limited
manufacturable fin height (H) if fin width (Tb) is small (Too
large H/Tb ratio may cause problems with etching and topog-
raphy). Assume a 50-nm fin height, 5-nm fin width, and 20-nm
gate length. This structure’s channel region will have 100 im-
purities when doped to cm . Because the randomness and
discrete nature of dopant atoms, the same macroscopic doping
profiles differ microscopically. For devices with minimized
geometry, both the fluctuation in the number of channel dopants
and their placement may cause significant device-to-device
performance variation. Traditional device simulation is based
on the locally continuum-doping model and the effect of the
discrete dopant distribution is ignored. Three-dimensional
(3-D) particle-based device simulation emerged only recently
and the effect has been considered for bulk MOSFETs [5], [6].
Because of the difficulties of including a sufficient number of
dopant atoms into the computation, the device width used in
simulation is typically very limited ( 50 nm) and results for
channel doping over cm were not reported. In our study
of the effect of random dopant placement on the threshold
voltage of 20-nm symmetric double-gate NMOSFET devices
with 5-nm body thickness and 50-nm width, up to cm
channel-doping concentration was considered. A realistic
3-D random doping profile was produced, and the average
was made along the width by two-dimensional (2-D) device
simulation. (Although 3-D device simulation results may be
more desirable, the unacceptably large computational burden
prevents us from getting statistically significant results from a
large number of simulations.) The density gradient method was
used to include the quantum confinement effect of inversion
carriers in the thin body. The dopant atoms were modeled as
discrete impurity dots (see Fig. 2). Such an approach is plau-
sible because dopants are easily ionized in the channel and act
XIONG AND BOKOR: SENSITIVITY OF DOUBLE-GATE AND FinFET DEVICES TO PROCESS VARIATIONS 2257

Fig. 3. NMOSV shift of RDDPDS from CDPDS (1V = V

V (RDDPDS) 0 V (CDPSD)). Fig. 4. NMOS variation due to random discrete dopant placement.

as random discrete charges in modulating the channel potential

profile. To produce the device doping profile, the channel was
cut from a much larger volume with uniform-random discrete
dopant distribution. The source and drain of the devices were
produced by random discrete Gaussian implantation. Twenty
simulations were performed for each macroscopic doping
profile with each simulation taking about 10 h.
We compared the threshold voltage from random
discrete dopant placement device simulations (RDDPDS)
with those from continuous doping profile device simulations
(CDPDS). We found that at low-channel concentration, the
mean threshold voltage in RDDPDS is slightly lower
than from CDPDS, which is consistent with the
results reported on bulk MOSFETs [5]. For the first time we
Fig. 5. NMOS V variation with body thickness (Squares: results from
pure classical modes; triangles: density gradient method).
see the mean in RDDPDS is higher than
calculated by CDPDS at high channel concentration. The
shift
is still fairly small up to cm (within 20 mV); above
cm the shift increases very rapidly and by cm
the underestimation of the by CDPDS reaches 110 mV
(Fig. 3). At lower channel concentrations cm , the
values of fluctuation caused by the random dopant effect
for the double-gate devices are smaller compared with results
reported from some small-width 3-D bulk MOSFET studies
[5]. The result is quite significant when the channel doping
concentration is well above cm . When the channel
dopant concentration reaches cm , we calculated a mean
about 0.18 V (with poly gate) and the 3 value of
variation is above 100% (Fig. 4). The variation caused by
random dopant placement in the S/D region was found to be
Fig. 6. pMOS V variation with body thickness (Squares: results from
pure classical modes; triangles: density gradient method).
small (1 of variation is about 3 mV for intrinsic channel)
because of the high concentration cm and steep profile
tivity analysis was then based on nearly intrinsic channel doping
(2 nm/dec).
and ideal gate work functions (the nominal device parameters
The variation caused by random dopant placement in the
are shown in Table I).
channel region might make it impossible to meet tight circuit
specifications required for manufacturing. If a device with much
longer width (W) is seen as the parallel connection of many un- III. EFFECT OF PROCESS VARIATION ON THRESHOLD VOLTAGE
correlated small width devices, the fluctuation decreases ac- From the simulated results of devices with an intrinsic
cording to . But in pursuit of minimum chip area, we channel, we found the absolute value of increases signifi-
favor the effort in looking for different gate materials and en- cantly with decreasing body thickness as shown in Fig. 5 and
gineering gate work function to minimize the random dopant 6. This is a consequence of two effects. First, as the silicon
effect for the double-gate devices. The following process sensi- body gets thinner, the two gates get closer and have better
2258 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 11, NOVEMBER 2003

control over the channel, reducing short channel effect and

roll-off. We can see this from the simulation results using
pure classical models. In addition, a significant part of the
change with body thickness is due to the quantum confinement
effect: as the body thickness decreases below 10 nm, a quantum
well is formed between the two gates. For electrons, the
quasicontinuous conduction band structures of bulk silicon
materials are replaced by a series of discrete 2-D subbands. The
lowest subband edge lies above the conduction band edge of
the bulk material. The energy states that the electrons occupy
in the quantum well are higher than those in the bulk material,
which means that the total energy of the inversion charge is
significantly raised, and more band bending is required to get
NMOS V
the same amount of inversion charge density as compared with
Fig. 7. variation with gate length.
the bulk case. As the body gets thinner, the energy states are
raised further in a narrower quantum well. Consequently, the
threshold voltage increases with decreasing body thickness.
The analysis for holes is quite similar. The confinement effect
is different in different quantization directions because of
different effective mass. For electrons the effect in the (110)
direction is larger than in the (100) direction. Two methods have
been employed by us to calculate the quantum effect in devices.
The first method solves the Poisson and the Schrodinger equa-
tions self-consistently and is appropriate for the case of small
. The second method is the density gradient method, which
introduces correction terms into the conventional drift-diffusion
equation and calculates the first order quantum effect by adding
the dependence of the energy of the electron gas on its density
gradient. The density gradient method has better convergence
Fig. 8. NMOS V variation with oxide thickness.
and can be applied to the multi-dimensional and large S/D bias
case. As a comparison, the linear threshold voltages
nominal gate length for NMOS and 10 mV/nm for pMOS de-
of devices were extracted by linear extrapolation in the triode
vices. As the gate dielectric gets thinner, the gate voltage con-
region at lower S/D voltage in all three
trols the channel more effectively. The effect of drain-induced
(Schrodinger, density gradient and classical) methods. In our
devices, the two quantum methods gave very close results barrier lower (DIBL) also reduces. As a result, increases
with decreasing oxide thickness, as shown in Fig. 8. We found
(within 10 mV difference) for . The saturation threshold
about 5 mV change in for every 1 of oxide thick-
voltages were extracted at constant current level
ness variation for both NMOS and pMOS devices. The threshold
for in both density gradient and pure classical
methods. For NMOS, around the nominal body thickness, we voltage is not subjected to channel doping variation here be-
cause the silicon body in the designed devices is nearly intrinsic
found that changes about 16 mV for every nanometer
cm . The variation of source and drain diffusion
of body thickness change (written as 16 mV/nm) and
length can vary the threshold voltage for large decay length (The
changes about 33 mV/nm. The simulation results of the
threshold of pMOS devices with different body thickness are S/D-channel junctions are less abrupt), which can be lumped
into the channel length variation.
shown in Fig. 6. We found around the nominal body thickness,
changes 18 mV/nm and changes 38 mV/nm.
These results are slightly larger than those for NMOS devices. IV. EFFECTS OF PROCESS VARIATION ON CURRENT
Our results are in good general agreement with the published For symmetric double-gate devices with longer channel and
theoretical calculations of the same effect [7], [8]. Comparison thicker body ( 10 nm), twin independent channels will be
to experimental results is complicated by extrinsic factors formed when the device is turned on. Here we found a mod-
such as thin film mobility and short channel effects. shifts erate dependence of drive current on the body thickness for the
extracted from capacitance–voltage (C–V) measurements are 20-nm devices (Fig. 9). The change of around the nominal
generally smaller than those extracted from current–voltage body thickness (5 nm) is 5 7% for each-nm of body thickness
(I–V) measurements ([7], [9]) for those reasons and tend to give variation. We can also see that is significantly lowered
better agreement with our and other simulations [7], [8]. due to quantum effects. For the nominal device, we have 120
The dependence of on gate length is well known. From m ( 16%) reduction of the drive current in the quantum
Fig. 7, we can see the threshold of the NMOS devices rolls off simulation in comparison with the pure classical case. The
exponentially for shorter gate length due to short channel effect. degradation is because of the increase caused by quantum
The variation of with gate length is 9 mV/nm around the confinement and the effective gate capacitance decrease (the
XIONG AND BOKOR: SENSITIVITY OF DOUBLE-GATE AND FinFET DEVICES TO PROCESS VARIATIONS
Fig. 9. NMOS I variation with body thickness.
Fig. 10. NMOS I variation with body thickness.
peak concentration of the inversion charge is away from the
Si SiO interface). When the body thickness falls below 5 nm,
ignoring quantum effect will bring significant overestimation
of leakage current (Fig. 10). The dramatic change of off-state
current ( 5x/nm around nm) is again the result of
threshold voltage change with different body thickness. The
high sensitivity of leakage current to body thickness variation
may limit the application of the devices in low power ICs. The
device gate length is many times larger than the dimension of
the body thickness. As a result, the current is less sensitive to
variation of gate length than to body thickness. The simulation
results show that the change of leakage with channel length is
about 1.7x/nm and change of on-state current is 2 3%/nm.
V. EFFECTS OF PROCESS VARIATION ON DIBL AND SWING
The sub-threshold swing depends more strongly on the body
thickness than other physical parameters. For NMOS devices,
from Fig. 11 we can see that the swing is smaller than 70 mV/dec
when the body thickness is less than 6 nm for the 20-nm sym-
metric double-gate devices. The change of the sub-threshold
swing is 4 mV/dec per nanometer of body thickness variation.
The DIBL effect of the double-gate device increases quadrati-
cally with the body thickness (Fig. 12). The nominal device has
a DIBL of about 50 mV. The DIBL variation rate around the
5-nm body thickness is 17 mV/nm.
2259
Fig. 11. Variation of subthreshold swing with body thickness (NMOS).
Fig. 12. Variation of DIBL (V 0 V ) with body thickness
(NMOS).
VI. THREE SIGMA STATISTICS OF PARAMETER VARIATIONS
From the above simulation results, we can make a statistical
calculation of the 3 values of device electrical parameter vari-
ations, which helps us optimize the nominal parameters and
determine the reasonable process tolerance for devices in cir-
cuits designed for manufacture. In the following example, we
looked for the corresponding physical parameter variations that
produce the device electrical fluctuations comparable to typical
logic circuit design requirements. The contributions to device
electrical parameter variations by small changes of physical pa-
rameters are assumed to be independent as expressed in (1). The
contribution from the variation of each physical parameter and
the 3 values of each electrical parameter are listed in Table II.
(1)
We found a total relative threshold voltage variation in the range
of 20% and drive current variation of . The sub-
threshold swing is 68 6 mV for NMOS and 70 6 mV for
pMOS. The highest leakage is five times larger than that of the
nominal device. By considering the results in the table, we see
that the body thickness variation is dominant. Less than 1 nm 3
value of line width control is a challenge because typical current
2260
TABLE II
3 VALUES OF DEVICE ELECTRICAL PARAMETER VARIATIONS (IN EACH CASE, TWO
ARE GIVEN. THE FIRST IS FOR NMOS AND THE SECOND FOR pMOS DEVICES)
lithography processes have 10 larger CD variations. Applica-
tion of FinFET devices in IC products will strongly depend on
the success in tight fin width control from emerging technolo-
gies. Our results show a 2 3 nm allowable gate length varia-
tion, which is less tight than the requirement on body thickness.
planar oxide thickness variation is now obtainable by
the industry.
VII. MISMATCH OF THE OXIDE THICKNESS
Unlike the planar MOSFET devices, the gate dielectric of
FinFET devices is vertical. Its thickness and the Si SiO inter-
face are affected by sidewall slope and roughness of the fin. We
may expect some difficulties to get the same uniformity as the
planar case. Here we considered the effect of possible thickness
mismatch of the two layers of gate dielectric in the 20-nm sym-
metric double-gate devices. For convenience we did not include
the gate leakage current in the analysis. Defining the mismatch
as , the devices can tol-
erate up to 30% of the mismatch with only slight variation of the
electric parameters: less than 3 mV of variation, less than 1
mV/dec change of sub-threshold swing, less than 4% of increase
of drive current and 12% of off-state current. For FinFETs, the
rough Si SiO interface will potentially degrade the device
performance and needs further study.
VIII. CONCLUSION
We have studied the sensitivity of double-gate and FinFET
device electrical parameters to process variations. For devices
with 20-nm nominal gate length and 5-nm body thickness, large
channel doping concentration is necessary to obtain suitable
values of threshold voltage if heavily doped polysilicon gates
are used. Because the total volume of the channel region is
small, the channel doping in turn will bring uncontrollable
fluctuations due to the randomness and discrete nature of
dopant atoms. Thus, heavily doped polysilicon may not be a
viable choice as the gate material. Engineering the gate work
function is a more desirable approach to minimize the random
dopant effect. Quantum confinement plays an important role in
affecting the performance of devices with small body thickness.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 11, NOVEMBER 2003
NUMBERS
As a result, the threshold voltage and current more strongly
depend on the body thickness. For 20-nm physical gate length
and 5-nm body thickness (or fin width), we predict that 3
values of body thickness variation must be controlled under
1 nm to meet the present logic circuit design requirement.
The acceptable 3 value of gate length variation is 2 3 nm.
Excluding possible gate leakage current increase, the device
structure can tolerate 3 value of oxide thickness
variation and up to 30% front-back oxide thickness mismatch
without degrading the electrical performance greatly.
ACKNOWLEDGMENT
The authors wish to acknowledge the longtime support of
TCAD vendors ISE in providing their most advanced simula-
tion tools to make the simulation possible.
REFERENCES
[1] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski,
E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J.
King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: pMOS,” in IEDM Tech.
Dig., 1999, pp. 67–70.
[2] G.Gen Pei, V. Narayanan, Z. Liu, and E. C. Kan, “3-D analytical sub-
threshold and quantum mechanical analysis of double-gate MOSFET,”
in IEDM Tech. Dig., 2001, pp. 103–106.
[3] Y. Taur, “Analytic solutions of charge and capacitance in symmetric
and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices,
vol. 48, pp. 2861–2869, Dec. 2001.
[4] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J.
King, J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,”
in IEDM Tech. Dig., 2001, pp. 421–424.
[5] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo mod-
eling of threshold variation due to dopant fluctuations,” in VLSI Tech.
Dig., 1999, pp. 169–170.
[6] T. Ezaki, T. Ikezawa, and M.Masami Hane, “Investigation of realistic
dopant fluctuation induced device characteristics variation for Sub-100
nm CMOS by using atomic 3-D process/device simulator,” in IEDM
Tech. Dig., 2002, pp. 311–314.
[7] K. Uchida, J. Koga, R. Ohba, T. Numata, and S. Takagi, “Experimental
evidences of quantum-mechanical effects on low-field mobility, gate-
channel capacitance, and threshold voltage of ultrathin body SOI MOS-
FETs,” in IEDM Tech. Dig., 2001, pp. 633–636.
[8] H. Majima, H. Ishikuro, and T. Hiramoto, “Experimental evidence for
quantum mechanical narrow channel effect in ultra-narrow MOSFETs,”
IEEE Electron Device Lett., vol. 21, pp. 396–398, Aug. 2000.
[9] Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, “Ultra-thin body pMOSFETs
with selectively deposited Ge source/drain,” in VLSI Tech. Dig., 2001,
pp. 19–20.
XIONG AND BOKOR: SENSITIVITY OF DOUBLE-GATE AND FinFET DEVICES TO PROCESS VARIATIONS
Shiying Xiong received the B.S. and M.S. degrees in
applied physics from Tsinghua University, Beijing,
China, in 1995 and 1998, respectively. From 2000,
he joined the University of California, Berkeley, to
study for the Ph.D. degree in solid state devices.
He did research on semiconductor quantum well
structures and high-Tc superconducting materials
at Tsinghua University. From 1998 to 2000, he was
studying at the Physics Department of the University
of California, Berkeley. His research at Berkeley
was on optimizing the performance of advanced
MOSFET transistors and investigating the impacts of process variations. His
current research interests are electrical transport in ultrascaled devices and
nanocontacts.
2261
Jeffrey Bokor (S’75–M’90–SM’95–F’00) received
the B.S. degree in electrical engineering from the
Massachusetts Institute of Technology, Cambridge,
in 1975, and the M.S. and Ph.D. degrees in electrical
engineering from Stanford University, Stanford, CA,
in 1976 and 1980, respectively.
He held management positions as Head of the
Laser Science Research Department at Bell Labs,
Holmdel, NJ, from 1987 to 1990, and Head of the
ULSI Technology Research Department at Bell
Labs, Murray Hill, NJ, from 1990 to 1993. During
these years, he did research on novel sources of ultraviolet and soft X-ray
coherent radiation, advanced lithography, picosecond optoelectronics, semi-
conductor physics, surface physics, MOS device physics, and integrated circuit
process technology. He was appointed Professor of electrical engineering and
computer sciences at the University of California, Berkeley, CA, in 1993, with
a joint appointment at the Lawrence Berkeley National Laboratory, Berkeley.
His current research activities include novel techniques for nanofabrication,
new devices for nanoelectronics, and extreme ultraviolet lithography.
Dr. Bokor is a Fellow of the APS and OSA.