Professional Documents
Culture Documents
Fig. 2. S/D doping profile used in this study. Doping level of the uniform
2
region is 3 10 cm , and that in the nonuniform region decays with a
Gaussian tail whose characteristic length of 4 nm and the junction abruptness
was about 2.5 nm/decade. The effective device width is defined as the length
of junction which is controlled by the gate.
(a)
To investigate the device short-channel effect, a simple drift-
diffusion model is used as it is enough for our purpose. This
model is also enough for studying the trend of the device current.
The gate voltage, which results in 0.1 A per unit-device
width in micrometers, was chosen to be the threshold voltage
of the device. We used twice the SOI thickness as the device
width, which is generally the case in FinFET. We adjusted the
threshold voltage of FinFET at V to be 0.2 V by
varying the gate workfunction, and this is consistent with the
previous study reported by Chang [2]. Doping level of boron
doped p-type channel was 1 10 cm , and the gate oxide
was 2 nm.
In this paper, short-channel effect was evaluated using drain- (b)
induced barrier lowering (DIBL) as a major parameter. DIBL
Fig. 3. DIBL and drain saturation current characteristics of various devices
was obtained from the change of threshold voltage as drain bias with a nonuniform S/D doping profile. (a) T =30 nm. (b) T = 50 nm.
changes 1 V. Drain saturation current was the current when In both cases, L = 36 nm, T = 2 nm.
V. Total currents of the devices with dif-
ferent SOI thicknesses were compared, and they were not di-
profiles along the channel direction ( direction) for the 70-nm
vided by the channel width. We took this approach, since the
SOI device are shown. As is fixed to 30 nm, potential pro-
important factor in the very large scale integration (VLSI) ap-
files at 0 nm and 10 nm show no difference. At 30
plication is a planar active area of the device, and the drive cur-
nm, the potential is lower than that of the upper region, and its
rent can be controlled by the number of fins, not necessarily by
minimum point moves to drain, which means the reduced lat-
the variation of device width [6].
eral electric field at that region. The junction crosses the gate
edge at 46 nm when 30 nm, potentials below this
III. SIMULATION RESULTS point become smaller as the depth increases, and there also ex-
Fig. 3 shows DIBL and drain saturation current character- ists a lateral electric field. For the 30-nm SOI device, the lateral
istics of the simulated devices. The effect of the increase of electric field near 30 nm is the same as those of the upper
SOI thickness ( ) with fixed uniform doping profile depth region.
( ) is shown in Fig. 3(a), and that of the increase of doping Hence, the reduction of DIBL can be explained by Fig. 5.
profile depth at fixed of 50 nm is shown in Fig. 3(b). Channel region I has a shorter channel length ( ) than the
In the device with fixed at 30 nm, varied from other regions (II and III), and has a higher channel potential due
30–80 nm. In this case, DIBL reduces and drain saturation cur- to the applied drain bias. Due to the difference in channel poten-
rent ( ) increases, with an increase of . For the same tial, a vertical electric field is generated from the shorter
, smaller causes reduced DIBL and smaller drain region to the longer region, as shown in Fig. 5. This vertical elec-
saturation current. tric field reduces the lateral electric field at the smaller channel
To investigate the origin of reduced DIBL, we obtained the region according to Gauss’ law, and causes smaller DIBL. This
potential profiles of each device along the vertical or the width phenomenon is similar to the “Pi-gate MOSFET” proposed by
direction ( direction) at the channel center ( ) just be- Park [5]. According to Gauss’ law, the lateral electric field at the
neath the gate oxide, and channel interface ( nm) from longer channel region can also be explained.
the Si/SiO interface. This is shown in Fig. 4(a). Drain saturation current becomes larger for the device with
For a 30-nm device, channel potential has a uniform pro- thicker SOI. In Fig. 3(a), this may be caused by the increase of
file, but the 50- and 70-nm devices show nonuniform potential the current path in the channel region, not by the increase of ef-
profiles along the vertical direction ( direction). This implies fective device width as the doping profile is fixed. The term “ef-
that there exists a vertical electric field from the shorter channel fective device width” is arbitrarily defined as the junction length
length ( ) region to the longer region. In Fig. 4(b), potential which overlaps with the gate. The increase of current path in the
WOO et al.: ELECTRICAL CHARACTERISTICS OF FINFET WITH VSOURCE/DRAIN PROFILE 235
(a)
Fig. 6. DIBL and drain saturation current of the devices with T =
30, 50, and 70 nm, and S/D doped by As ion implantation at the dose
2
of 5 10 cm . Implantation energy was varied to be 10, 15, 20, 25,
and 30 keV.
REFERENCES
[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,
E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned
double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron De-
vices, vol. 47, pp. 2320–2325, Dec. 2000.
[2] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate length scaling
and threshold voltage control of double-gate MOSFET’s,” in Tech. Dig.
IEDM, 2000, pp. 719–722.
[3] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King,
J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” in Tech.
Dig. IEDM, 2001, pp. 421–424.
[4] J. Kedzierski and H. -S. Philip Wong, “High-performance sym-
metric-gate and CMOS-compatible V asymmetric-gate FinFET
devices,” Tech. Dig. IEDM, pp. 437–440, 2001.
Fig. 7. Maximum allowable channel thickness (W ) considering DIBL [5] J.-T. Park, J.-P. Colinge, and C. H. Diaz, “Pi-Gate SOI MOSFET,” IEEE
constraints (< 100 mV/V) only. Electron Device Lett., vol. 22, pp. 405–406, Aug. 2001.
[6] S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V.
Subramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET-a quasi-planar
double-gate MOSFET,” in Proc. IEEE Int. Solid State Circuits Conf.,
2001, pp. 118–119.
Byung-Yong Choi received the B.S. degree in 1985 and served as the Director until 1989. He served as the Chairman of the
electronic engineering from Kyungpook National Electronics Engineering Department from 1994 to 1996. He was with Samsung
University, Taegu, Korea, in 1998. He received Display Devices Co., Ltd., as the Head of Display R&D Center in 1996, on leave
the M.S. degree from the School of Electrical from Seoul National University. He concentrated his study on the image sensors
Engineering, Seoul National University, Seoul, such as Vidicon type, MOS type, and also CCDs, for Samsung Display Devices
Korea, in 2000. Since 2000, he has been working Co. and Samsung Electronics Co. from 1984 to 1991. His current research inter-
toward the Ph.D. degree at the same university. ests include sub-0.1-m CMOS structure and technology, FEDs, CMOS image
His current research interests are nanoscale CMOS sensor, and high-speed SRAM design. He has published over 130 papers in the
device modeling, characterization, and fabrication. major international scientific journals, including over 65 SCI papers. He has
presented more than 180 papers, including 80 international conference papers.
He also has registered 11 U.S., three Japanese, and eight Korean patents.
Dr. Lee is a member of the Steering Committees for IVMC (International
Vacuum Microelectronics Conference) and KCS (Korean Conference on Semi-
Young-Jin Choi received the B.S. and M.S. degrees conductors). He was the Conference Chairman of IVMC’97 and KCS’98 who
from the School of Electrical Engineering, Seoul Na- led the IVMC’97 and the KCS’98. He was also a member of the IEDM (Inter-
tional University, Seoul, Korea, in 1994 and 1996, re- national Electron Devices Meeting) Subcommittee on Detectors, Sensors, and
spectively. Since 1996, he has been working toward Displays, IEEE Electron Devices Society, from 1998 to 1999. In June 1999, he
the Ph.D. degree at the same university. was elected First President of the Korean Information Display Society.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.