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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO.

4, DECEMBER 2002 233

Electrical Characteristics of FinFET With Vertically


Nonuniform Source/Drain Doping Profile
Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, Member, IEEE,
and Byung-Gook Park, Member, IEEE

Abstract—The effects of a nonuniform source/drain (S/D)


doping profile on the FinFET characteristics are investigated
using three-dimensional device simulation. With a fixed S/D
doping profile, larger silicon-on-insulator (SOI) thickness can
suppress short-channel effects due to the coexistence of longer
channel regions. There can be some design margin in the channel
thickness due to this reduced short-channel effect. Drain satu-
ration current in FinFET is proportional to the effective device
width and SOI thickness.
To determine the appropriate SOI thickness of FinFET, alter-
nating current (ac) characteristics are investigated. Device capaci-
tance increases with SOI thickness, but this is not for the gate delay, Fig. 1. Device structure used in this study. Two gates are located at both sides
as the drive current also increases and compensates for the increase of an ultra-thin channel. As S/D doping is performed vertically (y direction)
of capacitance. When driving a constant capacitance load such as nonuniformly, device channel length (L ) varies along the device width
direction (y direction). S/D is located at the far end of channel direction (x
interconnect, devices with larger drain current or thicker SOI are direction).
more favorable for the fixed S/D doping condition.
Index Terms—Double-gate, FinFET, nonuniform source/drain if the S/D regions fan out right at the channel edge, tilted
(S/D), silicon-on-insulator (SOI).
implantation would not be very useful. Another example would
be a multifin device with high aspect ratio fins. Tilted extension
I. INTRODUCTION implants may not be adequate, due to shadow effect. Besides,
zero or small-angle implant is simpler and easier in terms of
A S CMOS dimensions shrink down into a few tens of
nanometer regime, double-gate (DG) MOSFETs attract
much attention due to their robustness to the short-channel
fabrication, as long as the device characteristics do not show
degradation.
In this paper, we have studied the effects of a nonuniform
effect. Among DG CMOS devices, the “FinFET” [1] reported
doping profile along the device width direction on the device
by Hisamoto et al., is considered to be the most promising
characteristics using analytical profiles. Following that, the
candidate due to its simple process, which is compatible with
behavior of the device’s electrical characteristics is discussed.
the conventional planar process.
Finally, we present the device design guidelines for those
There have been many simulation studies on the DG
device geometrical parameters such as silicon-on-insulator
MOSFET [2], but those studies were performed using the
(SOI) thickness, using real doping profiles obtained from the
two-dimensional (2-D) device simulation. That was reasonable,
2-D process simulation.
as the FinFET with a vertically uniform source/drain (S/D)
doping profile has no 3-D structural issue. The first “FinFET”
[1] structure has highly doped polysilicon as an S/D pad. II. SIMULATION SCHEME
However, to dope the S/D region of FinFET for CMOS, ion im- The device used in this study is shown in Fig. 1. Two gates are
plantation is necessary. Recent researches on FinFET reported located at both sides of an ultra-thin channel. As S/D doping is
by Choi [3] and Kedzierski [4] used an ion-implantation process performed vertically ( direction) nonuniformly, device channel
to dope the S/D region. A vertically uniform S/D doping profile length ( ) varies along the device width direction ( direc-
can be obtained in a single-fin device through a tilted extension tion). S/D is located at the end of channel direction ( direction).
implant. There are, however, some cases in which a uniform In this paper, S/D doping profile is invariant along the di-
S/D doping profile cannot be easily obtained. For example, rection. To investigate electrical characteristics of the device,
a 2-D doping profile is enough. A simple analytical profile is
Manuscript received June 8, 2002; revised October 9, 2002. This work was shown in Fig. 2. Dopant concentration of the uniform region
supported by the BK21 Program, by the National Research Laboratory Project was 3 10 cm and it decays with a Gaussian tail outside
of Ministry of Science and Technology, Korea, and by the Collaborative Project the uniform region. The characteristic length of the Gaussian
for Excellence in Basic System IC Technology. This paper was presented in part
at the 2002 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, June 9–10, tail is fixed to 4 nm in this paper, and the junction abruptness
2002. was about 2.5 nm/decade along the channel length direction.
The authors are with the Interuniversity Semiconductor Research Center The latter part of this paper treats real doping profiles obtained
(ISRC) and School of Electrical Engineering, Seoul National University, Seoul
151-742, Korea (e-mail: woods@smdl.snu.ac.kr; bgpark@snu.ac.kr). from ion implantation and thermal annealing. In that case, 2-D
Digital Object Identifier 10.1109/TNANO.2002.807373 doping profiles were obtained from the 2-D process simulation.
1536-125X/02$17.00 © 2002 IEEE
234 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002

Fig. 2. S/D doping profile used in this study. Doping level of the uniform
2
region is 3 10 cm , and that in the nonuniform region decays with a
Gaussian tail whose characteristic length of 4 nm and the junction abruptness
was about 2.5 nm/decade. The effective device width is defined as the length
of junction which is controlled by the gate.
(a)
To investigate the device short-channel effect, a simple drift-
diffusion model is used as it is enough for our purpose. This
model is also enough for studying the trend of the device current.
The gate voltage, which results in 0.1 A per unit-device
width in micrometers, was chosen to be the threshold voltage
of the device. We used twice the SOI thickness as the device
width, which is generally the case in FinFET. We adjusted the
threshold voltage of FinFET at V to be 0.2 V by
varying the gate workfunction, and this is consistent with the
previous study reported by Chang [2]. Doping level of boron
doped p-type channel was 1 10 cm , and the gate oxide
was 2 nm.
In this paper, short-channel effect was evaluated using drain- (b)
induced barrier lowering (DIBL) as a major parameter. DIBL
Fig. 3. DIBL and drain saturation current characteristics of various devices
was obtained from the change of threshold voltage as drain bias with a nonuniform S/D doping profile. (a) T =30 nm. (b) T = 50 nm.
changes 1 V. Drain saturation current was the current when In both cases, L = 36 nm, T = 2 nm.
V. Total currents of the devices with dif-
ferent SOI thicknesses were compared, and they were not di-
profiles along the channel direction ( direction) for the 70-nm
vided by the channel width. We took this approach, since the
SOI device are shown. As is fixed to 30 nm, potential pro-
important factor in the very large scale integration (VLSI) ap-
files at 0 nm and 10 nm show no difference. At 30
plication is a planar active area of the device, and the drive cur-
nm, the potential is lower than that of the upper region, and its
rent can be controlled by the number of fins, not necessarily by
minimum point moves to drain, which means the reduced lat-
the variation of device width [6].
eral electric field at that region. The junction crosses the gate
edge at 46 nm when 30 nm, potentials below this
III. SIMULATION RESULTS point become smaller as the depth increases, and there also ex-
Fig. 3 shows DIBL and drain saturation current character- ists a lateral electric field. For the 30-nm SOI device, the lateral
istics of the simulated devices. The effect of the increase of electric field near 30 nm is the same as those of the upper
SOI thickness ( ) with fixed uniform doping profile depth region.
( ) is shown in Fig. 3(a), and that of the increase of doping Hence, the reduction of DIBL can be explained by Fig. 5.
profile depth at fixed of 50 nm is shown in Fig. 3(b). Channel region I has a shorter channel length ( ) than the
In the device with fixed at 30 nm, varied from other regions (II and III), and has a higher channel potential due
30–80 nm. In this case, DIBL reduces and drain saturation cur- to the applied drain bias. Due to the difference in channel poten-
rent ( ) increases, with an increase of . For the same tial, a vertical electric field is generated from the shorter
, smaller causes reduced DIBL and smaller drain region to the longer region, as shown in Fig. 5. This vertical elec-
saturation current. tric field reduces the lateral electric field at the smaller channel
To investigate the origin of reduced DIBL, we obtained the region according to Gauss’ law, and causes smaller DIBL. This
potential profiles of each device along the vertical or the width phenomenon is similar to the “Pi-gate MOSFET” proposed by
direction ( direction) at the channel center ( ) just be- Park [5]. According to Gauss’ law, the lateral electric field at the
neath the gate oxide, and channel interface ( nm) from longer channel region can also be explained.
the Si/SiO interface. This is shown in Fig. 4(a). Drain saturation current becomes larger for the device with
For a 30-nm device, channel potential has a uniform pro- thicker SOI. In Fig. 3(a), this may be caused by the increase of
file, but the 50- and 70-nm devices show nonuniform potential the current path in the channel region, not by the increase of ef-
profiles along the vertical direction ( direction). This implies fective device width as the doping profile is fixed. The term “ef-
that there exists a vertical electric field from the shorter channel fective device width” is arbitrarily defined as the junction length
length ( ) region to the longer region. In Fig. 4(b), potential which overlaps with the gate. The increase of current path in the
WOO et al.: ELECTRICAL CHARACTERISTICS OF FINFET WITH VSOURCE/DRAIN PROFILE 235

(a)
Fig. 6. DIBL and drain saturation current of the devices with T =
30, 50, and 70 nm, and S/D doped by As ion implantation at the dose
2
of 5 10 cm . Implantation energy was varied to be 10, 15, 20, 25,
and 30 keV.

channel potentials with different channel lengths ( ’s). In


the next section, we will investigate the effect of a nonuniform
S/D doping profile using the ion-implanted doping profiles
obtained from the 2-D process simulation. Oxide spacers
with a width of 50 nm were formed at each side of the gate
to prevent the S/D profiles merging. For the MOSFET, As ,
5 10 cm was implanted with various energies, followed
by a 1000 C, 10-s annealing process. Implantation energies
(b)
were 10, 15, 20, 25, and 30 keV. When obtaining an S/D doping
profile, the transient-enhanced diffusion (TED) model was
Fig. 4. (a) Vertical channel potential of the devices with T = 30 nm and
T = 30, 50, and 70 nm. (b) Lateral channel potential of 70-nm T device
ignored as the accurate profile was not necessary.
=
at various points (y 0, 10, 30, 40, 50, and 70 nm). Fig. 6 shows the DIBL and drain saturation current of the
devices. As mentioned previously, drain saturation current in-
creases as increases for the same S/D doping condition.
This can be explained by the increase of current path. For the
same , drain saturation current increases until some implan-
tation energy and it decreases for the further increase of implan-
tation energy. The energies were 20, 25, and 30 keV for the 30,
50, and 70 nm , respectively. This can be explained by the
change of effective device width, as it depends on the SOI thick-
ness and implantation energy.
In the fabrication of FinFET, the channel thickness is the crit-
ical dimension. This is the limiting factor in the scaling down
of FinFET. Using a vertically nonuniform S/D doping profile,
Fig. 5. Schematic diagram which explains the reduction of DIBL for the the short-channel effect can be reduced to some extent. For the
device with a vertically nonuniform S/D doping profile. Channel region I has devices with ion-implantation doped S/D, there would be some
a shorter channel length (L ) than the other regions (II, III), and has higher
channel potential due to the drain bias. This difference in potential causes the margin in the design of FinFET. Fig. 7 shows the maximum al-
vertical electric field to be generated from the shorter L region (region I) to lowable channel thickness ( ) of the FinFET which satisfies
longer regions (region II, III). the DIBL constraint of 100 mV/V. For the same S/D doping pro-
file, a thicker SOI device allows larger .
channel region can be verified by the lateral electrical field in the For the fixed S/D doping geometry, the device with a larger
longer channel region shown in Fig. 4(b). The result of effective shows larger drain saturation current and smaller DIBL.
device width change is shown in Fig. 3(b). By increasing , However, an increase of can result in large capacitance. In
we can increase effective device width, and the current stops in- FinFET, the main component is gate capacitance. The junction
creasing until the effective device width reaches maximum. In capacitance of FinFET can be ignored as the device is built on
Fig. 3(b), the depth of the uniform doping region ( ) is thick buried oxide. To evaluate the ac characteristics of FinFET,
45 nm, and the point where the junction profile crosses the gate gate capacitance at V and V was ob-
edge is 49 nm. This is where effective device width is maximum tained by applying a small signal to the gate and extracting the
at the device with an SOI thickness of 50 nm. change of gate charge. Signal frequency was 1 MHz. Each de-
In the previous section, we discussed the reason for the vice has a different channel thickness obtained in Fig. 7, and this
reduction of DIBL. The main reason was interaction between means there are no differences in short-channel effect. Using the
236 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002

REFERENCES
[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,
E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned
double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron De-
vices, vol. 47, pp. 2320–2325, Dec. 2000.
[2] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate length scaling
and threshold voltage control of double-gate MOSFET’s,” in Tech. Dig.
IEDM, 2000, pp. 719–722.
[3] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King,
J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” in Tech.
Dig. IEDM, 2001, pp. 421–424.
[4] J. Kedzierski and H. -S. Philip Wong, “High-performance sym-
metric-gate and CMOS-compatible V asymmetric-gate FinFET
devices,” Tech. Dig. IEDM, pp. 437–440, 2001.
Fig. 7. Maximum allowable channel thickness (W ) considering DIBL [5] J.-T. Park, J.-P. Colinge, and C. H. Diaz, “Pi-Gate SOI MOSFET,” IEEE
constraints (< 100 mV/V) only. Electron Device Lett., vol. 22, pp. 405–406, Aug. 2001.
[6] S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V.
Subramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET-a quasi-planar
double-gate MOSFET,” in Proc. IEEE Int. Solid State Circuits Conf.,
2001, pp. 118–119.

Dong-Soo Woo received the B.S. and M.S. degrees


from the School of Electrical Engineering, Seoul Na-
tional University, Seoul, Korea, in 1996 and 1998, re-
spectively. Since 1998, he has been working toward
the Ph.D. degree at the same university.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.
Fig. 8. Calculated C V =I gate delay (t ). Capacitance is the gate capacitance.
V = 1:0 V, V 0 V = 0:8 V, and the maximum channel thickness
(W ) was chosen from Fig. 7.

gate capacitance, gate delay was calculated and shown in


Fig. 8. Each gate delay shows no dependency on the drain
saturation current. This is because the capacitance also changes
Jong-Ho Lee received the B.S. degree in electronic
with SOI thickness and the channel thickness. Anyway, there is engineering from Kyungpook National University,
so small a difference in gate delay, less than 6% in its value, de- Taegu, Korea, in 1987. He received the M.S. and
spite about 230% difference in SOI thickness. Ph.D. degrees from Seoul National University,
Seoul, Korea, in 1989 and 1993, respectively, both
Moreover, there can be a case when the device drives a con- in electronic engineering.
stant capacitance load, such as an interconnect. In that case, the In 1983, he worked on advanced BiCMOS process
device with larger drain saturation current is better, as the delay development at the Interuniversity Semiconductor
Research Center (ISRC), Seoul National University,
is inversely proportional to the drain saturation current. Hence, as an Engineer. From 1994 to 2001, he was a faculty
the optimum should be determined considering system de- member of Wonkwang University, Iksan, Korea.
tails. In 2002, he joined the School of Electronics and Electrical Engineering,
Kyungpook National University, Daegu, Korea. From 1994 to 1998, he
was with ETRI as an Invited Member of Technical Staff, working on deep
IV. CONCLUSION submicrometer SOI devices, device isolation, 1/f noise, and device mismatch
characterization. From August 1998 to July 1999, he was with the Massachu-
The effects of a nonuniform S/D doping profile on the FinFET setts Institute of Technology (MIT), Cambridge, as a Postdoctoral Researcher,
characteristics were investigated using a 3-D device simulation. where he was engaged in research on sub-100–nm double-gate CMOS devices.
His research interests include sub-100–nm CMOS technologies, SiGe HBT,
With a fixed S/D doping profile, larger SOI thickness can sup- high-performance IC design, and microsystems.
press short-channel effect due to the effect of a longer channel
region. So, there can be some design margin in the channel
thickness, due to this reduced short-channel effect. Drain sat-
uration current in FinFET is proportional to the effective device
width and SOI thickness. Woo Young Choi received the B.S. and M.S. degrees
To determine the optimum SOI thickness of FinFET, ac char- from the School of Electrical Engineering, Seoul Na-
tional University, Seoul, Korea, in 2000 and 2002, re-
acteristics are also investigated. Device capacitance increases spectively. Since 2002, he has been working toward
with SOI thickness, but this is not necessarily the case for the the Ph.D. degree at the same university.
gate delay, as the drive current also increases and compensates His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.
for the increase of capacitance. When driving a constant capaci-
tance load such as interconnect, devices with larger drain current
or thicker SOI are more favorable.
WOO et al.: ELECTRICAL CHARACTERISTICS OF FINFET WITH VSOURCE/DRAIN PROFILE 237

Byung-Yong Choi received the B.S. degree in 1985 and served as the Director until 1989. He served as the Chairman of the
electronic engineering from Kyungpook National Electronics Engineering Department from 1994 to 1996. He was with Samsung
University, Taegu, Korea, in 1998. He received Display Devices Co., Ltd., as the Head of Display R&D Center in 1996, on leave
the M.S. degree from the School of Electrical from Seoul National University. He concentrated his study on the image sensors
Engineering, Seoul National University, Seoul, such as Vidicon type, MOS type, and also CCDs, for Samsung Display Devices
Korea, in 2000. Since 2000, he has been working Co. and Samsung Electronics Co. from 1984 to 1991. His current research inter-
toward the Ph.D. degree at the same university. ests include sub-0.1-m CMOS structure and technology, FEDs, CMOS image
His current research interests are nanoscale CMOS sensor, and high-speed SRAM design. He has published over 130 papers in the
device modeling, characterization, and fabrication. major international scientific journals, including over 65 SCI papers. He has
presented more than 180 papers, including 80 international conference papers.
He also has registered 11 U.S., three Japanese, and eight Korean patents.
Dr. Lee is a member of the Steering Committees for IVMC (International
Vacuum Microelectronics Conference) and KCS (Korean Conference on Semi-
Young-Jin Choi received the B.S. and M.S. degrees conductors). He was the Conference Chairman of IVMC’97 and KCS’98 who
from the School of Electrical Engineering, Seoul Na- led the IVMC’97 and the KCS’98. He was also a member of the IEDM (Inter-
tional University, Seoul, Korea, in 1994 and 1996, re- national Electron Devices Meeting) Subcommittee on Detectors, Sensors, and
spectively. Since 1996, he has been working toward Displays, IEEE Electron Devices Society, from 1998 to 1999. In June 1999, he
the Ph.D. degree at the same university. was elected First President of the Korean Information Display Society.
His current research interests are nanoscale CMOS
device modeling, characterization, and fabrication.

Byung-Gook Park (M’96) received the B.S. and


Jong Duk Lee (M’79) received the B.S. degree M.S. degrees in electronics engineering from Seoul
in physics from Seoul National University, Seoul, National University, Seoul, Korea, in 1982 and
Korea, in 1966 and the Ph.D. degree from the De- 1984, respectively, and the Ph.D. degree in electrical
partment of Physics, University of North Carolina, engineering from Stanford University, Stanford, CA,
Chapel Hill, in 1975. in 1990.
He was an Assistant Professor in the Department of From 1990 to 1993, he was with AT&T Bell Labo-
Electronics Engineering, Kyungpook National Uni- ratories, Murray Hill, NJ, where he contributed to the
versity, Taegu, Korea, from 1975 to 1978. In 1978, development of 0.1-m CMOS and its characteriza-
he studied microelectric technology in HP-ICL, Palo tion. From 1993 to 1994, he was with Texas Instru-
Alto, CA and soon afterwards, worked for the Korea ments, Dallas, TX, developing 0.25-m CMOS. In
Institute of Electronic Technology (KIET) as the Di- 1994, he joined the School of Electrical Engineering, Seoul National University,
rector of the Semiconductor Division. He established the KIET Kumi Facility as an Assistant Professor, and he is currently an Associate Professor. His cur-
and introduced the first polysilicon gate technology in Korea by developing 4K rent research interests are nanoscale CMOS devices, Si single-electron devices,
SRAM, 32K and 64K Mask ROMs, and one-chip 8-bit microcomputers. In July organic electroluminescent display, and scanning probe microscopy systems.
1983, he moved to the Department of Electronics Engineering, Seoul National Dr. Park was a member of the IEDM (International Electron Devices Meeting)
University, as an Associate Professor, where he has been Professor since 1988. Subcommittee on Solid State Devices, IEEE Electron Devices Society, from
He established the Interuniversity Semiconductor Research Center (ISRC) in 2001 to 2002.

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