References
the ultra-thin channel is used as a part of the source/drain region. This
1 MALLIK, R.K.,WIN, M.Z., and WINTERS, J.H.: ‘Perf0r”Ce of dual-diversity
predetection EGC in correlated Rayleigh fading with unequal branch
SNRs’, IEEE Trans. Commun., 2002, 50, (7), pp. 1041-1044
2 ANNAMALAI, A., RAMANATHAN, V, and TBLLAMBURA, C.: ‘Analysis O f
equal-gain diversity receiver in correlated fading channels’. Proc. IEEE
VTC, Birmingham, AL, USA, May 2002, pp. 2038-2041
3 ISKANDER, C.-D.,and MATHIOPOULOS, ET.: ‘Performance ofM-QAM with
coherent equal-gain combining in correlated Nakagami-m fading’,
Electron. Lett., 2003, 39, (I), pp. 141-142
4 NAKAGAMI, M.: ‘The m-distribution-general formula of intensity
distribution of rapid fading’ in HOFFMAN, W.C. (Ed.): ‘Statistical
methods in radio wave propagation’ (Pergamon, 1960)
5 GRADSHTEYN, I.s., and RYZHIK, I.M.: ‘Table of integrals, series, and
products’ (Academic Press, 2000, 6th edn.)
6 WTN, M.Z., CHRISIKOS, G., and WINTERS, J.H.: ‘MRC performance for M-ary
modulation in arbitrary correlated Nakagami fading channels’, 1EEE
Commun. Lett., 2000, 4, (IO), pp. 301-303
30 n m self-aligned FinFET with large
source/drain fan-out structure
Dong-Soo Woo, Byung Yong Choi, Woo Young Choi,
Myeong Won Lee, Jong Duk Lee and Byung-Gook Park
A 30 nm self-aligned FinFET with a large single-crystalline source/
drain structure is proposed and has been fabricated. The fabricated
FinFET shows large intrinsic transconductance of 1070 pS/pm at
0.8 V gate overdrive and good short channel behaviour in spite of
thick gate oxide of 3.6 nm.
lntroduction: As C M O S dimensions shrink down into a few tens of
nanometer regime, FinFET [l] becomes one of the most promising
device structures due to its immunity to short channel effect. At
experimental level, a FinFET with gate length of 10 nm has been
reported [2].
m
n
a b
C d
e
Fig. 1 Key process sequence of self-aligned FinFET
a Channel hardmask and oxide spacer formation
b S J D doping
c Groove formation on deposited dummy oxide layer
d SO1 etching outside fin
e Gate electrode formation
To suppress short channel effect in FinFETs, fin width should be less
than 0.7 times gate length. However, conventional FinFET structures
1154 ELECTRONICS LETTERS 24th July2003
would not have the best performance due to the structural problem that
can cause increase of parasitic resistance and degrades the drive current.
To fabricate devices with low source/drain extrinsic resistance, the
source/drain fan-out should be wide and the length of the ultra-fine
channel region which acts as a source/drain should be as short as
possible. Choi el al. [3] and Kedzierski and Wong [4] proposed devices
which have a relatively large source/drain fan-out structure using
selective Ge deposition or selective epitaxy process.
In this Letter, we propose and fabricate a novel FinFET structure with
a wide single-crystalline source/drain fan-out region. The wide
source/drain region is connected to the ultra-fine channel at the gate
edge in a self-aligned manner.
source drain
a
lo 1
21 4 I I I I
0 1 2 3 4 5
implantation dose (x1015cm-*)
b
Fig. 2 Results after key process steps
a SEM view of device after groove and SO1 etch as in Fig. Id
Groove width, about 30 nm; fin thickness, 30 nm. Considering subsequent
oxidation processes, final groove width and fin thickness will be 32 and 22 nm,
respectively
b Doping dependency of thermally grown oxide thickness
Gate-source or gate-to-drain oxide thickness is thicker than gate-to-fin oxide.
8OO0C, 10 min dry oxidation was performed on (100) surface and As+ was
implanted at energy of 30 keV
Inset: Plan view of device
Symbols represent oxide thickness measured at differentposition on same wafer
Device fabrication: The self-aligned FinFET process is shown in
Fig. 1 . The starting material was a 1 x 10” cmP3 boron-doped (1 00)-
oriented SIMOX wafer. The top silicon layer was thinned to 5 0 n m
using thermal oxidation and a subsequent oxide strip. To protect the
fin region, an Si/Si02 stacked channel hardmask was defined on top
of the active region of the device using e-beam lithography and dry
etching. A 5 0 n m TEOS oxide spacer was then formed along the
channel hardmask to provide a smooth surface for later lithography as
shown in Fig. la. Arsenic was implanted at energy of 20 keV to form
a source/drain at a dose of 1 x l O I 5 cmp2. 100 nm oxide was
deposited. Using e-beam lithography and subsequent sequential
etching of oxide and a 5 0 n m SOT layer, grooves were then
formed across the channel hardmask. The source/drain region was
separated except the fin as shown in Fig. Id. Sacrificial oxidation was
Vol. 39 No. 15
performed with the condition of 5 nm oxide growth on a (100) silicon
surface. The oxide was removed and a 3 nm gate oxide was grown. A
poly-silicon layer was deposited using LPCVD at 625°C and doped
with POC13. As the width of the groove is smaller than the thickness
of the gate polysilicon layer, the subsequent etchback of polysilicon
results in the gate electrode filled in the region of the groove in a self-
aligned manner as shown in Fig. le. Source/drain doping profiles
were diffused to the fin edge by additional heat treatment. Back-end
process including ILD deposition and aluminium metallisation was
performed without silicidation process.
Fig. 2a shows the SEM view taken after groove and SO1 etch as in
Fig. Id. The groove width was about 30 nm and the fin thickness was
30 nm. As the following sacrificial and gate oxidation processes were
performed on a (110) surface of silicon, grown oxides may be thicker
than the (100) surface. Assuming an enhancement factor of 1.2, the
estimated final fin width and groove width after gate oxidation will be
22 and 32 nm, respectively.
As the doping concentration at the region where the gate overlaps
with the source/drain region is high, different oxide thickness can be
obtained as shown in Fig. 2b. Thicker gate-to-source/drain oxide can
prevent tunnelling leakage that may occur at the gate-to-source/drain
surface and reduce the overlap capacitance.
Results: Fig. 3 shows the subthreshold characteristics of the fabri-
cated device. In this device, as p-type channel doping was
1 x 1015cmP3 and the gate was n+ polysilicon, the threshold voltage
remains negative. The drain saturation current was about 110 pA/pm
and transconductance was 300 pS/pm for a 0.8 V gate overdrive. This
relatively low performance was due to high source/drain contact
resistance the value of which was 12 kS2 measured from the Kelvin
pattern. Extracted intrinsic transconductance was 1070 pS/pm.
Considering gate oxide thickness, it shows excellent value in trans-
conductance for a 30 nm gate length FinFET. DIBL and subthreshold
swing values were 28 mV/0.9 V and 80 mV/Dec. in spite of the
estimated 3.6 nm gate oxide. This device shows good short channel
behaviour.
10-3 400
104
I 0-5 300
E,
2 10-6
0 a,
10-7
200
10-8
0 U
;. 10-9
U
10-10
Acknowledgments: This work was supported by the Ministry of
Science and Technology through the NRL (National Research Lab.)
and the Collaborative Project for Excellence in Basic System IC
Technology.
0 IEE 2003 15 May 2003
Electronics Letters Online No: 20030656
DOI: 10.1049/e1:20030656
Dong-Soo Woo, Byung Yong Choi, Woo Young Choi, Myeong Won
Lee, Jong Duk Lee and Byung-Gook Park (Znter-university Semi-
conductor Research Center (ISRC) and School of Electrical
Engineering, College of Engineering, Seoul National University,
Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea)
E-mail: bgpark@snu.ac.kr
References
1 HISAMOTO, D., LEE, W-C., KEDZIERSKI, J., TAKEUCHI, H., ASANO, K., KUO, C.,
ANDERSON, E., KING, T.-J., BOKOR, J., and HU, C.: ‘FinFET-a self-aligned
double-gate MOSFET scalable to 20 nm’, IEEE Trans. Electron Devices,
2000,47, pp. 2320-2325
2 YU, B., CHANG, L., AHMED, S., and HU, C.: ‘FinFET scaling to 10 nm gate
length’, IEDM Tech. Dig., 2002, pp. 251-254
3 CHOI, Y.-K., LINDERT, N., XUAN, P., TANG, S., HA, D., ANDERSON, E.,
KING, T.-J., BOKOR, J., and HU, C.: ‘Sub-20nm CMOS FinFET
technologies’, IEDM Tech. Dig., 2001, pp. 421424
4 KEDZIERSKI, J., and WONG, H.-S.P.: ‘High-performance symmetric-gate and
CMOS compatible V, asymmetnc-gate FinFET devices’, IEDM Tech.
Dig., 2001, pp. 437440
Influence of Si02 and Si3N4 passivation on
AIGaN/GaN/Si HEMT performance
P. Javorka, J. Bernat, A. Fox, M. Marso, H. Luth and
P. KordoS
Different influence of Si02 and Si3N4passivation on performance of
AlGaN/GaN/Si HEMTs is reported. DC characteristics are less
E enhanced by using SiOz than Si3N4.This is in agreement with camer
concentration changes after passivation, as follows from Hall data.
0E
,
Small signal RF performance is degraded after applying SiOz and
enhanced after Si3N4 passivation, e.g. for unpassivated devices
f T % 17 GHz which decreased to 9 GHz and increased to 28 GHz for
0
Si02 and Si3N4respectively. The fman/fT ratio has not changed after
3
passivation.
8
2

io-”
100
-
2 Introduction: It is well known that AlGaN/GaN HEMTs exhibit a
DC/RF dispersion as well as that a passivation can suppress this effect
and thus higher output power can be achieved [l]. Application of
10-12 0 various insulators, mainly SiOz and Si3N4, is therefore currently
-0.8 -0.4 0 0.4 0.8
studied. However, some published data are often controversial.
gate voltage VG3 V
Lower gate currents were found for SiOz than for Si3N4 passivation
Fig. 3 Measured subthreshold Characteristicsof self-aligned FinFET [2]. An increase [2] as well as a decrease [3] of gate leakage current
Fin height, 50 nm; gate oxide grown on (1 10) surface when 3 nm oxide grows on after Si3N4 passivation was reported. Conversely, about ten-times
(100)surface. Each curve measured at VDs= 0.1 and 1.O V,respectively.Threshold lower density of interface states is found for silicon nitride than for
voltage was gate voltage when drain current was 10 nA/pm at VDs= 0.1 V Si02 [4]. An enhancement [5] as well as a degradation [ l , 31 of small
Lgare= 32 nm, W”’ = 22 nm (estimated);DIBL = 28 mV/0.9 V, VTH= -0.409 V; signal RF performance of HEMTs after passivation with Si3N4 is
subthreshold swing = 80 mV/Dec. at VDs= 0.1 V, g, = 300 pS/pm at 0.8 V gate reported. This shows that many questions are still open and better
overdrive; R, = 12 kR
~ V,,=O.l v understanding of passivation effect on the device performance is
_ _ - V,,=I.OV - required. In this Letter we describe different impacts of SiOl and
Si3N4 passivation on DC and RF performance of AlGaN/GaN/
Si HEMTs.
Conclusions: We fabricated a novel self-aligned 30 nm FinFET
device the gate of which is located at the edge of the wide single
crystalline source/drain fan-out region. Considering high contact Experiment: AlGaN/GaN heterostructures were grown on 2-inch
resistance of 12 kS2, excellent intrinsic transconductance of (1 11)-oriented Si substrates by LP-MOVPE in an AIXTRON reactor.
1070 pS/pm can be obtained. The short channel effect was properly A special stress-relaxing layer sequence was grown first, followed by
suppressed with 3.6 nm gate oxide. Small drain saturation current can a GaN buffer layer [6]. Finally, a 25 nm-thick intentionally undoped
be improved by optimisation of contact resistance and reducing gate (i.e. polarisation doped) AlGaN barrier layer was grown on top of
oxide thickness. This device can be used for low-power application. GaN. The mole fraction of A1N was xAINS 0.28, as determined by
Due to the pre-source/drain process sequence, it is also compatible RBS. The growth procedure used allows the production of crack-free
with the metal gate FinFET process. structures with reduced tensile strain and good surface roughness.

ELECTRONICS LETTERS 24th July2003 Vol. 39 No. 15 1155