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nnovative device architectures will be necessary to continue thereby demonstrating its compatibility with today’s planar
OVERCOMING OBSTACLES
BY DOUBLING UP
CMOS technology scaling has traversed many anticipated barri-
may be deferred if a DGCMOS architecture is employed. Previ- ers over the past 20 years to rapidly progress from 2 µm to 90
ously, serious structural challenges have made adoption of nm rules, as discussed in the article by Chuang et al. also found
DGCMOS untenable. Recently, through use of the delta device in this issue of the magazine [24]. Currently, two obstacles,
[1], now commonly referred to as the FinFET [2], significant namely subthreshold and gate-dielectric leakages, have become
advances in DGCMOS device technology and performance have the dominant barrier for further CMOS scaling, even for highly
been demonstrated. Fabrication of FinFET-DGCMOS is very leakage-tolerant applications such as microprocessors.
close to that of conventional CMOS process, with only minor Double-gate (DG) FETs, in which a second gate is added
disruptions, offering the potential for a rapid deployment to opposite the traditional (first) gate, have long been recognized
manufacturing. Planar product designs have been converted to [3], [4] for their potential to better control short-channel
FinFET-DGCMOS without disruption to the physical area, effects (SCEs). Such short-channel effects limit the minimum
■ 20 8755-3996/04/$20.00 ©2004 IEEE IEEE CIRCUITS & DEVICES MAGAZINE ■ JANUARY/FEBRUARY 2004
channel length at which an FET is electrically well behaved.
Figure 1 schematically illustrates the advantage of DG-FETs.
Channel GATE Channel GATE
As the channel length of an FET is reduced, the drain poten-
tial begins to strongly influence the channel potential, leading
to an inability to shut off the channel current with the gate.
This short-channel effect is mitigated by use of thin gate oxide XD
(to increase the influence of the gate on the channel) and thin
depletion depth below the channel to the substrate, to shield BODY (Neutral)
GATE
the channel from the drain. Gate oxide thickness has been
Single-Gate FET Double-Gate FET
reduced to the point where, at 90 nm CMOS, the power drain
from gate leakage is comparable to the power used for switch-
1. The double-gate device architecture escapes the intrinsic
ing of circuits. Thus, further reduction of the thickness would compromise presented by conventional FETs [5].
lead to unreasonable power increases.
Alternatively, further decrease of the depletion region XD
degrades gate influence on the channel and leads to a slower
turn on of the channel region.
In DG-FETs, the longitudinal electric field generated by the 400 120
DIBL (mV/V)
reduced short-channel effects, in particular, reduced drain- 80
250
induced-barrier lowering (DIBL) and improved subthreshold
swing (S). Therefore, as CMOS scaling becomes limited by leak- 200 60
age currents, DGCMOS offers the opportunity to proceed 150 Single-Gate/Bulk
40
beyond the performance of single-gate (SG) bulk-silicon or PD- Double-Gate
100
SOI CMOS. Figure 2 shows MEDICI-predicted DIBL and sub- 20
50
threshold swing for bulk silicon and (symmetrical) DG devices
0 0
as functions of effective channel length Leff. Both the DIBL and
15 25 35 45 55
subthreshold swing for the DG device are dramatically
improved relative to those of the bulk-silicon counterpart. LEFF (nm)
From a bulk-silicon device design perspective, increased body
2. MEDICI-predicted DIBL and subthreshold swing versus effective
doping concentration could be employed to reduce DIBL; how- channel length for DG and bulk-silicon nFETs. The DG device is
ever, at some point it would also increase the subthreshold designed with an undoped body and a near-mid-gap gate material.
swing, thereby requiring higher threshold voltage VT to keep
the subthreshold current adequately low. Similarly, decreasing
the body doping concentration could improve the subthreshold
swing but degrade DIBL. Hence a compromise is necessary for
the bulk-silicon device design. Note that, for a scaled bulk-sili- 10–2
G
con (or PD-SOI) device, a highly doped channel/halo must be 10–3 S D
used to control severe SCEs, and lower S for extremely short G
10–4 G
Leff could not be achieved by use of low channel/halo doping.
S D
In Figure 3 simulations of the IDS–VGS characteristics of 10–5
DG and SG FETs shows the steeper turn on of the DG-FET,
|DS (A/∝m)
10–6
which results from the gate coupling advantage previously
discussed in Figure 1. This property enables the use of lower 10–7
threshold voltage for the DG-FET for a given off-current. As a DG
10–8
direct result, higher drive currents at lower power-supply Bulk Si
voltages VDD are attainable. 10–9
10–10
DOUBLE-GATE THRESHOLD VOLTAGE –0.2 0.0 0.2 0.4 0.6 0.8 1.0
The very thin silicon body associated with fully depleted DG- VGS(V)
FETs suggests that the centering of VT could be a challenging
proposition. Three basic techniques have been explored both 3. Simulation of double-gate and single-gate FETs designed for equal
theoretically and experimentally, namely, use of body doping, subthreshold current density at VGS = 0 V illustrates the gain in drive
use of asymmetric gate work function, and use of symmetric current from improved channel control of the double-gate FET. Both
gates contribute to control of the channel potential in subthreshold,
mid-gap work-function gate-electrodes. Each technique will while in the bulk case the gate must compete with the influence of the
be visited briefly. substrate.
1E–4
1E+2
pFET nFET Vd = 1.5V
1E+1 1E–5 nFET
1E+0
|Id|(A/∝m) 1E–6 pFET
1E–1
Vd = 0.05V
1E–2 1E–7
ID(λA)
1E–3
1E–8
1E–4 Tsi = 40nm
1E–5 1E–9
1E–6
1E–10
1E–7 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5
–1.5 –1.0 –0.5 0.0 0.5 1.0 1.5
Simulated
VGATE(V) Vg(V) Gate Doping
4. Drain current versus gate voltage for both n-type and p-type DG- 5. Id − Vg characteristics of Asymmetric-double-gate nFET
FETs integrated on a single die, using halo doping to center VTs [6]. and pFET [7].
Tox = 1.6 nm
Si
Fin
Tsi = 25 nm
Si
BOX
7. Electron density versus distance from body center for
6. TEM cross section of metal-gate DG-FinFET using nickel-silicide as symmetric-metal-gate and asymmetric-poly-gate FETs. TSi = 5 nm for
the gate electrode (reprinted from [8]). this simulation.
Deposit/Etch Spacer
Oxide Isolation Planarization Ion-Implant Sources/Drains, Gates
11. FinFET process flow (I) (reprinted with permission from [5]). 12. FinFET process flow (II) (reprinted with permission from [5]).
Vdata-True (V)
1.0
sitic series resistances associated with the bot- V-Bi-True
tom junction low. Furthermore, a space-efficient Write "0"
low-capacitance contact scheme to the lower
junction requires a high-wire act in process 0.5
integration. While high drive currents have been
achieved with Type II structures, high perfor- Write "1"
mance (e.g., low capacitance) and CMOS inte- 0.0
0.0 0.5 1.0 1.5
gration have met with limited progress.
V-BL-True (V)
Type III vertical fin-type DG-FETs have the
advantages of access to both gates, and both Cu-M1
sides of source and drain, from the front of the
wafer. Gate length is conventionally defined
since the direction of the current is in the wafer
plane. Gate width, however, is no longer con- Pull-Down
W-Via
nFETs
W-Via
trolled by lithography; rather, the width is given
by twice the height of the silicon fin HFin (Fig-
ure 10). This aspect will be discussed in more
detail later.
16. Waveform of the buffer output from the ring oscillator shown in 17. Potential for double-gate applications [21]. (a) Low-power design.
Figures 11 and 12 (reprinted with permission from [5]). (b) Variable threshold CMOS. (c) Simplified logic gates [16].
Planar Process
Poly Gate
Active Area
WP
Planar P/N=1.5
FinFET Process
Poly Gate
FinFET Devices
FinFET P/N=9/6=1.5
Pitch
20. NAND2 gate conversion for processing with sidewall image
19. Device width quantization [19]. transfer (SIT) technique.
scanc1
so
for processing in the 90 nm FinFET technology
so
c2_b
node. The FinFET height HFin together with the
|2 fin pitch (determined by photolithography) defines
scanc1
fb_si fb
given silicon width of the planar device (WP). To
c1_und_b
c1_und_b c2_b
get the same or better device strength, (1) in Fig-
ure 19 must be followed [19]. As an example, a
scanc1_b
CONCLUSION
Double-gate devices will enable the continuation of CMOS
scaling after conventional scaling has stalled. DGCMOS/Fin-
FET technology offers a tactical solution to the gate dielectric
RDS(Pg)
Beta Ratio = PL PR barrier and a strategic path for silicon scaling to the point
RDS(Cc)
where only atomic fluctuations halt further progress. The
(Bitline_Left) (Bitline_Right) conventional nature of the processes required to fabricate
Pg L these structures has enabled rapid experimental progress in
BL R BR
just a few years. Fully integrated CMOS circuits have been
Cc demonstrated in a 180 nm foundry-compatible process, and
methods for mapping conventional, planar CMOS product
designs to FinFET have been developed. For both low-power
WL and high-performance applications, DGCMOS-FinFET offers a
most promising direction for continued progress in VLSI.
Wordline
WL
SL
SR
22. 6T-SRAM cell converted to FinFETs (layer convention, see Figure 20). 23. Compact model simulation for FinFET 6T-SRAM cell.
[5] E. Nowak, T. Ludwig, I. Aller, J. Kedzierski, 24. Design flow for design with FinFETs [21]. Areas with orange background
M. Ieong, B. Rainey, M. Breitwisch, V. Gern- require new developments or extensions to existing tools.
hoefer, J. Keinert, D.M. Fried, “Scaling
beyond the 65 nm node with FinFET-
DGCMOS,” in Proc. IEEE CICC, San Jose, CA, pp. 339–342. [14] E. Nowak, B. Rainey, D.M. Fried, J. Kedzierski, M. Ieong, W. Leipold,
J. Wright, and M. Breitwisch, “A functional FinFET-DGCMOS SRAM
[6] B. Rainey, D.M. Fried, M. Ieong, J. Kedzierski, and E.J. Nowak, cell,” in Tech. Digest IEDM 2002, San Francisco, CA, pp. 411–414.
“Demonstration of FinFET CMOS circuits,” in Proc. 2002 Device
Research Conf., Santa Barbara, CA, pp. 47–48. [15] S.H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Sub-
ramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET - A quasi-planar double-
[7] J. Kedzierski, D.M. Fried, E.J. Nowak, T. Kanarsky, J.H. Rankin, H. gate MOSFET,” in Proc. ISSCC 2001, San Francisco, CA, pp. 118–119.
Hanafi, W. Natzle, D. Boyd, Y. Zhang, R.A. Roy, J. Newbury, C. Yu, Q.
Yang, P. Saunders, C.P. Willets, A.R. Johnson, S.P. Cole, H.E. Young, N. [16] K.W. Guarini, P.M. Solomon, Y. Zhang, K.K. Chan, E.C. Jones, G.M.
Carpenter, D. Rakowski, B. Rainey, P.E. Cottrell, M. Ieong, and H.-S.P. Cohen, A. Krasnoporova, M. Ronay, O. Dokumaci, J.J. Buchignano, C.
Wong, “High-performance symmetric-gate and CMOS-compatible asym- Cabral Jr., C. Lavoie, V. Ku, D.C. Boyd, K.S. Petrarca, I.V. Babich, J. Tre-
metric-gate FinFET device,” in Tech. Digest IEDM 2001, Washington, ichler, P.M. Kozlowski, J.S. Newbury, C.P. D'Emic, R.M. Sicina, and H.-
DC, pp. 437–440. S.P. Wong, “Triple-self-aligned, planar double-gate MOSFETs: Devices and
circuits,” in Tech. Digest IEDM 2001, Washington, DC, pp. 425–428.
[8] J. Kedzierski, E.J. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers,
C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, [17] W.R. Hunter, T.C. Holloway, P.K. Chatterjee, and A.F. Tasch Jr., “A
P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. Rainey, new edge-defined approach for submicrometer MOSFET fabrication,”
D.M. Fried, P.E. Cottrell, H.-S.P. Wong, M. Ieong, and W. Haensch, “Metal IEEE Elec. Dev. Let., vol. EDL-2, no. 1, pp. 4–6, Jan. 1981.
gate FinFET and fully depleted SOI devices using total gate silicidation,”
in Tech. Digest IEDM 2002, San Francisco, CA, pp. 247–250. [18] Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for
nanoscale CMOS," IEEE Trans. Elec. Dev., vol. 49, no. 3, pp. 436-441,
[9] Y.K. Choi, L. Chang, P. Renade, J.-S. Lee, D. Ha, S. Balasubramanian,
Mar. 2002.
A. Argawal, M. Ameen, T.-J. King, and J. Bokor, “FinFET process refine-
ments for improved mobility and gate workfunction engineering,” in [19] T. Ludwig, I. Aller, V. Gernhoefer, J. Keinert, A. Mueller, E. Nowak,
Tech. Digest IEDM 2002, San Francisco, CA, pp. 259–262. R.V. Joshi, and S. Tomaschko, “FinFET Technology for future micropro-
cessors,” IEEE SOI Conference, Sept. 29 – Oct. 2, 2003, Newport Beach,
[10] H.-S. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann, J.J. Welser,
CA, pp. 33–34.
“Nanoscale CMOS,” Proc. IEEE, vol. 87, no. 4, p. 537, Apr. 1999.
[11] J.-H. Lee, G. Taraschi, A. Wei, T.A. Langdo, E.A. Fitzgerald, and D.A. [20] V. Gernhöfer, “FinGEN, a tool for automated FinFET level genera-
Antoniadis, “Super self-aligned double-gate (SSDG) MOSFETs utilizing tion,” unpublished.
oxidation rate difference and selective epitaxy,” in Tech. Digest IEDM [21] I. Aller, “The double-gate FinFET: Device impact on circuit design,”
2001, Washington, DC, pp. 71–74. in Proc. ISSCC 2003, San Fransisco, CA, pp. 14–15 (and visual supple-
[12] J.M. Hergenrother, D. Monroe, F.P. Clemens, A. Kornblit, G.A. Weber, ments pp. 655-657).
W.M. Mansfield, M.R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A.
[22] R.V. Joshi, A. Pellela, O. Wagner, Y.H. Chan, W. Dachtera, S. Wilson,
Ciampa, R.I. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frackoviak, H.J.
and S.P. Kowalczyk, “High performance SRAMs in 1.5 V, 0.18 µm par-
Grossman, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleiman, W.Y-C.
tially depleted SOI technology,” in Dig. Tech. Papers, Symp. VLSI Cir-
Lai, J.T-C. Lee, R.C. Liu, H.L. Maynard, M.D. Morris, S.-H. Oh, C.S. Pai,
cuits 2002, Honolulu, HI, pp. 74–77.
C.S. Rafferty, J.M Rosamilia, T.W. Sorsch, and H-H. Vuong, “The vertical
replacement-gate (VRG) MOSFET: A 50 nm vertical MOSFET with [23] R. Williams and E. Nowak, “FinFET PowerSPICE compact model,”
lithography-independent gate length,” in Tech. Digest IEDM 1999, unpublished.
Washington, DC, pp. 75–78.
[24] C.T. Chuang, K. Bernstein, R.V. Joshi, R. Puri, K. Kim,
[13] D. Fried, A.P. Johnson, E.J. Nowak, J.H. Rankin, and C.R. Willets, “A E.J. Nowak, T. Ludwig, and I. Aller, “Scaling planar silicon devices,”
sub-40 nm body-thickness n-type FinFET,” in Conf. Digest 59th Device IEEE Circuits Devices Mag., vol. 20, no. 1, pp. 6–19, Jan./Feb. 2004.
Research Conf., Notre Dame, IN, June 2001, pp. 24–25.