IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO.
5, MAY 2005
An Air Spacer Technology for Improving
Short-Channel Immunity of MOSFETs With Raised
Source/Drain and High- Gate Dielectric
Chunshan Yin, Student Member, IEEE, Philip C. H. Chan, Senior Member, IEEE, and
Mansun Chan, Senior Member, IEEE
Abstract—An air-spacer technology with raised source/drain
(S/D) for ultrathin-body (UTB) silicon-on-insultor MOSFETs is
developed. The results show that the poly raised S/D can effec-
tively reduce the series resistance and the air spacer can effectively
reduce the fringing capacitance. The air spacer is particularly
useful when combined with high- gate dielectric. The improved
device characteristics are demonstrated experimentally and by
extensive two-dimensional device simulation.
Index Terms—Air spacer, gate insulator, high- dielectric,
raised source/drain (S/D), silicon-on-insulator (SOI), ultrathin-
body (UTB).
I. INTRODUCTION
U LTRAHIN-BODY (UTB) silicon-on-insulator (SOI)
MOSFETs are a promising candidate for further scaled
MOSFETs [1]–[3]. However, several issues must be addressed
in order to achieve high-performance UTB devices. Two of the
most important issues are high series resistance and leaky gate
oxides [2], [3]. Raised source/drain (S/D) with a reduced offset
spacer width can reduce the external resistance. However, out
fringing capacitance increases with closer proximity of the
raised S/D to the gate edge. High- gate dielectric can reduce
the gate leakage current while maintaining a low equivalent
oxide thickness (EOT). However, the use of high- is dif-
ferent from reducing dielectric thickness due to the proximity
effect and fringing E-field [4]. In fact, a number of parasitic
capacitors shown in Fig. 1 are playing an important role in
determining the effectiveness of the high- material to suppress
the short-channel effect (SCE). The effect of fringing capaci-
tance is more prominent when raised S/D is used. Low- spacer
must be used to reduce the fringing field effect and suppress
SCE [5], [6].
In this letter, an air spacer [7] technology with poly raised S/D
for UTB SOI MOSFETs is demonstrated. The poly raised S/D
was adopted to reduce the series resistance, and the air spacer
was used to reduce the fringing E-field. The influence of raised
S/D and air spacer on current drive and SCE are studied in detail
by two-dimensional (2-D) device simulator Medici [8], and the
results are discussed in this letter.
Manuscript received January 4, 2005; revised February 3, 2005. The review
of this letter was arranged by Editor A. Chatterjee.
The authors are with the Department of Electrical and Electronic Engi-
neering, Hong Kong University of Science and Technology, Kowloon, Hong
Kong (e-mail: yincs@ust.hk).
Digital Object Identifier 10.1109/LED.2005.846584
0741-3106/$20.00 © 2005 IEEE
323
II. DEVICE FABRICATION AND CHARACTERIZATION
The process flow to form an air spacer is summarized in
Fig. 2. The gate electrode consists of 10-nm gate oxide and 200-
and 100-nm cap oxide. After gate-electrode patterning, source
drain extension (SDE) was implanted [Fig. 2(a)]. Then 20-nm
oxide and 80-nm nitride were deposited, and a dummy nitride
spacer was constructed [Fig. 2(b)]. After that, the dummy nitride
spacer was totally removed by wet etch. Then 80-nm poly was
deposited and S/D was implanted [Fig. 2(c)]. After that, 300-nm
oxide was deposited and polished using chemical–mechanical
polish (CMP) to expose the underneath poly [Fig. 2(d)]. The
poly was then etched down to the bottom of the buffer oxide
with enough over etch [Fig. 2(e)]. Air gap was formed beside the
gate electrode [Fig. 2(f)] after another oxide deposition with op-
timized deposition conditions. The raised S/D and air gap can be
clearly observed from the scanning electron microscope (SEM)
picture of the fabricated device [Fig. 2(g)]. No silicide was pro-
cessed in this run. Conventional UTB MOSFETs with a channel
thickness of 30 nm and a partially depleted SOI (PDSOI) with a
channel thickness of 130 nm were fabricated following a stan-
dard CMOS SOI process flow for comparison.
Fig. 3 shows the – and – characteristics of the UTB
MOSFETs with raised S/D and air spacer compared with that
from a regular UTB MOSFET. The poly raised S/D devices
produce higher drive current [Fig. 3(a)] due to reduced S/D se-
ries resistance. Comparing raised S/D UTB MOSFETs with and
without an air spacer, the air spacer significantly reduced the
fringing parasitic capacitance [Fig. 3(b)].
III. EFFECTS OF THE AIR SPACER
For a MOSFET with raised S/D, two different fringing
capacitors through a gate dielectric and spacer can be dis-
tinguished: S/D to gate capacitor ( ) and S/D to channel
capacitor ( ), as shown in Fig. 1. is the main component
that degrades SCE. We perform a device simulation based on
the ITRS 2003 Roadmap [1] in the extremely scaling regime
with a metallurgical channel length ( ) of 20 nm. According
to the roadmap, other major parameters are EOT nm,
nm, and nm. Considering the silicide
process, a raised S/D of 12 nm was selected in the simulation.
Without loss of generality, a reference value of is
used for the gate dielectric, which is close to the most promising
Hf-based dielectric [9].
324 IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 5, MAY 2005

Fig. 1. Schematic of two different capacitors through gate dielectric and spacer: drain-to-gate capacitor (C ) and drain-to-channel capacitor (C ). Only half of
the device (drain side) is shown here. C includes gate overlap capacitance (C and out fringing capacitance (C +C +C ). C = C 1 + C 2 +
C 3.

Fig. 3. (a) Measured nMOS I –V characteristics (L = 0:35 m).

Fig. 2. Process flow of raised S/D with air spacer. (a) Gate patterning and SDE
implantation. (b) Dummy nitride spacer formation. (c) Nitride wet etching, poly
deposition, and S/D implantation. (d) Oxide deposition and polish. (e) Poly etch
back. (f) Air-gap formation. (g) SEM picture of the fabricated device. Major
device parameters are T = 360 nm, T = 30 nm, T = 10 nm, T = to the channel through the spacer and gate dielectric, thus re-
80 nm, and L = 100 nm.
Fig. 4 shows the drain-induced barrier-lowering (DIBL) and
the delay of ring oscillators as a function of spacer values. For
devices with high- gate dielectric, increasing overlap length
( ) will increase both gate control over channel and drain
coupling to channel through gate dielectric. According to the
simulation results, nm is the optimized value for de-
vices with high- gate dielectric and air spacer. Re-
The two devices have same channel thickness (T = 30 nm). (b)
Measured gate-to-channel capacitance (C ) for various MOSFETs with
W=L = 50 m=1 m. The capacitances were measured at V = V = 0 V
with frequency = 1 MHz. The poly raised UST SOI used an air spacer, and
the others used an oxide spacer. No raised S/D was used for the PDSOI.
ducing the spacer -value can effectively reduce drain coupling
ducing DIBL. For devices with oxide as the gate dielectric, drain
coupling to the channel through the gate oxide can be ignored.
A high- spacer produces a higher outfringing E-field and pro-
vides better gate control over the junction-depletion region near
the drain side. As a result, increasing spacer -value decreases
DIBL.
Parasitic capacitance can always be reduced by decreasing
the spacer -value, and, by doing so, the delay of the ring os-
cillator is significantly reduced. To achieve the same EOT, a
YIN et al.: AIR-SPACER TECHNOLOGY FOR IMPROVING SHORT-CHANNEL IMMUNITY OF MOSFETS 325

pacitance was effectively reduced, which is very useful for de-

vices with high- gate dielectric. Simulation results indicated
that the air spacer was effective for suppressing SCE of devices
with high- gate dielectric. Compared to those with an oxide
spacer, the speed of devices with high- gate di-
electric can be improved as much as 23% by using an air spacer.

Fig. 4. Simulated DIBL of nMOS and delay of a ring oscillator. The schematic
of the simulated structure was same as that shown in Fig. 1. The devices have
L = 20 nm, L = 2 nm, L = 5 nm, EOT = 1:3 nm and raised S/D
(T = 12 nm). Solid symbols are for devices with high- gate dielectrics, and
open symbols are for devices with oxide gate dielectrics.
higher -value requires larger geometrical sep-
aration between the gate and the channel so that smaller is
achieved when same spacer material is used. As a result, devices
with high- gate dielectric have smaller delay than that of de-
vices with oxide gate dielectric. With an air spacer, the speed of
devices with high- gate dielectric can be im-
proved as much as 23% compared to that using an oxide spacer.
IV. CONCLUSION
UTB SOI MOSFETs with an air spacer and raised S/D were
successfully fabricated. The results suggested that fringing ca-
REFERENCES
[1] PIDS and FEP of ITRS 2003. [Online]. Available: http://public.itrs.net
[2] B. Doris, M. Ieong, H. Zhu, Y. Zhang, M. Steen, W. Natzle, S. Callegari,
V. Narayanan, J. Cai, S. H. Ku, P. Jamison, Y. Li, Z. Ren, V. Ku, D. Boyd,
T. Kanarsky, C. D’Emic, M. Newport, D. Dobuzinsky, S. Deshpande, J.
Petrus, R. Jammy, and W. Haensch, “Device design considerations for
ultrathin SOI MOSFETs,” in IEDM Tech. Dig., 2003, pp. 631–634.
[3] A. Vandooren, A. Barr, L. Mathew, T. R. White, S. Egley, D. Pham,
M. Zavala, S. Samavedam, J. Schaeffer, J. Conner, B.-Y. Nguyen, B. E.
White Jr., M. K. Orlowski, and J. Mogab, “Fully-depleted SOI devices
with TaSiN gate, HfO2 gate dielectric, and elevated source/drain exten-
sions,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 342–344, May
2003.
[4] B. Cheng, M. Cao, P. V. Voorde, W. Greene, H. Stork, Z. Yu, and J. C.
S. Woo, “Design consideration of high- gate dielectrics for sub-0.1-um
MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 261–262,
Jan. 1999.
[5] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The
effect of high- gate dielectrics on deep submicronmeter CMOS device
and circuit performance,” IEEE Trans. Electron Devices, vol. 49, no. 5,
pp. 826–831, May 2002.
[6] D. L. Kencke, W. Chen, H. Wang, S. Mudanai, Q. Ouyang, A. Tasch, and
S. K. Banerjee, “Source-side barrier effects with very high- dielectrics
in 50 nm Si MOSFETs,” in Device Res. Conf. Dig., 1999, pp. 22–23.
[7] M. Togo, A. Tanabe, A. Furukawa, K. Tokunaga, and T. Hashimoto, “A
Gate-side Air-gap Structure (GAS) to reduce the parasitic capacitance
in MOSFETs,” in Symp. VLSI Tech. Dig., 1996, pp. 38–39.
[8] MEDICI User’s Manual, vol. 4, Avant!, Fremont, CA, 2001.
[9] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-K gate dielectrics:
current status and materials properties considerations,” J. Appl. Phys.,
vol. 89, no. 10, pp. 5243–5275, May 2001.