IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO.

4, APRIL 2004 199

High-Performance P-Type
Independent-Gate FinFETs
David M. Fried, Student Member, IEEE, Jon S. Duster, Member, IEEE, and Kevin T. Kornegay, Senior Member, IEEE

Abstract—We present, to our knowledge, the first successful

integration of two independent gates on a p-type FinFET. These
results also represent a significant performance improvement
over previously reported Independent-Gate FinFET results. The
devices have gate lengths ranging from 0.5 to 5 m, and designed
fin thicknesses ranging from 25 to 75 nm. Electrical results show
near-ideal subthreshold slopes in double-gate mode (both gates
modulated simultaneously). Independent-Gate operation is also
examined by modulating saturated drain current with both front
and back-gate voltages independently. The results are compiled to
analyze performance trends versus fin thickness and gate length. Fig. 1. Planned structure of the IG-FinFET.
Index Terms—Double gate (DG), FinFET, independent gate
(IG), MOSFET, threshold tuning, threshold voltage.

I. INTRODUCTION

T HE PURPOSE of Independent-Gate FinFET (IG-FinFET)

development is to produce a fully depleted double-gate
MOSFET that leverages the fabrication advantages and integra-
tion capabilities of FinFET technology [1]–[7] with the unique
behavioral characteristics of “back-gate” or “ground-plane”
devices [8]–[10]. Utilizing mostly top-down fabrication pro-
cesses, as used in conventional CMOS processing and nominal
FinFET fabrication, IG-FinFETs are inherently more amenable
to CMOS manufacturing environments. With relatively few
process modifications, IG-FinFET technology could be inte-
grated with nominal FinFET technology, offering both novel
four-terminal devices and high-performance logic devices. This
work represents a significant step forward in the development
of IG-FinFET technology with significant performance and
yield improvements and includes detailed characterization.
II. DEVICE FABRICATION
The fabrication details of this work largely follow previously
reported processing [11], [12]. Starting silicon-on-insulator
(SOI) wafers contained a 400-nm buried oxide layer and a
340-nm device layer. A 250-nm thermal SiO film was grown
as a mask for the silicon fin etch, thinning the SOI layer to
Manuscript received December 4, 2003. This work was performed in part
at the Cornell Nano-Scale Science and Technology Facility (a member of the
National Nanofabrication Users Network), supported by the National Science
Foundation under Grant ECS-9731293, its users, Cornell University, and Indus-
trial Affiliates. This work made use of the Cornell Center for Materials Research
Shared Experimental Facilities, which was supported through the National Sci-
ence Foundation Materials Research Science and Engineering Centers program
under Grant DMR-0079992. The LEO 1550 SEM was originally supported by
the Keck Foundation, with additional support from the Cornell Nanobiotech-
nology Center STC Program under NSF award ECS-9876771. The review of
this letter was arranged by Editor B. Yu.
The authors are with the School of Electrical Engineering, Cornell University,
Ithaca, NY 14853 USA.
Digital Object Identifier 10.1109/LED.2004.825160
0741-3106/04$20.00 © 2004 IEEE
Fig. 2. Top-down SEM of device active area of a 0.35 m gate length on a
designed 75-nm-thick fin. The fin runs from top to bottom, and the gates are
shown on the left and right.
roughly 230 nm. Fins of thicknesses ranging from 10 to 100 nm
were written using electron-beam lithography. The hard-mask
and the SOI layers were etched down to the buried oxide layer
to produce the bodies of the FinFETs. A sacrificial SiO was
grown and removed to repair the reactive ion etching dam-
aged sidewalls. Phosphorus was implanted at a 5e11 dose and
30-keV energy at a 45 tilt and continuous rotation to produce
lightly n-type doped fin bodies. This implant was followed by
a 30-s rapid thermal annealing (RTA) at 1050 C. An identical
thermal SiO was grown for the gate dielectric. These SiO
films measured 55 A on bulk silicon monitor wafers. 600-nm
of undoped polysilicon was deposited, implanted with Boron,
and annealed and polished/planarized to the height of the oxide
hard-mask using chemical mechanical polishing (CMP). The
polysilicon was recessed 25 nm to ensure isolation across the top
of the fin. A 400-nm low-pressure checmial vapor deposition
(LPCVD) Si N layer was deposited as a gate electrode mask,
and patterned using 248-nm DUV lithography. The Si N
mask and polysilicon were etched down to the buried oxide to
define the gate electrodes. The remaining oxide hard-mask was
stripped in hydrofluoric acid (HF). At this point in the process,
the independent double gate structure has been formed as shown
in Fig. 1. A sidewall reoxidation was performed to eliminate
gate shorts and to cap the silicon for source/drain implantation.
200 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 4, APRIL 2004

TABLE I
SUMMARY OF EXTRACTED DEVICE PARAMETERS IN DOUBLE-GATE MODE (DG, BOTH GATES MODULATED SIMULTANEOUSLY) AND
INDEPENDENT-GATE MODE (IG, ONE GATE HELD CONSTANT WHILE OTHER GATE MODULATED)

Fig. 3. Cross section SEM showing fin capped by oxide hard mask and
surrounded by Polysilicon gates.

The wafer was implanted with BF at a 5e15 dose and 25-keV

energy with 12 tilt with continuous rotation followed by a 5 s
950 C RTA to form source/drain regions. A simple one-level
Aluminum metallization was performed to ease probing of
the devices. A final surface-state anneal was performed before
electrical testing. The major changes from previously reported
fabrication were the use of implanted Polysilicon gate elec-
trodes, a new wafer-scale CMP balancing scheme and the change
from plasma-enhanced chemical vapor deposition (PECVD)
to LPCVD Nitride for the gate electrode mask, in addition to
p-type source/drain implants. The top-down scanning electron
microscope (SEM) image seen in Fig. 2 shows the continuity of
planar Si N over the fin, protecting the channel region from the
source/drain implants. The cross-sectional SEM seen in Fig. 3
shows the successful separation of the two polysilicon gate
electrodes by CMP and the remaining oxide hardmask isolating
the two gates.
Fig. 4. Measured drain current versus front-gate voltage for various back-gate
voltages, between 2.0 to 0.0 V.
III. DEVICE RESULTS
Due to its lightly doped, fully depleted, double-gate nature,
the threshold voltage of a p-type polysilicon-gated FinFET will
be positive without gate work function engineering [5]. As such,
the testing conditions for this work have been adjusted to show
the full range of operation. Linear and saturated device curves
were taken with 50 mV and 2.5 V, respectively, from drain to
source. An example of versus and data in Indepen-
dent-Gate (IG) mode is shown in Fig. 4. Several devices were
tested, and the data has been compiled to show trends based on
gate length and fin thickness. Table I shows the number of func-
tional devices that are included in the statistical analysis, in ad-
FRIED et al.: HIGH-PERFORMANCE P-TYPE INDEPENDENT-GATE FinFETs
dition to several parameters extracted from the test data. The
DG mode trends show several advantages of thinner fins. Lines
2 and 3 show a severe increase in off-current of short-channel
devices as a function of fin thickness. This increase is tightly
coupled to the threshold voltage rolloff, as seen on Line 7, re-
sulting in the increase in drain-induced barrier lowering (DIBL)
for these devices, as shown on Line 8. A major advantage of
thinner fins can be seen on Line 9, with the dramatic increase
in subthreshold slope for the short-channel devices with thicker
fins. One disadvantage of thinner fins, as illustrated by Line 5,
is the decrease of for the thinner fins. This is due to the
increased source/drain resistance presented by the small cross
section of a thinner fin. Process improvements such as silicide
or raised source/drain technologies could reduce this effect.
Operating the IG-FinFET in IG mode by modulating the
two gate biases independently shows the effect of one gate on
the threshold voltage of the other gate. Line 12 shows that the
change in as the back-gate voltage is adjusted from 2.0
to 1.5 V is enhanced on the thinner fins. This trend is intuitive,
as the devices with thinner fins have a tighter coupling between
the two gates [15]. Line 13 shows the effect of “back-gate” bias
on . Here, the effect of DIBL on the thicker fin devices is
much greater than the effect of the back-gate bias. Therefore,
the thicker fin devices exhibit a substantially larger than
the thinner fin devices. However, in relation to the DG (as
shown on Line 7), the IG can be lowered significantly. This
effect comes at the expense of on-current, as only one side of
the fin is operated in inversion mode, effectively halving the
device width.
IV. CONCLUSION
This work provides more evidence of the advantages of the
IG-FinFET for independent double-date applications. The data
201
collected as part of this work shows statistical proof of sev-
eral elements of double-gate and back-gate physics. Process im-
provements are necessary for high-performance applications.
Future research includes additional process enhancements and
CMOS integration.
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