IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO.
12, DECEMBER 2008
Three-Dimensional Closed-Form Model for Potential
Barrier in Undoped FinFETs Resulting in Analytical
Equations for VT and Subthreshold Slope
Alexander Kloes, Member, IEEE, Michaela Weidemann, Member, IEEE, Daniel Goebel, and Bryan T. Bosworth
Abstract—An analytical approach for modeling the electrostatic
potential in nanoscale undoped FinFETs is derived. This method
uses a 2-D solution for this potential within a double-gate FET and
takes into account the top gate electrode as the third dimension
by applying the conformal mapping technique. Herewith, an an-
alytical closed-form model for the height of the potential barrier
below threshold is defined which includes 3-D effects. From that,
models for subthreshold slope and threshold voltage of nanoscale
triple-gate FETs are derived. The results are in good agreement
with numerical device simulation results and measurements for
channel lengths down to 20 nm.
Index Terms—Conformal mapping, FinFET, modeling,
MOSFET, potential, threshold voltage, trigate.
I. INTRODUCTION
T HE ONGOING miniaturization of microelectronic de-
vices requires a continuous improvement of compact
models used for circuit simulations. Today, research on sub-
50-nm technologies focuses on advanced devices with SOI-type
structures. These multiple-gate devices such as FinFETs [1], [2]
are strongly influenced by 3-D effects [Fig. 1(a)]. A complete
compact model for FinFETs, based on 3-D approximation,
is currently missing. However, one is urgently needed, since
FinFETs are among the most promising nanoscale devices [3].
Electrical device parameters such as leakage current below
threshold and threshold voltage are controlled by the height
of the potential barrier which the carriers have to surmount to
enter the drift region of the channel. This barrier is located at
the minimum of the electrostatic potential along the direction
from the source to the drain. Furthermore, the most leaky path
in the channel cross section will be at the position with the
highest electron concentration and, hence, where the maximum
potential is located.
The potential barrier is defined by a 3-D potential problem.
There has already been a published work on analytically solving
Manuscript received July 23, 2008. Current version published November 26,
2008. This work was supported by the German Federal Ministry of Education
and Research under Contract 1764X06. The review of this paper was arranged
by Editor C. McAndrew.
A. Kloes and M. Weidemann are with the University of Applied Sci-
ences Giessen–Friedberg, 35390 Giessen, Germany (e-mail: alexander.kloes@
ei.fh-giessen.de).
D. Goebel is with LTi Drives GmbH, 35633 Lahnau, Germany.
B. T. Bosworth is with the Department of Electrical Engineering, Princeton
University, Princeton, NJ 08544 USA.
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2008.2006535
0018-9383/$25.00 © 2008 IEEE
3467
the potential in triple-gate FETs, whose overview can be found
in [4]. To our knowledge, in the work published so far, the
results of this 3-D problem always led to an analytical solution
with a converging infinite series formalism. In order to obtain
a compact model equation, for certain geometry scaling, e.g., if
the channel thickness is less than the channel length, this series
can be approximated by its first terms [2], [4]–[6]. However,
increasing deviations can be expected if the channel length is
further scaled down. The approaches differ in the boundary
conditions defined at the bottom of the channel. In [2] and [6], it
is assumed that no field lines enter the channel region from the
buried oxide. On the other hand, in [4] and [5], the influence of a
back-gate bias is taken into account. The approaches presented
in [2], [5], and [6] solve the 3-D potential in a volume, including
the channel region and the gate oxide, whereas in [4], the
potential is solved only in the silicon channel while applying
boundary conditions at the silicon-to-oxide interface derived
from 1-D analysis. This avoids an accurate solution for corner
effects in the silicon channel. However, the solution in [4]
takes into account a mobile-charge term, making the approach
interesting for the near-threshold regime of undoped devices.
In this paper, we like to contribute an analytical structure-
oriented model for the potential barrier in undoped FinFETs,
which inherently includes short-channel and corner effects.
Since we neglect mobile charge, our potential solution is only
accurate in the subthreshold regime. The analytical approach
is derived by applying the conformal mapping technique [7],
which, in [8], was introduced in MOS transistor modeling for
the first time. The results of our model have already been pub-
lished in [9]. Here, for the first time, the details of the mathemat-
ical approach and the derived model equations are presented.
In the first step, a proper 2-D solution for the potential φdg
within a double-gate FET (DG-FET) is defined [10], [11].
Therefore, the problem is reduced to 2-D. From this model, we
find the position of the potential barrier along the center line of
the channel.
In the second step, at this position, we solve the 3-D potential
problem in a cross section of the triple-gate device, taking
into account the third gate electrode by applying again the
conformal mapping technique. Here, the same conformally
mapped structure, as defined in [8], will be used to model the
influence of the top gate on the potential barrier. We assume
that, in the triple-gate structure, the distance of the potential
barrier from the source is nearly the same as in the DG-FET,
which can be justified from numerical simulations. In the
subthreshold regime of operation, the most leaky path is close
3468 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008

to the bottom of the channel, where the triple-gate FET behaves

much like a DG-FET. Furthermore, in the vicinity of the barrier,
the potential profile is quite flat.
Finally, from the solution for the barrier height, an analytical
expression for the subthreshold slope is derived. Furthermore,
a definition of threshold is introduced which permits analytical
calculation of VT as well.
In our approach, we assume the substrate oxide to be thick
enough that field lines going from the channel to the substrate
can be neglected. We consider a device with undoped channel
region, so depletion charge does not have to be considered.
Herewith, in subthreshold operation, when mobile charges can
be neglected, Poisson’s equation in 3-D is reduced to a 3-D
Laplace equation
Qdep + qinv
Δφ(x, y, z) = − ≈ 0. (1)
εs

II. SOLVING 3-D POISSON ’ S EQUATION

A. Definition of DG-FET Solution
In order to solve the potential within a DG-FET, a four-corner
structure representing the channel region within this 2-D device
has to be considered. This structure can be regarded as a cross
section in plane xz of the FinFET device [refer to Fig. 1(b)].
In [10] and [11], a way to analytically solve the 2-D potential
problem is proposed which is based on the conformal mapping
technique as well. From that, an expression for the potential
barrier in undoped channels, including the drain-induced barrier
lowering (DIBL) effect, has been derived.
From this 2-D potential solution within the DG-FET, the
following parameters are obtained, where
φdg (x, z) potential solution within the DG structure;
xm position of the potential barrier along axis x;
φdg,m potential in the middle of the channel at
position xm ;
φdg,s potential at the silicon-to-oxide interface at
position xm ;
∂ 2 φdg /∂x2 second derivative of potential with respect to
x at position xm ;
∂ 2 φdg /∂z 2 second derivative of potential with respect to
z at position xm .
In [10], an analytical expression for the potential in a
DG-FET has been derived by conformally mapping the four-
corner device structure upon the upper plane W
     
1  1−ku 1 + ku
φdg (u, v) = V π−arctan − arctan
π gs kv kv
    
1−u 1+u
+ Vgs arctan + arctan
v v
    
1 − ku 1−u
+ Vbi arctan −arctan
kv v
  
Fig. 1. (a) Triple-gate FET on SOI substrate (FinFET), having a silicon 1 + ku
channel which, from three sides, is controlled by a gate electrode. (b) Boundary + (Vbi + Vds ) arctan
conditions for the Laplace equation in potential φ. (c) Transformed boundary kv
conditions by subtracting the DG solution φdg from the potential φ. In this  
1+u
decomposition, boundary T is treated as if it has potential Vbi . The error − arctan (2)
introduced hereby can be neglected if we assume that toxt is relatively small. v
KLOES et al.: MODEL FOR POTENTIAL BARRIER IN FinFETs RESULTING IN ANALYTICAL EQUATIONS 3469

where B. Definition of Boundary Conditions for 3-D Poisson

Vgs = Vgs − Vfb . (3) The 2-D solution from the DG model is used as a particu-
lar solution of the 3-D Laplace equation for the electrostatic
The center line from the source√to the drain (i.e., z = 0) is potential φ. Following the approach given in [8], we obtain
mapped upon a circle of radius 1/ k in upper plane W transformed boundary conditions for the structure, which define
the solution for the potential ϕ(x, y, z)
1
u = √ cos(θ) (4)
k ϕ(x, y, z) = φ(x, y, z) − φdg (x, z). (11)
1
v = √ sin(θ). (5) In the channel cross section, we get a 2-D potential problem
k
with a bias only applied to the top gate. We have to assure that
√
Here, θ is the angle along a half circle of radius 1/ k in the error introduced at boundary T [refer to Fig. 1(c)] can be
plane W . neglected. This is the case for a typical triple-gate FET where
At the position of the potential minimum, the conditions toxt is much less than the distance between the source end of the
  channel and the position where the potential barrier is located.
∂φdg (x, z)  ∂φdg (x, z)  It should be noticed that, at this stage, the potential problem
 = 0 and  =0 (6) does not fulfill the 2-D Laplace equation, because the influence
∂x  ∂z 
xm z=0 in the x-direction has to be taken into account.
must be fulfilled. Conformal mapping scales the electric field
by the derivative of the mapping function [7]
C. Geometry Scaling to Include 3-D Effect
     
 ∂φdg (z)   ∂φdg (w)   ∂w 
 = ·  So far, potentials φ and ϕ are neither given by a 2-D Laplace
 ∂z   ∂w   ∂z  . (7)
equation in the device cross section nor are they a solution of a
2-D potential problem. The field components in the x-direction
Therefore, we obtain the position of the potential barrier along have an increasing influence on the potential in the cross section
the center line of the channel as well in complex plane W by for decreasing channel length. The electric field components in
inserting (4) and (5) into (2) and solving for the root of its plane yz are reduced by this effect compared to a strictly 2-D
derivative with respect to θ potential problem, and hence, the influence of the top gate
 increases.
∂φdg (θ)  In order to include the effect of the third dimension, we
 = 0. (8)
∂θ  modify the device geometry in a special way. Following this
θm
approach discussed in this section, the conformal mapping tech-
This equation has been solved in closed-form nique can be applied in the channel cross section in plane yz
 for solving a 2-D Laplace equation in ϕ while taking the 3-D
1
2 (k + 1)Vds effect into account.
θm = π − arccos √
 . (9)
k 2Vgs − 2Vbi − Vds We start from the 3-D Laplace equation

Mapping back to the original Z plane is done by ∂2ϕ ∂2ϕ ∂2ϕ

Δϕ = + + = 0. (12)
√  ∂x2 ∂y 2 ∂z 2
L 2 k
2 F 1+k , cos(θ m )
xm = √  (10) Now, we consider a geometry scaling in the y-direction, i.e., the
2 k
K 1+k direction not considered in the DG solution. We define

where F is the standard (Lagrange) elliptic integral of the first y

y = (13)
kind and K is the complete elliptic integral of the first kind [7], a
[10]. These integrals can be approximated by generalized power
series or iteration methods and have been tabulated. where parameter a is independent from y, and can rewrite
The potential barrier φdg,m at position xm can be calculated the second derivative of ϕ with respect to y  in this mapped
by evaluating (2) at θm . If the potential is calculated at several geometry. We arrive at
positions x and z in the vicinity of the barrier (at least three
positions each), an approximation for the second derivatives ∂2ϕ 1 ∂2ϕ
2
= 2 · 2 . (14)
∂ 2 φdg /∂x2 and ∂ 2 φdg /∂z 2 at this point can be calculated. ∂y a ∂y
These results will be used for the 3-D solution of the Laplace
equation in the triple-gate device at the potential barrier. If we insert (14) into (12), we get
The potential of the silicon surface φdg,s at position xm
can be determined from the normal electrical field at the gate ∂2ϕ 1 ∂2ϕ ∂2ϕ
2
+ 2 · 2 + = 0. (15)
electrodes [11]. ∂x a ∂y ∂z 2
3470 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008

Manipulation results in
  2
∂2ϕ ∂2ϕ ∂2ϕ 1 ∂ ϕ
+ 2 + + − 1 · 2 = 0. (16)
∂x2 ∂y ∂z 2 a2 ∂y
In order to solve for the potential ϕ in plane zy  by conformal
mapping, we have to fulfill
∂2ϕ ∂2ϕ
Δϕ = + =0 (17)
∂y 2 ∂z 2
so the scaling factor a results from the condition
  2
∂2ϕ 1 ∂ ϕ
2
+ 2
− 1 · 2 = 0. (18)
∂x a ∂y
For transformed boundary conditions, near the top gate, we
obtain the largest absolute values for ∂ 2 ϕ/∂x2 and ∂ 2 ϕ/∂y 2 .
If Tch  Hch , closer to the substrate, both terms become ≈ 0,
and (18) becomes valid for any value of a. That is reasonable
because, here, the 3-D solution for φ tends to be equivalent
to the potential within the DG-FET, and hence, ϕ ≈ 0 and is
independent of a.
That is the reason why we calculate the scaling parameter a
from the boundary at the top gate, showing a constant potential
φ. Here, from (11), we can follow

∂2ϕ ∂φ2dg Fig. 2. (a) Device cross section in plane Z and its conformally mapped
2
=− (19) representation in plane W . (b) Boundary condition along electrode B in
∂x ∂x2 plane W . The parabolic boundary condition in plane Z results in an elliptically
2
∂ ϕ ∂φ2dg shaped potential profile along axis u.
= − . (20)
∂z 2 ∂z 2 
Hch + toxt  Tch . Nevertheless, the approach can also be ap-
The second derivatives of the DG solution have been obtained plied to a four-corner structure, as given in [10].
in Section II-A from [10] and [11]. In the channel cross section, the gate oxide of thicknesses
From (17), we get toxs and toxt , having a dielectric constant εox , is replaced by
that of equivalent thicknesses t̃oxs and t̃oxt , respectively, with
∂2ϕ ∂2ϕ ∂φ2dg the same dielectric constant as the silicon body [8]
= − = . (21)
∂y 2 ∂z 2 ∂z 2
εs  εs
t̃oxt = t̃ toxs = toxs . (25)
Now, we can solve (18) for parameter a εox oxt εox
 
 ∂2ϕ ∂2ϕ  ∂φ2 Fig. 2(a) shows the 2-D structure of plane yz with the given
  dg ∂φ2
1  ∂x2 + ∂z2  ∂x2 + ∂zdg boundary conditions in complex plane Z with ẑ = x̂ + iŷ. Ac-
=
2
= . (22)
a ∂2ϕ ∂φ2dg cording to (11), along electrodes A and C, we get the boundary
2 ∂z ∂z 2 condition ϕ = 0. The boundary condition along electrode B
results from the DG solution
With scaling of all dimensions and boundaries in direction y
by a factor of 1/a, we can describe the 3-D potential problem ϕ̄(x̂) = Vgs − φdg (xm , z). (26)
by a 2-D Laplace equation in the cross section. Therefore, in the
subsequent approach for solving the 2-D potential problem by The conformal mapping function which results in the rep-
conformal mapping, we use the following device parameters: resentation of the 2-D structure in complex plane W [refer to
Fig. 2(b)] with w = u + iv is given by [8]
Hch

Hch = (23)  
a πẑ
toxt w = f −1 (ẑ) = cosh . (27)
toxt = . (24) Tch + 2t̃oxs
a
For calculation of the potential solution ϕ in the conformally
D. Solving 2-D Laplace Equation at Potential Barrier mapped geometry, the Poisson integral [7] in complex plane W
has to be solved
In the next step, we solve the 2-D Laplace equation (17)
by using the conformal mapping technique. In order to keep 1
1 v
the expression at a manageable level, we use the two-corner ϕ(u, v) = ϕ̄(ū)dū. (28)
π (ū − u)2 + v 2
structure introduced in [8]. For that, we have to assume that −1
KLOES et al.: MODEL FOR POTENTIAL BARRIER IN FinFETs RESULTING IN ANALYTICAL EQUATIONS 3471

Fig. 3. Potential in the device cross section calculated by the analytical

model. Device parameters: L = 20 nm, Hch = 20 nm, Tch = 10 nm, and
toxs = toxt = 2 nm. Bias conditions: Vgs = −0.55 V and Vds = 0 V.

Here, ϕ̄(ū) is the boundary condition ϕ̄ along electrode B in

plane W . The conformal mapping function defines the relation
between ū and ŷ
 
π ŷ
ū = cos . (29)
Tch + 2t̃oxs
In order to get a closed-form solution for the Poisson integral,
we approximate the potential profile ϕ̄ along axis u. Fig. 2(b)
shows the elliptical approximation ϕ̃(ū) ≈ ϕ̄(ū), which can be
written as


ϕ̃(ū) = Vgs − φdg,m 1 − ū2 . (30)

Integration results in

1
1 v
ϕ(u, v) = ϕ̃(ū)dū
π (ū − u)2 + v 2
−1 Fig. 4. Potential φ for (a) Vds = 0 and various gate biases and for (b) Vgs =

 −0.55 V and various drain biases along the trace, as defined in the upper plot
= Vgs − φdg,m in devices with a channel length of 20 nm. (Solid lines) Results calculated by
   the model. (Dashed lines) Sentaurus. In both plots, the accuracy of the model is
1   better than 20 mV.
× 1 − (u − iv) + 1 − (u + iv) − v .
2 2
2
(31) For comparison with the numerical device simulation results
computed with Sentaurus [12], we compare the potential along
Using this result together with (27), we can calculate the the silicon surface and in the middle of the channel. In Fig. 4(a),
potential ϕ for each position (y  , z)=(x̂,
ˆ iŷ). If we add the DG the trace is defined which is followed within the device cross
solution φdg (x, z) according to (11), we obtain the potential φ section in the subsequent plots.
in the channel cross section at position (y  , z) and, finally, by Fig. 4(a) shows the potential along the trace in a device with
rescaling y according to (13), at position (y, z). 20-nm channel length and a bias of Vds = 0.05 V. We observe
very good agreement with the numerical results, even in the
corner regions of the device. In Fig. 4(b), we investigate the
III. RESULTS OF 3-D POTENTIAL SOLUTION
influence of an applied drain voltage on the potential. Even
For evaluation of our analytical result, we consider triple-gate for Vds = 1 V, we obtain good agreement along the trace. The
devices with toxs = toxt = 2 nm and εox = 7ε0 and aluminum accuracy in both plots is better than 20 mV.
gate (work-function difference: −0.55 V). In Fig. 3, the poten- Below threshold, the most leaky path will be located at
tial profile in the middle of the channel as it results from (31) the bottom middle of the channel. The height of the potential
is shown. Due to the approximation of ϕ̃ in (30), we notice a barrier φm at this position is essential for the calculation of
slight ripple along the boundary at the top gate. the subthreshold current or the threshold voltage in Sections IV
3472 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008

and V, respectively. The position of the most leaky path in the where the total current is given by integration of (36) in the
channel cross section in plane Z is given by (refer to Fig. 2) cross section excluding the oxide
   
  φ(y, z)

  Tch Isth = isth dy dz ∼ ni exp dy dz. (38)
ẑm = Hch + t̃oxt + i + t̃oxs . (32) Vth
2
Due to the closed-form solution for the potential φ, the total
Using the conformal mapping function (27), we obtain in current can easily be obtained by computing (36) at discrete
complex plane W points in the cross section and herewith approximating (38).
Hence, by (37), the slope can be calculated without numerical
wm = um + ivm (33) iteration.
In order to arrive at a closed-form solution for (38), the poten-
where um = 0 and, considering (23) and (24) tial solution within the cross section including the oxide can be
  approximated by the following function, which is parabolically
π Hch + t̃oxt shaped with respect to y and z:
vm = cosh · . (34)
a Tch + 2t̃oxs  2   2 



 y z
φ̃(y, z) = Vgs + φm − Vgs · 1 − · 1−
Now, using (11) and (31), we can write a compact expression y0 z0
for the height of the potential barrier at the most leaky path (39)

φm = φdg,m + ϕ(0, vm ) where the position y = 0, z = 0 is the bottom center of the

channel region with potential φm , and y0 = (Hch + toxt ) and


 
= φdg,m + Vgs − φdg,m 2 −v
1 + vm m . (35)
z0 = (Tch /2 + toxs ). This approximation with respect to the
y-direction gets worse if Hch  Tch . For this case, this approx-
As expected, for a large channel height Hch  Tch with vm  1, imation should only be used in the top device, whereas in the
we obtain φm ≈ φdg,m , i.e., the top gate loses control, and we bottom device, a parabolic approximation only with respect to
obtain the DG solution for the potential barrier with a maximum y is necessary.
influence of the source/drain potential on the barrier height. Integration along the z-axis results in
If we increase the influence of the top gate by Hch  Tch , z0  
φ̃(y, z)
(35) results in φm ≈ Vgs , resulting in suppressed short-channel fz (y) = exp dz
effects due to an increased control of the gate on the channel Vth
potential. Therefore, the model correctly predicts the influence
0
   √  
Vgs πz0
of the top gate on the barrier height. = exp + g(y) ·  · erf g(y) (40)
Vth 2 g(y)
The channel length L takes influence on φm by scaling
parameter a in (34), which, by (22), is controlled by the shape where
of the DG solution. If ∂ 2 φdg /∂x2 = 0, which is the case for   2 
a long-channel device, we obtain a = 1 and, therefore, a 2-D φm − Vgs y
g(y) = 1− . (41)
potential problem within the channel cross section without any Vth y0
need for scaling the channel height in the analytical solution.
For short-channel lengths, we obtain a > 1. Here, due to scaling Before integrating with respect to y, the result on a log scale is
of the channel height, the 3-D potential solution takes into once more parabolically approximated
account the electric field along the channel and results in a 
further increase of the gate control compared to a strictly 2-D fz (y) ≈ exp ln (fz (y = 0))
solution.
 2 
y
− [ln (fz (y = 0)) − ln(fz (y0 ))] .
IV. MODELING OF SUBTHRESHOLD CURRENT y0
(42)
For calculation of the subthreshold current, we assume that,
at each position within the cross section, the contribution to the This ensures a closed-form solution for the final integral with
total channel current is proportional to the total amount of free respect to y, and we obtain as result for (38)
electrons diffusing over the barrier [13]
  y0
φ(y, z) Isth ∼ ni fz (y) dy
isth ∼ ni exp . (36)
Vth 0
√  
The slope can be expressed as πy0 erf ln (fz (y = 0)) − ln (fz (y0 ))
≈ 
∂Vgs 2 ln (fz (y = 0)) − ln (fz (y0 ))
S= (37)
∂ log Isth · ni · exp (fz (y = 0)) . (43)
KLOES et al.: MODEL FOR POTENTIAL BARRIER IN FinFETs RESULTING IN ANALYTICAL EQUATIONS
Fig. 5. Subthreshold slope versus channel length for different channel geome-
tries and bias conditions. The slope degradation is accurately predicted by the
model. Top and side oxide thickness: 2 nm. Bias condition: Vgs = −0.55 V.
(Symbols) Sentaurus. (Lines) Analytical model.
Finally, evaluating this result at two distinct gate biases Vgs1 and
Vgs2 , we get an analytical solution for the subthreshold slope
Vgs2 − Vgs1
S= . (44)
log(Isth2 /Isth1 )
The results of this model that are compared with the numerical
device simulation results computed with Sentaurus [12] are
shown in Fig. 5. Slope degradation is correctly predicted. The
increasing deviation of our model for a channel length below
30 nm is because of the fact that, in Section II-B, boundary
T has been neglected. Furthermore, in the numerical results,
part of the voltage drop across the junctions extends into the
highly doped source/drain regions, whereas for the model, fixed
boundary conditions at both channel ends have been defined.
In Fig. 5(a), for a channel height of Hch = 20 nm, our model
3473
Fig. 6. Numerical results for potential φ with Vds = 0 V and gate bias below
(Vgs = −0.15 V) and above (Vgs = −0.05 V) threshold. The plot shows the
potential along the trace defined in Fig. 4 at the position of the potential barrier.
Below threshold, the most leaky path is at the end of the trace (bottom middle
of the channel), whereas above threshold, this path moves to the silicon surface
and, in particular, to the corner regions.
gets worse for higher drain-to-source voltages. This can be
contributed to the fact that, in our approach, the potential barrier
is assumed to be at the same position as in the DG solution.
V. DEFINITION AND MODELING OF VT
Fig. 6 shows numerical results for the case of a gate bias
below and above threshold. Below threshold, the most leaky
path, i.e., the minimum of the potential in the cross section
located at the position xm of the barrier, is located in the bottom
middle of the channel, whereas above threshold, the inversion
channel moves to the silicon surface, and the most leaky path is
located in the corners of the cross section.
According to this behavior, we simply define the threshold
condition as the gate bias which results in a certain electron
concentration, i.e., an inversion potential φi in the most leaky
path. While increasing the gate voltage, before strong inversion
sets on at the surface of the silicon fin, this concentration is
obtained first in the middle of the channel. The corresponding
gate bias is defined as the threshold voltage.
It should be noted that this definition does not take into
account further effects such as volume inversion in the silicon
fin. However, it is capable of covering main short-channel
effects such as VT roll-off and DIBL in a very easy way and
can therefore be useful to compare different device geometries.
For calculation of VT , at two different gate voltages below
threshold, we compute the potential at the barrier from the 3-D
potential solution by (35). Therefore, we still neglect the mobile
charge in solving Poisson’s equation. While linearly extrapolat-
ing this result, we obtain a closed-form result for the threshold
voltage by the gate bias where potential φi at the barrier is
reached
φi − φm (Vgs1 )
VT = Vgs1 + (Vgs2 − Vgs1 ) · . (45)
φm (Vgs2 ) − φm (Vgs1 )
3474
Fig. 7. (a) DIBL effect versus channel length L. The plot shows threshold
voltage shift dVT between Vds = 0.05 V and Vds = 1 V for two different
channel heights. (Line) Analytical model. (Symbols) Sentaurus. (b) Threshold
voltage VT of a FinFET with a channel length of 60 nm versus channel
thickness Tch for various channel heights Hch ’s. For a height of 65 nm, (thick
line) the analytical model is compared to (symbols) measurements which were
taken from [2].
In Fig. 7(a), the results of the threshold voltage model are
compared with the numerical results computed by Sentaurus.
The inversion potential φi at threshold has been taken as the
fitting parameter that is independent of channel geometry (φi =
0.793 V which corresponds to an electron concentration of
5 · 1018 cm−3 at the most leaky path). The increase of the DIBL
effect with decreasing channel length is in good agreement
with the simulation results due to the better control of the
channel potential by the gate. As expected, it can be seen that
a reduced channel height and thickness results in less short-
channel effects. Because, in this plot, the relative shift of the
threshold voltage is shown, here, obviously, the effects causing
in Fig. 5 deviations of our model for short-channel lengths have
only a minor influence.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008
Furthermore, in Fig. 7(b), the dependence of threshold volt-
age on the thickness of the silicon fin fits very well to data
from measurements published in [2] (having been extracted by
a constant current criterion). The influence of channel height
and thickness on VT is correctly predicted by our model.
VI. CONCLUSION
An analytical approach to calculate the 3-D electrostatic
potential in undoped triple-gate SOI MOS devices was pre-
sented. It is valid below threshold and is based on transforming
a 3-D Laplace equation within a cross section by geometry
scaling into a 2-D Laplace equation. This equation has then
been solved by the conformal mapping technique. By this
approach, the height of the potential barrier was calculated
in a highly structure-oriented way, obtaining closed-form ex-
pressions, including corner effects. This result can be used as
starting point to define a current model for circuit simulation
purposes.
With this result, the degradation of the subthreshold slope by
geometry scaling can be calculated very efficiently. We defined
a simple threshold voltage model which is able to predict
the influence of channel length, width, and height, including
the DIBL effect. These results are in good agreement with
numerical device simulation results and can therefore be useful
for predictive device scaling investigations.
To our knowledge, with our model, for the first time, a
fully analytical approach is presented, which does not require
an infinite series formalism to expresses the bias-dependent
influence of 3-D effects on the barrier height in FinFETs in a
closed form. However, it should be noted that our solution does
not include mobile charge and therefore does not cover effects
such as volume inversion or quantization effects.
ACKNOWLEDGMENT
The authors would like to thank B. Iñiguez, Universitat
Rovira i Virgili, Tarragona, Spain, and T. A. Fjeldly, Univer-
sity Graduate Center, Kjeller, Norway, for the many useful
discussions.
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[3] N. Collaert et al., “Multi-gate devices for the 32 nm technology node and
beyond,” in Proc. ESSDERC, Munich, Germany, 2007, pp. 143–146.
[4] H. A. El Hamid, J. R. Guitart, V. Kilchytska, D. Flandre, and B. Iñiguez,
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KLOES et al.: MODEL FOR POTENTIAL BARRIER IN FinFETs RESULTING IN ANALYTICAL EQUATIONS
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Alexander Kloes (M’95) received the Diploma and
Ph.D. degrees in electrical engineering from the
Solid-State Electronics Laboratory, Darmstadt Uni-
versity of Technology, Darmstadt, Germany, in 1993
and 1996, respectively.
He was an R&D Project Manager with Braun
GmbH, Kronberg, Germany, from 1997 to 2002,
where he focused on IR sensor technology in sili-
con. Since 2002, he has been a Professor with the
University of Applied Sciences Giessen–Friedberg,
Giessen, Germany. His research interests include
semiconductor device modeling, specifically for nanoscale MOS devices.
Prof. Kloes is an Associate Member of COMON (Compact Modelling Net-
work, European Union’s 7th Research Framework Programme), contributing to
the research group at the Universitat Rovira i Virgili, Tarragona, Spain.
3475
Michaela Weidemann (M’06) received the Diploma degree from the Univer-
sity of Applied Sciences Giessen–Friedberg, Giessen, Germany, in 2005 and
the M.S. degree in electrical engineering from the Universitat Rovira i Virgili,
Tarragona, Spain, in 2007, where she is currently working toward the Ph.D.
degree. The main focus of her dissertation is compact modeling of multiple-
gate FETs.
She is currently with the University of Applied Sciences Giessen–Friedberg.
Daniel Goebel received the Diploma degree in elec-
trical engineering from the University of Applied
Sciences Giessen–Friedberg, Giessen, Germany,
in 2008.
He is with LTi Drives GmbH as Engineer R&D.
During his study, he was with the Device Model-
ing Research Group, University of Applied Sciences
Giessen–Friedberg, in various projects on numerical
device simulations.
Bryan T. Bosworth is currently working toward the
B.S. degree in electrical engineering in the Depart-
ment of Electrical Engineering, Princeton University,
Princeton, NJ.
He was an Intern Software Engineer with ARINC,
Inc., an Intern Electrical Engineer with Northrop
Grumman Electronic Systems, and as a RISE
Intern with the University of Applied Sciences
Giessen–Friedberg, Giessen, Germany. His general
research interest includes semiconductor devices.