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Abstract—The titanium nitride (TiN) gate electrode with a doping concentration in scaled FinFETs. Furthermore, the
tunable work function has successfully been deposited on the impurity fluctuation in the thin Si-fin channel should result in
sidewalls of upstanding Si-fin channels of FinFETs by using a the severe variation. On the contrary, the gate work function
conventional reactive sputtering. It was found that the work func-
tion of the TiN ( TiN ) slightly decreases with increasing nitrogen engineering can offer a promising method to control the in
(N2 ) gas flow ratio, = N2 (Ar + N2 ) in the sputtering, the undoped Si-fin channel device. The total gate silicidation
from 17% to 100%. The experimental threshold voltage ( th ) [8] and the combination of a metal (molybdenum) gate and a
dependence on the shows that the more offers the lower nitrogen implantation technique [11], [19] have been proposed
th for the TiN gate n-channel FinFETs. The composition analysis to obtain the correct for FinFETs. As one of the promising
of the TiN films with different showed that the more amount
of nitrogen is introduced into the TiN films with increasing , metal gate materials, the sputtered TiN has been studied for
which suggests that the lowering of TiN with increasing conventional planar CMOS devices due to its high purity and
should be related to the increase in nitrogen concentration in thermal stability [22]–[28]. Very recently, the conformal TiN
the TiN film. The desirable th shift from 0.22 to 0.22 V was
experimentally confirmed by fabricating n+ poly-Si and TiN
deposition by a chemical vapor deposition (CVD) method has
actively been developed for three-dimensional device structures
gate n-channel multi-FinFETs without a channel doping. The
developed simple technique for the conformal TiN deposition on in such a multigate MOSFET [29]–[32], and the well symmet-
the sidewalls of Si-fin channels is very attractive to the TiN gate rical of both nMOS and pMOS devices has been obtained
FinFET fabrication. without a channel doping, thanks to the midgap . However,
Index Terms—Double-gate MOSFET, FinFET, metal gate, tiN- to our knowledge, there have been no reports regarding TiN
gate, work function. gate FinFETs using a conventional reactive sputtering, except
our recent works [33], [34].
In this paper, we report the experimental study of the TiN gate
I. INTRODUCTION electrode with a tunable work function by using a conventional
reactive sputtering for the FinFET fabrication. The uniform TiN
deposition on the sidewalls of the right-angled Si-fin channels
ECENTLY, the fin-type double-gate (DG) [1] MOSFET
R (FinFET) [2] has been received considerable attentions
as the most scalable device. The advantages of FinFETs such
and the controllability of the by changing a nitrogen gas
flow ratio in the sputtering are demonstrated.
as the excellent short-channel effects (SCEs) immunity and
II. FABRICATION PROCESSES
high current drivability have been confirmed experimentally
[2]–[19]. However, there are some technological challenges So far, we have developed the simple fabrication technique of
for the fabrication of the practical high-performance CMOS Si-fin channels with an ideal rectangular cross section [12]–[16]
FinFETs. One of the most important issues for the CMOS and ultrathin vertical Si walls [20], [21] using the orientation-de-
FinFETs is the setup of the proper for both the nMOS pendent wet etching, and we demonstrated the excellent elec-
and pMOS. Some techniques to adjust the , e.g., the body trical characteristics of the n poly-Si gate n-channel FinFETs.
doping and n asymmetric gates [7], have been proposed In the n poly-Si gate n-channel FinFETs in the previous works,
so far. However, the traditional body doping should cause however, the was not managed and actually showed a neg-
carrier mobility degradation because of the need of increasing ative value of V. The main target of this work is to de-
velop the TiN gate FinFET with a proper . To fabricate such
Manuscript received May 16, 2006; revised August 7, 2006. The review of
a device by using a conventional reactive sputtering, the uni-
this paper was arranged by Associate Editor B. G. Park. form TiN deposition on the sidewalls of Si-fins and fine TiN
Y. Liu, E. Sugimata, M. Masahara, K. Endo, T. Matsukawa, K. Ishii, K. patterning technique should be established.
Sakamoto, T. Sekigawa, H. Yamauchi and E. Suzuki are with the National In-
stitute of Advanced Industrial Science and Technology (AIST), Tsukuba 305-
To explore the best sputtering condition, we investigated the
8568, Japan (e-mail: yx-liu@aist.go.jp). pressure dependence of the TiN deposition from both the mea-
S. Kijima and Y. Takanashi are with the Tokyo University of Science, 2641 surement of the TiN resisitivity and observation of the TiN cross
Yamazaki, Noda, Japan. section on the Si-fin channels fabricated by the orientation-de-
Color versions of Figs. 1 and 5 are available online at http://ieeexplore.ieee.
org. pendent wet etching. It is found that the TiN resistivity increases
Digital Object Identifier 10.1109/TNANO.2006.885035 markedly with increasing pressure in the sputtering as shown in
1536-125X/$20.00 © 2006 IEEE
724 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 6, NOVEMBER 2006
Fig. 8. XPS spectrum of TiN film deposited at 1 Pa. No carbon and oxygen are Moreover, it should be noted that the TiN is continuously con-
observed. Insert is the composition ratio of N/Ti in the TiN films as a function tacted with the upstanding gate oxide surface without any voids
of R .
regardless of the rough surface due to crystallization of the TiN
film in the sputtering process. Therefore, it is concluded that
is controlled from 0 to 17%. This result is reasonable be- the conventional reactive sputtering can be used in the TiN gate
cause the sputtered metal at should be titanium (Ti). FinFET fabrication by optimizing the sputtering pressure.
With further increasing from 17 to 83%, it is experimentally The gate to channel capacitance and drain current
found that the slightly decreases from 4.82 to 4.71 eV. This of the fabricated multi-FinFETs with the TiN and n poly-Si
result is basically consistent with the reported data [27]. To ex- gates were measured and the results are plotted as a function of
plore the origin of the lowering, the composition analysis gate voltage as shown in Fig. 10. The significant -
of TiN films with different ’s was performed by X-ray pho- and - curve shifts in the positive direction are achieved
toelectron spectroscopy (XPS) as shown in Fig. 8. It is clear that without any channel doping by replacing the n poly-Si gate
no impurities such as carbon and oxygen are detected, which with the TiN gate. Note that the optimum of 0.22 V for
means that the sputtered TiN is a high purity film. But, the ratio n-channel multi-FinFETs is realized by using the TiN gate de-
of nitrogen/titanium (N/Ti) in the sputtered TiN films slightly posited with the of 83%. The gate current of the TiN
increases with increasing as shown in the insert in Fig. 8. and n poly-Si gate multi-FinFETs were also examined. As a
Therefore, it is reasonably considered that the lowering result, no marked leakage currents were observed in the TiN
should be related to the higher N/Ti ratio. gate multi-FinFETs. This indicates that the quality of gate oxide
The plane-SEM image of the fabricated TiN gate layer of 2.2 nm on the sidewall surface of the Si-fin channel was
multi-FinFET is shown in Fig. 9(a). It is clearly shown not deteriorated in the sputtering process, which is consistent
that the multifins are fabricated uniformly and the TiN gate with the reported gate oxide integrity data [23]. The reliability
is formed at the center of the multifin channels. The cross issue of the thin gate oxide by the TiN deposition still requires
section of the fabricated TiN gate multi-FinFET was observed further study.
by a scanning transmission-electron microscope (STEM) and The measured – characteristics of the fabricated multi-
the cross-sectional images are shown in Fig. 9(b) and (c). It FinFETs with the different TiN gates deposited at two different
is noteworthy that the uniform TiN film is deposited on the ’s (17 and 83%) are shown in Fig. 11(a). These two devices
sidewalls of the ideal rectangular cross section Si-fin channels. were fabricated the same processes except the . It is clear
LIU et al.: INVESTIGATION OF THE TIN GATE ELECTRODE WITH TUNABLE WORK FUNCTION AND ITS APPLICATION FOR FINFET FABRICATION 727
Yongxun Liu was born in Jilin, China, in 1961. He Kazuhiko Endo received the B.S., M.S. and Ph.D.
received the B.S. degree in electronics engineering degrees in electrical engineering from the Waseda
form Jilin University, China, in 1983 and the M.S. University, Tokyo, Japan, in 1991, 1993 and 1999,
and Ph.D. degrees from Tohoku University, Sendai, respectively. From August 1999 to August 2000 he
Japan, in 1996 and 1999. was a Visiting Scholar at the Stanford University
From 1999 to 2001, he was a Research Assistant Center for Integrated Systems, where he worked on
at the department of Mechatronics and Precision En- the thermal effects in the Cu interconnects. He was
gineering, Tohoku University, where he worked on with Silicon Systems Research Laboratories, NEC
MEMS devices. In 2001, he joined the National Insti- Corporation from 1993 to 2003, where he worked
tute of Advanced Industrial Science and Technology on the research and development of multilevel inter-
(AIST), Tsukuba, Japan, where he has been engaged connection of ULSI, high-k gate stack technologies.
in the research and development of nanoscale silicon devices such as double- He is a Researcher in the Silicon Nanoscale Devices Group, Nanoelectronics
gate MOSFET and SOI devices. He is also interested in the fabrication of bar- Research Institute, National Institute of Advanced Industrial Science and
rier controlled tunneling and ballistic devices such as the ideal static induction Technology, Tsukuba, Japan. His research interests include nanometer-scale
transistor (ISIT) as well as in device physics. manufacturing for high-performance and low-power ULSI. He also works on
Dr. Liu is a member of the Japan Society of Applied Physics. exploratory high-performance interconnects. Additionally, his research extends
to aggressively scaled double gate transistors in advanced VLSI technologies.
Dr. Endo is a member of the Japan Society of Applied Physics. He is the
recipient of a Best Paper Award at the 2003 Advanced Metallization Conference,
Shinya Kijima was born in Saitama, Japan, in 1981. and at the 1998 Meeting of Japan Society of Applied Physics.
He received the B.E. and M.S. degrees from the
Tokyo University of Science, Tokyo, Japan, in 2003
and 2005, respectively.
In 2005, he joined Toyota Motor Corporation,
Aichi, Japan.
Takashi Matsukawa received the B.S., M.S.,
and Ph.D degrees in electrical engineering from
the School of Science and Engineering, Waseda
University, Tokyo, Japan.
From 1993 to 1996, he was a JSPS Scholarship
Fellow at Waseda University working on testing of
soft-error immunity against high-energy ion irradia-
tion. From 1996 to 1998, he was a Research Associate
Etsuro Sugimata was born in Ishikawa, Japan, in of Waseda University working on development of a
1970. He received the B.E. degree in electrical engi- novel ion-implantation technique. In 1998, he joined
neering and M.S. and Ph.D. degree in material design the Electrotechnical Laboratory, Ibaraki, Japan. He is
engineering from Kanazawa Institute of Technology now a Senior Researcher of National Institute of Advanced Industrial Science
in 1995, 1997, and 2000, respectively. and Technology (AIST), Tsukuba, Japan, and is working on microscopic anal-
He is a Postdoctoral Researcher at the National ysis of device/process using scanning probe microscopy.
Institute of Advanced Industrial Science and Tech- Dr. Matsukawa is a member of the Japan Society of Applied Physics.
nology (AIST), Tsukuba, Japan, From 2000 to 2003,
he was engaged in the research and development of
intrinsic Josephson junction (IJJ) and high temper-
ature superconducting devices. From 2004 to 2006,
he was engaged in the research and development of nanoscale silicon devices
such as metal-gate MOSFETs. Kenichi Ishii was born in Tokyo, Japan, on De-
Dr. Sugimata is a member of the Japan Society of Applied Physics and the cember 10, 1945.
Ceramic Society of Japan. In 1969, he joined the Electrotechnical Laboratory
(ETL), Ibaraki, Japan, where he worked on the
research and development of silicon processes for
double-gate MOSFET (XMOSFET) and thin film
solar silicon cell devices. In 2001, he joined the Na-
Meishoku Masahara received the B.S., M.S. tional Institute of Advanced Industrial Science and
and Ph.D. degrees in electrical engineering from Technology (AIST) with the reorganization of ETL,
the School of Science and Engineering, Waseda Tsukuba, Japan, where he has been engaged in the
University, Tokyo, Japan, in 1990, 1992 and 1995, research and development of fabrication processes
respectively. for ultrathin and ultra-short channel SOI devices and double-gate MOSFETs.
From 1994 to 1996, he was a Research Associate Mr. Ishii is a member of the Japan Society of Applied Physics.
at Waseda University, and worked on development of
single-ion microprobe system for MOS device diag-
nosis. From 1996 to 1998, he was a Researcher at
CREST, Japan Science and Technology Corporation
(JST) and joined Research Center for Nanodevices
and Systems, Hiroshima University, where he worked on research and devel- Kunihiro Sakamoto was born in Tokyo, Japan, in
opment of small-geometry MOSFETs with ultrathin gate oxide. From 1998 to 1959. He received the B.S. and Ph.D. degrees in
2000, he was a Visiting Lecturer at Kagami Memorial Laboratory for Materials electrical engineering from the University of Tokyo,
Science and Technology, Waseda University, and worked on development of Japan, in 1981 and 1986, respectively.
a novel Si nanoprocess. He is now a senior researcher of National Institute of He joined the Electrotechnical Laboratory (ETL),
Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, and is Tsukuba, Japan in 1986, which was reorganized into
working on research and development of multigate MOSFETs. From July 2005 the Institute of Advanced Industrial Science and
to June 2006, he also worked at IMEC as a Visiting Researcher. He has pub- Technology (AIST), Tsukuba, in 2001. He spent the
lished over 100 research papers in archival journals and refereed international first ten years in ETL studying MBE growth and
conferences on these subjects. characterization of Si/Ge nano structures. Since then
Dr. Masahara serves on the Technical Program Committee of the Symposium he has researched silicon technology focusing on
on VLSI Technology, and International Microprocesses and Nanotechnology advanced contact process for scaled CMOS devices, and is presently involved
Conference. He is a member of the IEEE Electron Devices Society, the Institute in work on double-gate CMOS technology.
of Electrical Engineers of Japan, and the Japan Society of Applied Physics. Dr. Sakamoto is a member of the Japan Society of Applied Physics.
730 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 6, NOVEMBER 2006
Toshihiro Sekigawa received the B.E. degree in elec- GaAs 2DEG transistors, and GaAs permeable base transistors. Since 1987, he
trical engineering from Yokohama National Univer- has been engaged in research on bipolar transistors and phototransistors com-
sity, Yokohama, Japan, in 1966 and the Ph.D. degree posed of InP-based material systems at the Opto-Electronics Laboratories, NTT.
in electrical engineering from the Tokyo Institute of In 1999, he joined the Tokyo University of Science, Chiba, Japan, where he is
Technology, Tokyo, Japan, in 1993. now a Professor in the Department of Materials Science and Technology.
In 1966, he joined the Electrotechnical Labora- Dr. Takanashi is a member of the Japan Society of Applied Physics and the
tory, Ibaraki, Japan, and since then has done research Institute of Electronics, Information and Communication Engineers (IEICE) of
on devices and integrated circuits, such as Schottky Japan.
TTL, low power high speed ECL, DSA MOS
transistors including VMOS, low submicrometer
MOS transistors with punchthrough stopper, XMOS
transistors for deca-nanaometer regime, and thin film Si solar cells. He is Eiichi Suzuki was born in Mie, Japan, in 1947. He
interested in research on very small size MOS devices for the future. received the B.E. degree in electronic engineering
Dr. Sekigawa received the 1990 SSDM award from International Solid State from Nagoya Institute of Technology, Nagoya,
Device and Materials Conference at Sendai, Japan, in 1990. He is a member of Japan, in 1970 and the M.S., and Ph.D. degrees in
Electronics, Information, and Communication Engineers of Japan. electronic engineering from the University of Tokyo,
Tokyo, Japan, in 1972 and 1983, respectively.
In 1972, he joined the Electrotechnical Laboratory
(ETL), Ibaraki, Japan, where he was engaged in
Hiromi Yamauchi was born in Nagasaki, Japan, research and development of nonvolatile semicon-
in 1973. She received the B.S. degree in chemistry ductor memories, solar cells, quantum functional
and chemical engineering from Niigata University, devices, and short-channel MOS devices. In April
Niigata, Japan, in 1997. 2001, he joined the Nanoelectonics Research Institute (NeRI), National Insti-
In 2000, she joined the National Institute of tute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan,
Advanced Industrial Science and Technology with the reorganization of ETL, and assumed the deputy-director of NeRI and
(AIST), Ibaraki, Japan, where she has been engaged the group leader of the Silicon Nanoscale Devices Group. He is a Visiting
in the development of nanostructure observation Professor of Science University of Tokyo, Noda, Japan, since 2000. From 1985
technology by scanning transmission-electron mi- to 1986, he was a Visiting Faculty Associate at the Department of Electrical
croscope (STEM) and nanoscale semiconductor Engineering, Arizona State University, Tempe, working on characterization of
device fabrication process. nonvolatile semiconductor memory.
Dr. Suzuki is a member of the Institute of Electronics, Information and Com-
munication Engineers of Japan, the Japan Society of Applied Physics, and the
Electrochemical Society. He received the Ohm Technology Award in 1996.
Yoshifumi Takanashi was born in Yokohama,
Japan, on November 25, 1949. He received the
B.S. degree in physics from the Tokyo University
of Science, Japan, in 1972, and the M.S. degree in
physics and Ph.D. degree in electronic engineering
from the Tokyo Institute of Technology, Japan, in
1974 and 1983, respectively.
Since joining the Musashino Electrical Communi-
cation Laboratories, NTT, Tokyo, Japan in 1974, he
has worked on 0.8-m AlGaAs/GaAs light sources,
1.0–1.5-m InP/InGaAs optical detectors, AlGaAs/