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Extremely Scaled Silicon Nano-CMOS Devices

LELAND CHANG, STUDENT MEMBER, IEEE, YANG-KYU CHOI, DAEWON HA,


PUSHKAR RANADE, SHIYING XIONG, JEFFREY BOKOR, FELLOW, IEEE,
CHENMING HU, FELLOW, IEEE, AND TSU-JAE KING, SENIOR MEMBER, IEEE

Invited Paper

Silicon-based CMOS technology can be scaled well into the


nanometer regime. High-performance, planar, ultrathin-body
devices fabricated on silicon-on-insulator substrates have been
demonstrated down to 15-nm gate lengths. We have also intro-
duced the FinFET, a double-gate device structure that is relatively
simple to fabricate and can be scaled to gate lengths below 10
nm. In this paper, some of the key elements of these technologies
are described, including sublithographic patterning, the effects
of crystal orientation and roughness on carrier mobility, gate
work function engineering, circuit performance, and sensitivity to Fig. 1. Cross-sectional schematics of various MOSFET
process-induced variations. structures. (a) the classic bulk-Si structure. (b) UTB SOI structure.
(c) DG structure. The classic structure utilizes very heavy channel
Keywords—CMOS, FinFET, metal gate, molybdenum, doping (localized to “halo” regions near to the source/drain
MOSFET, nanotechnology, scaling, ultrathin body (UTB). junctions) to suppress subthreshold leakage current. This results in
degraded carrier mobility and ON current. The advanced structures
utilize a very thin channel (thickness T ) to suppress leakage
more effectively.
I. INTRODUCTION
Rapid advances in the semiconductor industry have led
to the proliferation of electronic devices and information
technology. Integrated circuits (ICs) based upon silicon being approached [1]. In the future, bulk-Si MOSFETs will
MOSFETs can perform functions such as computing, require high-permittivity (high- ) gate dielectrics and metal
signal processing, and information storage efficiently and gate electrodes, as well as low-resistance ultrashallow junc-
cheaply, and are, thus, used in virtually every electronic tions, in order to meet the stringent specifications of the Inter-
device produced today. Over the past three decades, by national Technology Roadmap for Semiconductors (ITRS)
reducing transistor gate lengths with each new generation [2]. Techniques such as semiconductor band-gap and strain
of manufacturing technology, steady improvements in engineering to improve device transconductance and on-state
circuit performance (speed) and cost per function have been current may also be required [3]. Advanced MOSFET struc-
achieved. However, continued transistor scaling will not be tures (Fig. 1) such as the ultrathin-body (UTB) silicon-on-in-
as straightforward in the future as it has been in the past sulator (SOI) single-gate transistor and the double-gate (DG)
because fundamental materials and process limits are rapidly transistor can be scaled more aggressively than the classic
bulk-Si structure [4], [5] and, hence, may be adapted for IC
production as early as the 65-nm technology node (25-nm
Manuscript received December 19, 2002; revised June 2, 2003. This physical gate length) [2]. However, these advanced structures
work was supported by the Semiconductor Research Corporation under
Contract 2000-NJ-850 and the Microelectronics Advanced Research
have distinctly different materials and process technology re-
Corporation under Contract 2001-MT-887. quirements and associated challenges.
L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, and T.-J. This paper begins by discussing the significant circuit per-
King are with the Electrical Engineering and Computer Sciences Depart-
ment, University of California, Berkeley, CA 94720 USA. formance advantages that advanced transistor structures can
C. Hu is with the Taiwan Semiconductor Manufacturing Corporation, provide. Metallic gate electrodes will be necessary in order
Hsin-chu, Taiwan 300, R.O.C., on leave from the Electrical Engineering for these devices to provide the maximum performance ben-
and Computer Science Department, University of California, Berkeley, CA
94720 USA. efit over bulk-Si MOSFETs; therefore, the development of
Digital Object Identifier 10.1109/JPROC.2003.818336 metal gate technology for fully depleted SOI CMOS devices

0018-9219/03$17.00 © 2003 IEEE

1860 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
is described. Design considerations, fabrication process de-
tails, and measured electrical characteristics are then pre-
sented in turn for the UTB and DG structures. Ultimate limits
for CMOS scaling are discussed, and practical consideration
is then given to the effects of process-induced variations on
transistor performance and their implications for manufac-
turing processes.

II. CIRCUIT PERFORMANCE ENHANCEMENT OF THIN-BODY


MOSFETS
While it may be possible to scale the traditional bulk
MOSFET device structure down into the 10-nm gate length

Fig. 2. DG maintains a 40% FO4 inverter delay improvement
over bulk devices. The UTB improvement disappears at small
regime [6], a heavy channel doping will likely be required L because of poor short-channel effect control in a 5-nm body,
to control short-channel effects. This presents a challenge especially in the PMOS. To meet leakage specifications, V must
therefore be extremely high.
in terms of device fabrication because a heavy halo implant
must be localized close to the surface underneath the gate
edge. However, even if this is achievable, it will likely Fig. 2 quantifies the benefits of DG and UTB devices
result in the degradation of device performance. Because in terms of inverter gate delay through simulation using
thin-body devices can control short-channel effects with realistic device structures based on ITRS specifications [2]
only intrinsic doping in the channel, significant performance for sub-50-nm gate length technology generations. Body
enhancements can be expected [7]. thickness requirements for each gate length are derived
In a bulk device with a heavily doped channel, carrier from scaling rules presented in [12] for DG devices; for
mobility will be severely degraded due to impurity scat- single-gate UTB devices, body thicknesses are assumed to
tering and an increased transverse electric field. Above a be half this value. Mixed-mode device simulation [13] is em-
concentration of 2 10 cm , mobility is expected to ployed using the energy balance model for carrier transport.
be noticeably affected by channel dopants [8]. In addition, Because the full Boltzmann equation is not solved, drain
significant depletion charge in the channel will form, thus current values may be overestimated [14], but the trends
increasing the average vertical field experienced by a carrier and differences between device technologies should still be
in the inversion layer and increasing the effects of phonon valid. Quantum effects, including carrier confinement due
and interface scattering [9]. Furthermore, this increased de- to body thickness scaling, which can increase the device
pletion charge will result in a larger depletion capacitance threshold voltage [15], and carrier scattering due to quantum
and subthreshold slope. As a result, for a given off-state charge transport, which may affect current distribution in
leakage current specification, the threshold voltage must the channel [16], are not considered.
be raised, thus reducing the on-state drive current. A large For DG and UTB devices, the enhancement in drive cur-
channel doping will also inevitably enhance band-to-band rent at a given off-state current specification leads directly
tunneling leakage between the body and drain [10]. This will to an improvement in inverter delay. An additional speedup
be especially important because abrupt halo doping profiles ( 5%–10%) results from the elimination of depletion and
in the channel are desirable to localize the heavy channel junction capacitances. As shown in Fig. 2, improvements in
doping whereas abrupt drain doping profiles are desirable fanout of four (FO4) inverter delay over bulk devices are
for the reduction of series resistance. Together, these effects in the 30%–40% range. The amount of improvement shown
will greatly increase band-to-band tunneling, which could here is smaller than that reported in [7] due primarily to the
eventually become the dominant off-state leakage mecha- realistic doping profiles used. Series resistance is, thus, con-
nism in the transistor. sidered in this work, which lessens the improvements associ-
In UTB and DG devices, short-channel effects are con- ated with the intrinsic device structure. For all technologies,
trolled by a thin silicon film, thus allowing for gate-length the DG device shows a larger enhancement over traditional
scaling down to the 10-nm regime [11] without the use of bulk-Si MOSFETs than the UTB case because of improved
channel dopants. With a lightly doped channel, DG and UTB short-channel effects. It is possible, however, that body thick-
devices have negligible depletion charge and capacitance, ness scaling may be limited to 5 nm [17]. In that case, UTB
which yields a steep subthreshold slope. DG devices show devices at 25-nm gate lengths and below, which need body
even better subthreshold slope than their UTB counterparts thicknesses below 5 nm to adequately control short-channel
due to better short-channel effect control by the DG structure. effects, can show severely degraded device performance.
Lower transverse electric field and negligible impurity scat- Because DG and UTB devices exhibit better short-channel
tering contribute to increased mobility that further improves effects, which become more important at small gate lengths,
the drive current in both devices. With respect to circuit per- it could be expected that the delay improvement should
formance, DG and UTB devices provide an additional advan- increase with technology scaling. However, the value stays
tage in that the capacitive load is decreased by the elimination relatively constant with technology scaling following ITRS
of both depletion and junction capacitances. specifications because the roadmap allows a dramatic rise

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1861


Fig. 4. Because metal gate work function engineering is difficult,
Fig. 3. V can be lowered in thin-body devices to reduce energy V adjustment in thin-body devices may need to be accomplished
consumption per transition. When the delay is matched to that of through channel doping or the asymmetric DG structure. Both

bulk, a reduction of up to 60% can be observed. As with delay, solutions degrade circuit performance, but could still provide slight
the UTB improvement disappears at small gate lengths if T is improvement over bulk. Threshold voltage adjustment in all cases
limited to 5 nm. was adjusted to meet roadmap specifications [2].

in the off-state leakage current specification based on the depletion effect, which increases the effective dielectric
expectations of bulk-Si MOSFET scaling. thickness, and dopant penetration through the dielectric,
Thin-body devices essentially improve the tradeoff be- which can degrade oxide reliability and shift the device
tween gate delay and energy consumption. Given a delay threshold voltage.
specification, the advantage of thin-body MOSFETs can Over the last few years, research in metal gate CMOS
be expressed in terms of energy consumption, since the technology has led to the identification of several candidate
power supply voltage can be reduced to match the delay metals for this application. Several high melting point re-
of a bulk-Si device. Since energy is a quadratic function fractory metals, e.g., W, Ti, Ta, Mo, Nb, Re, Ru, and their
of the power supply voltage, this can result in a dramatic binary or ternary metallic derivatives, e.g., WN, TiN, TaN,
improvement in energy. In this scenario, thin-body devices MoN, and TaSiN, have been investigated [19]–[24]. In the
can show up to a 60% reduction in energy consumption most straightforward case, two separate metals with appro-
(Fig. 3). priate work functions need to be used on a single Si substrate
Ideally, since channel dopants are not necessary in in order to obtain low and symmetric devices [25]. For
thin-body MOSFETs, threshold voltage adjustment is minimal process complexity, however, a method for tuning
achieved by gate work function engineering. However, the gate work function over the required range is highly de-
until suitable gate materials become available, alternative sirable. Such a tunable work function gate CMOS technology
methods of controlling the threshold voltage may need to is attractive for bulk-Si and SOI-CMOS devices alike.
be used [11]. The use of channel dopants is one solution to From an integration perspective, ion implantation, whether
control the threshold voltage; however, this brings problems by structural or chemical modification of the gate material, is
with reduced mobility and random dopant fluctuations [18]. the simplest method by which to achieve a tunable gate work
An asymmetric DG structure can also achieve an appropriate function technology. There have been several reports on the
threshold voltage by using n and p polysilicon gates in use of ion implantation to change the work function of thin
the DG device; this is, however, at the cost of increased metal films [19], [26]–[28]. Molybdenum (Mo) is an attrac-
tive candidate for this application given the strong crystalline
transverse electric field, since a built-in potential exists
anisotropy of its work function [29]. Such anisotropy is gen-
through the body due to the asymmetric gate work func-
erally displayed by most metals and is believed to arise from
tions. As a result, both channel doping and an asymmetric
differences in interatomic spacing and atom plane smooth-
DG result in degraded device performance (Fig. 4). This
ness with crystal orientation [30]. Mo is particularly attrac-
emphasizes the need for gate work function engineering as
tive given its compatibility with Si CMOS processing, as it
alternative solutions can negate the performance benefits of
can be deposited by physical vapor deposition (PVD) and
thin-body devices.
chemical vapor deposition (CVD), can be etched by conven-
tional reactive ion etching (RIE) chemistry, and is thermody-
III. METAL GATE CMOS TECHNOLOGY
namically stable on SiO . It has been shown that a high-dose
For thin-body transistors with undoped channels, gate Ar ion implant can selectively amorphize thin Mo films, thus
work functions must be chosen such that the gate Fermi level leading to a significant lowering of the work function [26].
falls between 0.2 V of (intrinsic Si Fermi level) Unfortunately, such a purely structural change is seldom per-
[11]. These work function values are needed for low and manent, and crystallization upon high-temperature annealing
complementary CMOSFET devices. This requirement restores the work function to the unimplanted value. Never-
precludes the use of doped poly-Si as the gate electrode. theless, the possibility of locking in amorphous metal states
Metallic materials are, thus, likely to replace poly-Si for is still a possibility through the simultaneous modification
this application beyond the ITRS 45-nm node. Metal gate of film chemistry (e.g., implanting another element, e.g., Si,
materials also eliminate problems associated with the gate along with Ar).

1862 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Fig. 6. Cross-sectional transmission electron microscopy (TEM)
Fig. 5. Variation of Mo work function with thermal annealing. of a 3-nm UTB MOSFET.
All anneals were 15 min long except for the 900 C anneal (15 s).

interfacial metal work functions are dependent on the per-


An alternative approach to changing the Mo work func-
mittivity of the gate dielectric [33].
tion is through selective changes in the film chemistry.
Thus, while the potential benefits of metal gate electrodes
Nitrogen implantation has been shown to be an effective
can be fairly significant, the task of metal selection and
way to nitridize the Mo film and controllably lower its work
process integration is far from trivial and is likely to need
function [26]. As shown in Fig. 5, the Mo work function
major research and development efforts in the coming years.
is dependent on the N implant dose and energy. Chem-
ical changes like nitridation are permanent and continue to
IV. ULTRATHIN BODY SINGLE-GATE MOSFET
evolve with temperature. The Mo work function after N
implantation becomes progressively lower with increasing In this section, we review recent work in our group on
annealing temperature and tends to stabilize between 800 C the development of the UTB single-gate MOSFET device
and 900 C. The range of work functions obtained makes structure. Fig. 6 shows a transmission electron micrograph
this approach attractive for FDSOI-CMOS applications. The depicting a cross-sectional view of a UTB ( 30 nm,
next two sections will illustrate the application of this ap- 3 nm) single-gate MOSFET. The detailed fabrication
proach to both UTB (UTBFET) and FinFET fabrication. processes, which are fully compatible with conventional bulk
It is important to evaluate the effects of potential chan- CMOS processes, have been previously reported in [34].
neling of the N ions into the gate dielectric and the subsequent Fig. 7 shows measured electrical characteristics for an 80-nm
impact on dielectric reliability. In this context, the use of gate length UTB n-channel MOSFET 20 nm
thin Mo films and low implant energies is beneficial in and a 30-nm gate length UTB p-channel MOSFET
ensuring tight implant straggles and relatively high atomic 4 nm , each with a 2.1-nm gate oxide. High drive
fractions of N in the Mo film. The thin Mo films can current—750 A m for NMOS and 400 A m for
then be capped with poly-Si so that while the of the PMOS at a 1.0 V gate overdrive V —was achieved
device is determined by the metal work function, the bulk while short-channel effects are well suppressed.
of the gate electrode is made of doped Si to be more com- For UTB MOSFETs, short-channel effects are strongly
patible with subsequent processing steps (e.g., gate etch dependent on the body thickness , and can be evaluated
and self-aligned source/drain dopant implants). Recently, by the ratio of the gate length to the body thickness .
the use of large angled implants has also been shown to Fig. 8 shows the measured subthreshold swing (S) and
lower the ion channeling effect [31]. Yet another way to drain-induced barrier lowering (DIBL) across a large sample
introduce N into thin Mo films with minimal damage to of devices with gate lengths ranging from 30 to 190 nm
the underlying dielectric is to use a solid sacrificial source and body thicknesses from 4 to 8 nm. Short-channel effects
for N, e.g., N rich TiN. It was recently shown that Mo are sufficiently suppressed when the ratio between the two
films capped with nitrogen-rich TiN can act as sinks for device dimensions is larger than 4. This criterion
the excess N upon high temperature annealing [32]. The holds for the measured experimental devices, which have
N diffusing into the Mo film segregates at the dielectric a relatively thick gate oxide (2.1 nm) and low channel
interface and serves to change the gate work function. This doping; the value may be further reduced by scaling the
is an attractive technique and can also be used with other gate-oxide thickness or an increase in the channel doping
metals and diffusion sources. concentration.
Finally, it should be emphasized that the search for ad- As discussed in the previous section, metal gate work func-
vanced gate dielectrics needs to be carried out in tandem with tion engineering is necessary to control the threshold voltage
that for alternative gate dielectric materials, since it is quite of UTB MOSFETs. Fig. 9 shows the measured subthreshold
likely that aggressively scaled CMOS devices will employ characteristics for 300-nm gate length UTB PMOS-
high-permittivity gate dielectrics instead of the conventional FETs 15 nm using pure and nitrogen-implanted Mo
SiO -based gate dielectrics [5]. It was recently shown that gate [27]. The measured Mo-gated PMOS threshold voltage

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1863


Measured electrical characteristics for UTB n-channel MOSFET (L = 80 nm,
Fig. 7.
T = 20 nm) and p-channel MOSFET (L = 30 nm, T = 4 nm) with 2.1-nm-thick gate oxide.

limit transistor drive currents [35]–[37]. By using selective


deposition, a raised source/drain structure can be created
to reduce the parasitic resistance. One drawback of this
structure, however, is that it inevitably results in increased
overlap capacitance. Thus, spacer widths between the gates
and raised source/drain should be optimized [38]. Several
methods have been demonstrated, including selective silicon
epitaxial growth [36], selective silicon–germanium (SiGe)
epitaxial growth [39], and selective germanium (Ge) depo-
sition [40]. Among these approaches, germanium carries
additional benefits in higher dopant solid solubility, which
Fig. 8. Measured subthreshold swing (S) and DIBL
can further reduce parasitic resistance, and lower thermal
(30 nm <L < 190 nm, and 4 nm <T < 8 nm). The budget for dopant activation, which is promising for high-
L =T
short-channel effects can be evaluated by . All devices have dielectric integration. While traditional silicides cannot be
a nominal gate-oxide thickness of 2.1 nm.
formed when selective Ge is used, promising results on the
formation of metal germanides have been obtained [41],
[42], which could further reduce the series resistance.
High-performance UTB device technologies have also
been reported by other research groups [37], [43], [44]
(Table 1). In [37], gate lengths down to 6 nm were achieved
by the introduction of an ultrathin gate dielectric and strong
halo implant, which can further improve the control of
short-channel effects.

V. DOUBLE-GATE FINFET
The DG device is electrostatically more robust than a
single-gate UTB MOSFET because two gates are used
to control the channel from both sides, thus allowing for
additional gate length scaling by at least a factor of two.
The addition of a second gate electrode not only halves the
effect body thickness of the device, but also eliminates pen-
Fig. 9. Measured subthreshold I 0V characteristics for UTB etration of the drain electric field through the buried oxide,
p-channel MOSFETs using pure and nitrogen-implanted Mo gate.
The Vof UTB MOSFETs can be effectively adjusted via gate which improves gate control of the channel. In the past,
work function engineering. numerous methods have been proposed and demonstrated
to fabricate DG devices [45]–[49]; however, many suffer
is 0.2 V, and shifts by approximately 65 mV for every from process complexity. A more practical DG structure,
10 cm increment in the N implant dose. the FinFET, was, thus, proposed [50], [51]. In this device,
In the UTB device structure, the body thickness should the gate straddles a thin, fin-shaped body, which forms
be as thin as possible for ultimate scalability; however, two self-aligned channels along the sidewalls of the fin.
the series resistance of the source and drain regions could This original FinFET structure, however, still required a

1864 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Table 1
Performance Comparison of Published UTB MOSFETs

deposited over a silicon fin to form perfectly aligned gates


along the fin sidewalls.
The fin width is the most important process variable
because it determines the body thickness, which governs
short-channel effects. The off-state leakage current density
increases dramatically as the fin width increased because
gate control of the channel is worsened [11]. Channel
mobility [56] and threshold voltage [40], [57] can also be
sensitive to this dimension. It is, thus, important to achieve
small and controllable dimensions for the fin width. This can
be accomplished using optical or electron beam lithography,
but both inevitably lead to critical dimension (CD) variation
and line edge roughness. A key issue for the FinFET is that
adequate suppression of short-channel effects requires that
the fin width be approximately half of the gate length
[11], [50] such that a sublithographic patterning technology
is needed for fin formation. This is a clear departure from
historic device scaling in the gate length is at the limit of
Fig. 10. Schematic diagram, SEM, and TEM photographs of lithographic capabilities.
FinFET. (a) Schematic diagram after gate patterning. (b) Top view We have explored two sublithographic patterning tech-
of SEM photograph showing 10-nm fin width and 20-nm gate
length after gate patterning. (c) Cross-sectional TEM photograph of nologies: photoresist ashing followed by oxide hard mask
10-nm fin (x-x direction). (d) Cross-sectional TEM photograph trimming and spacer lithography (Fig. 11). Photoresist
(z-z direction) showing selectiveGe raised source/drain. ashing by oxygen plasma can be used to reduce the size of
resist patterns defined by lithography. Further size reduction
complicated fabrication process and resulted in a large can be achieved by additional hard mask oxide trimming
overlap capacitance between the gate and source and drain in HF. A combination of ashing and trimming can be used
regions. A simpler, more manufacturable process similar to reduce 500-nm line widths down to below 20 nm [58].
to conventional SOI CMOS processes was then developed Spacer lithography involves the use of a sacrificial layer
to create a quasi-planar FinFET structure (Fig. 10) with and a spacer layer [58]–[60]. Sacrificial layers to support
significantly less gate-to-source/drain overlap capacitance the spacers are initially defined by conventional lithography
[12], [52]–[55]. The FinFET uses a single-gate material and plasma etching. Then, a second thin layer is deposited

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1865


Fig. 11. Sublithographic patterning technology: photoresist ashing-hard mask oxide trimming
technique and spacer lithography. (a)–(d) Process flows of ashing-trimming from 500-nm initial line
width to sub-20 nm. (e) Minimum-sized features are defined by thin film deposited by CVD. The
spacer lithography doubles pattern density within a given pitch.

by CVD and etched back to form spacers. After removal of


the sacrificial structures, these spacers are used as an etch
mask to transfer the pattern to the substrate by an anisotropic
plasma etch. With this process, minimum-sized features as
small as 7 nm can be defined [60], [61]. Another feature of
spacer lithography is that it can double the pattern density
achievable by lithography. This is important in the FinFET
structure because in order to obtain higher drive current
multiple fins must be placed parallel—all straddled by a
single-gate line [7]. The achievable fin pitch, thus, deter-
mines the amount of layout area required for a device. To
further decrease line pitch, this spacer lithography process
can be repeated, effectively doubling the line density with
each successive iteration (Figs. 11 and 12).
As with single-gate UTB MOSFETs, additional FinFET
technological challenges include threshold voltage control
Fig. 12. Multiplication of pattern density by spacer lithography.
and parasitic source/drain resistance. We have integrated ni- (a) After patterning sacrificial poly-Si layer. (b) After
trogen-implanted Mo gate technology [62] and selective ger- low-temperature oxide (LTO) deposition, LTO spacer etch by CF
manium deposition for raised source/drain formation [53]. plasma, and removal of sacrificial poly-Si by KOH . (c) After
poly-Si deposition, poly-Si spacer etch by Cl and HBr , and
Due to their vertical nature, FinFET devices lie in the removal of LTO by HF . (d) After LTO deposition, LTO spacer etch
(110) plane when oriented parallel and perpendicular to the by CF plasma, and removal of sacrificial poly-Si by KOH . As
wafer flat of a standard (100) wafer (Fig. 13). As compared an etch stop, nitride was deposited before any spacer lithography
steps. Eight (= 2 ) lines were generated after repeating the spacer
with (100) silicon surfaces, hole mobility is enhanced while lithography process three times. As shown in (d), the final line
electron mobility is degraded in (110) surfaces [63]. These width and space was 70 nm and 80 nm, respectively.

1866 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
source/drain and metal silicide, the performance of DG
MOSFETs can exceed that of traditional bulk-Si MOSFETs.

VI. SCALING LIMITS


While MOSFET gate length scaling can be extended with
the UTB and DG device structures, an ultimate limit will
eventually be reached. For digital circuit applications, this
limit will be determined by the ability to maintain proper
transistor operation—namely that an ultimately scaled de-
vice must have the capability to be turned both on and off.
Fig. 13. Crystal orientation of NMOS and PMOS FinFETs. With scaling of transistor gate lengths, the primary difficulty
PMOS FinFETs are parallel or perpendicular to the flat zone, which lies in control of the off-state leakage current, which, if not
situates the channel in the (110) plane. NMOS FinFETs can be
rotated by 45 in order to use the (100) plane.
properly controlled, can be greatly increased by DIBL in the
channel of the device. By quantifying the off-state leakage
current for the DG MOSFET structure, an estimate of its
trends are consistent with previous reports of FinFET
scaling limit can be obtained. This structure has been shown
dependence on crystal orientation [12]. These anisotropy
to be the most scalable transistor design due to its dual-gate
effects become even more important in trigate [64] or
nature, in which the two gate electrodes provide significant
gate-all-around devices [65]. To simultaneously achieve
control of the channel. Thus, evaluation of the scaling limit
high NMOS and PMOS drive currents, a (100) sidewall
of the DG structure can be an estimate of the scaling limit of
surface for NMOS and (110) sidewall surface for PMOS is traditional silicon MOSFETs.
desirable. One way to implement these two different crystal
At very small channel lengths, carrier scattering can be
orientations is to align silicon fins to be perpendicular or ignored because ballistic transport will occur in the channel.
parallel to the flat zone of a (100) wafer for PMOS and Under this assumption, the off-state leakage current of a
at a 45 rotation for NMOS as shown in Fig. 13. Such a MOSFET will be composed of three major mechanisms:
scheme, which may incur a small area penalty, will depend thermionic emission above the channel potential barrier,
on lithographic capabilities. band-to-band tunneling between the body and drain p-n
Using electron beam lithography, CMOS FinFETs down junction, and quantum mechanical tunneling directly
to below sub-20 nm in gate length ( 20 nm, between the source and drain. Thermionic emission is
10 nm, 2.1 nm) have been fabricated. For these de- primarily controlled by the channel potential barrier height,
vices, NMOS drive current is 365 A m and PMOS drive which is determined by the degree of short-channel effect
current is 270 A m at V V and V V control in the device structure. Band-to-band tunneling is
(Fig. 14). The drive current is normalized with twice the fin governed by the electric field across the body/drain junction,
height [ in Fig. 10(a)]. The relatively low NMOS cur- which depends upon the gradient of the source/drain doping
rent is likely caused by the low electron mobility in the (110) profiles as well as the applied drain voltage (in the worst
surface and by fin sidewall roughness. Furthermore, a raised case, the supply voltage). Direct tunneling of carriers from
source/drain was not used for these devices. The drive cur- the source to drain may occur at extremely small gate
rent could be increased by 28% with a selectively deposited lengths because the channel potential barrier width is very
raised Ge source/drain [53]. small. In this analysis, tunneling leakage current through the
FinFET short-channel characteristics are shown in gate dielectric is ignored. Under the assumption that high-
Fig. 15(a)–(c). Threshold voltage rolloff is improved as the dielectric materials will become available, we investigate
fin width is decreased [Fig. 15(a)]. Saturation subthreshold only those drain leakage current mechanisms that cannot be
swing at V V and DIBL at nA m were avoided.
measured for gate lengths ranging from 20 nm to 150 nm By calculating these three leakage current components,
and fin widths from 10 nm to 42 nm. When the ratio of the the off-state leakage can be estimated for the DG MOSFET
gate length to the fin width is larger than 1.5, (Fig. 16). Scaling of the gate length results in increased
the subthreshold slope and DIBL are below 100 mV/dec leakage current because gate control of the channel is
and 0.1 V/V, respectively, for NMOS and PMOS devices reduced, thus allowing for increased DIBL. This reduces the
[Fig. 15(b), (c)]. PMOS devices show somewhat worse barrier height of the channel potential barrier, thus enhancing
short-channel effects because boron diffusivity is higher the thermionic emission, the dominant leakage component.
than that of phosphorus, which results in a smaller Scaling of the body thickness, however, eliminates leakage
after rapid thermal annealing for source/drain activation. An paths that are not well controlled by the gate—those that
added benefit of DG FinFETs is that they show extremely are physically far from the gate electrode. As a result,
low gate-induced drain leakage (GIDL) current as shown in short-channel effects are minimized at small gate lengths,
Fig. 15(d) [66]. thus reducing leakage by thermionic emission.
The device performance of published DG FinFETs The scaling limit of DG MOSFETs is, thus, a strong
are summarized in Table 2. With an appropriate raised function of the body thickness. Previous work has suggested

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1867


Fig. 14. FinFET I-V characteristics. Device dimensions are L = 20 nm, W = 10 nm, and
T =2.1 nm.

Fig. 15. FinFET short-channel effects and GIDL. (a) Threshold voltage rolloff versus L .
(b) Subthreshold swing versus L =W . (c) DIBL versus L =W . (d) GIDL current. The
fabricated FinFET devices show very low GIDL current, which decreases as the fin width is reduced.

that the minimum acceptable body thickness for a thin-body scaling limit for DG MOSFETs can be obtained under
MOSFET will be 5 nm [17]. This is because the series the assumption that body thicknesses cannot be scaled
resistance in the source and drain regions introduced by below 5 nm. With the additional assumption that equivalent
such a thin film may become unacceptable even with oxide thickness scaling will be limited to 1 nm (due to
the incorporation of a raised source/drain technology. In gate leakage current—even with alternative gate dielectric
addition, quantum confinement in the thin body may cause materials), off-state leakage current targets can be met at
an intolerable shift in the device threshold voltage. Fur- gate lengths down to 10 nm [11]. This scaling limit is
thermore, quantum confinement effects could also impact also dependent upon the choice of threshold voltage and
charge scattering and transport in the on-state [16], which the lateral source/drain doping gradient. The value of the
may present a practical limit to device scaling. Thus, a scaling limit based upon off-state leakage criteria becomes

1868 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Table 2
Performance Comparison of Published FinFETs

for both NMOS and PMOS. The results (Table 3) show


that process variation can be tolerable, as the deviation in
electrical parameters is comparable to current values seen in
the industry today.
The device threshold voltage fluctuates significantly
with fin width variation due to changes in the degree of
short-channel effect control ( rolloff) and quantum
confinement effects. The combined effects result in NMOS
V (extracted at low drain bias) variation of 16 mV for
every nanometer change in body thickness while V
(extracted at high drain bias) variation is slightly higher
(33 mV/nm) due to DIBL; PMOS values are similar. Gate
length and oxide thickness variation have a significantly
weaker effect on the threshold voltage because only the
Fig. 16. DIBL improves as the body thickness is reduced, short-channel effect is modulated. Using the drift-diffusion
thus lowering off-state leakage current. At a body thickness of model for carrier transport (nonequilibrium and quantum
5 nm, a 10-nm gate length DG MOSFET can meet an off-state charge transport effects are, thus, ignored), only a moderate
leakage current target of 160 nA=m. The above data assumes a
1-nm/decade lateral source/drain doping gradient, a long-channel dependence of the drive current on the body thickness was
threshold voltage of 0.2 V, and a power supply of 0.6 V. observed. A dramatic change in the off-state current ( 5
per nm around 5 nm) is seen due to the exponential
smaller as the body thickness and equivalent oxide thickness dependence of on the threshold voltage.
are decreased, but is raised by an abrupt source/drain doping Using these simulation results, a statistical calculation of
profile and a low threshold voltage. the values of each electrical parameter was performed.
The contributions of each of the physical parameters are as-
VII. THE EFFECTS OF PROCESS VARIATIONS sumed to be independent. Threshold voltage variation is in
the range of 40 mV while drive current variation is within
Ultimately, scaling of DG MOSFETs may be limited by
8% 10%. The subthreshold swing is 68 6 mV for NMOS
process controllability. Because the FinFET is a vertical
and 70 6 mV for PMOS. The highest leakage is five times
structure, the fin width is susceptible to line width variation
larger than that of the nominal device. Based on these results,
and line edge roughness effects. Furthermore, gate oxidation
with reasonable assumptions for process variation (
may be affected by sidewall roughness of the fin. We have,
1 nm, 2 nm, and ), device param-
thus, studied the sensitivity of several important device pa-
eter fluctuations can be kept within reason.
rameters to process variation using device simulation [67].
As a specific example, we choose a nominal device with a
VIII. CONCLUSION
20-nm gate length, 5-nm fin width, and 1.0-nm gate-oxide
thickness. The device is assumed to be ideal—with a ad- Advanced MOSFET structures such as the UTB SOI
justable work function metal gate and small spacer widths MOSFET and the DG MOSFET show promise for scaling
(parasitic source/drain series resistance is not significant). CMOS technology to gate lengths below 10 nm to enable
The device is designed for low power application according continued improvements in IC cost and performance (e.g.,
to the ITRS roadmap [2] with off-state current of 1 nA m THz operating frequencies) for at least 15 more years. Their

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1869


Table 3
3  Values of Parameter Variation in FinFET Devices. In Each Case, Two Numbers Are Given: The
First Is for NMOS and the Second for PMOS Devices. Nominal Device Parameters aAre:
L = 20 nm, W = 5 nm, T = 1 nm, N = 10 cm , I = 1 nA=m, and Source
2
Drain Doping Profiles With a Peak of 2 10 cm With a 2-nm/dec Gaussian Lateral Decay

performance benefit is maximized by using a lightly doped also be taken to remove etch damage and to smoothen the Si
(or undoped) channel to achieve high carrier mobilities. fin sidewalls, as well as to orient the fin channel surfaces in
The use of a lightly doped body requires that the gate order to achieve high drive current.
work function be tunable in the range 4.4 eV to 5.0 eV For very short gate lengths, the body can be so thin
to provide a means for adjusting the transistor threshold that quantum confinement effects become significant. At
voltage. Molybdenum is an attractive candidate for gate- 5 nm, is very sensitive to variations in body thick-
electrode application because of its compatibility with CMOS ness—more so than to variations in . Since can be
processing, and its high work function ( 5 eV) makes it twice as thick for the DG MOSFET as compared to the UTB
ideal as a gate material for lightly doped p-channel UTB and MOSFET (for a given ), the DG MOSFET will be more
DG MOSFETs. The work function of molybdenum can be tolerant of process-induced variations for sub-20-nm gate
lowered to 4.4 eV in a controllable manner by low-energy lengths and, hence, will ultimately be more manufacturable.
nitrogen implantation followed by thermal annealing, which
makes it suitable as a gate material for n-channel UTB and
DG MOSFETs as well. The capability to achieve multiple ACKNOWLEDGMENT
values by selectively adjusting the implant dose is important The authors would like to thank the University of Cali-
because it enables optimization for high-performance versus fornia, Berkeley, Microlab staff for their support in device
low-power applications without the need for any channel fabrication.
doping.
UTB SOI MOSFETs with body thicknesses down to 3 nm
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[65] J. Colinge, M. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, Berkeley, in 1998 and 2002, respectively.
“Silicon-on-insulator ‘gate all-around device’,” in Int. Electron De- In 2002, he was with IBM Corporation’s T.J.
vices Meeting, 1990, pp. 595–598. Watson Research Center, Yorktown Heights,
[66] Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, “Reduction of gate- NY. He is currently with Intel Corporation,
induced drain leakage (GIDL) current in single-gate ultra-thin body Hillsboro, OR. He has authored or coauthored
and double-gate FinFET devices,” in Proc. Solid State Devices and over 30 scientific publications and has three
Materials, 2002, pp. 140–141. U.S. patents pending. His doctoral research was in the area of sub-100-nm
[67] ISE TCAD: DESSIS, v7.0 User’s Manual, Integrated Systems Engi- MOS transistor design and fabrication and involved the integration of novel
neering, Inc., San Jose, CA, 2001. gate stack materials and processes and ultrashallow junction fabrication
techniques.

Leland Chang (Student Member, IEEE) re-


ceived the B.S. (highest honors) M.S., and Ph.D.
degrees in electrical engineering and computer
sciences in 1999, 2001, and 2003, respectively,
from the University of California, Berkeley. Shiying Xiong received the M.S. degree in
He is with the Electrical Engineering and physics from Tsinghua University, P. R. China,
Computer Science Department, University of in 1998. He is currently working toward the
California, Berkeley, CA. His research interests Ph.D. degree in solid-state devices in the Depart-
include the fabrication and analysis of thin-body ment of Electrical Engineering and Computer
SOI MOSFETs, nonvolatile memory devices, Sciences, University of California, Berkeley.
and RF MEMS resonators.
Dr. Chang received the National Defense Science and Engineering Grad-
uate (NDSEG) Fellowship from the Department of Defense in 1999 and the
IBM Ph.D. Fellowship in 2002.

1872 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Jeffrey Bokor (Fellow, IEEE) received the B.S. Tsu-Jae King (Senior Member, IEEE) received
degree in electrical engineering from the Massa- the B.S., M.S., and Ph.D. degrees in electrical
chusetts Institute of Technology in 1975 and the engineering from Stanford University, Stanford,
M.S. and Ph.D. degrees in electrical engineering CA, in 1984, 1986, and 1994, respectively.
from Stanford University in 1976 and 1980, re- Her research involved the seminal study of
spectively. polycrystalline silicon–germanium films and
From 1980 to 1993, he was with AT&T their applications in metal–oxide–semiconductor
Bell Laboratories, Holmdel, NJ, where he did technologies.
research on novel sources of ultraviolet and soft From 1992 to 1996, she was a Member
X-ray coherent radiation, advanced lithography, of Research Staff with the Xerox Palo Alto
picosecond optoelectronics, semiconductor Research Center, Palo Alto, CA, researching
physics, surface physics, MOS device physics, and integrated circuit and developing polycrystalline–silicon thin-film transistor technologies
process technology. From 1987 to 1990, he was Head of the Laser Science for high-performance flat-panel display and imaging applications. She is
Research Department at Bell Labs. From 1990 to 1993, he was Head of currently an Associate Professor of Electrical Engineering and Computer
the ULSI Technology Research Department, Bell Labs, Murray Hill, NJ. Sciences, University of California, Berkeley, and the Director of the
Since 1993, he has been Professor of Electrical Engineering and Computer University of California, Berkeley, Microfabrication Laboratory. She
Sciences at the University of California, Berkeley, with a joint appointment has authored or coauthored over 150 publications and holds six U.S.
at the Lawrence Berkeley National Laboratory, Berkeley, CA. His current patents. Her research activities are presently in sub-50-nm Si devices and
research activities include extreme ultraviolet lithography, nanoscale technology, and thin-film materials and devices for integrated microsystems
MOSFET device technology, novel techniques for nanofabrication, and and large-area electronics.
new devices for nanoelectronics.
Dr. Bokor is a Fellow of the American Physical Society and the Optical
Society of America.

Chenming Hu (Fellow, IEEE) received the B.S.


degree from the National Taiwan University,
Taipei, Taiwan, R.O.C., in 1968 and the M.S.
and Ph.D. degrees in electrical engineering from
the University of California, Berkeley, in 1970
and 1973, respectively.
He is the CTO of the Taiwan Semiconductor
Manufacturing Corporation, Hsinchu, Taiwan,
R.O.C., on leave from the University of Cali-
fornia, Berkeley. He has authored or coauthored
five books and over 700 research papers. He is a
Member of the editorial boards of the Journal of Semiconductor Science
and Technology and the Journal of Microelectronics Reliability.
Dr. Hu received the 2002 IEEE Solid State Circuits Award for leading the
development of the industry standard MOSFET model for IC simulation,
BSIM. He also received the 1997 IEEE Jack A. Morton Award for contri-
butions to the physics of MOSFET reliability. He is a Member of the U.S.
National Academy of Engineering, a Fellow of the Institute of Physics, and
a Life Honorary Professor of the Chinese Academy of Science. He has re-
ceived the University of California, Berkeley’s highest honor for teaching,
the Distinguished Teaching Award; the Monie A. Ferst Award of Sigma Xi;
the W. Y. Pan Foundation Award; and the DARPA Most Significant Tech-
nological Accomplishment Award for codeveloping the FinFET transistor
structure.

CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1873

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