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1860 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
is described. Design considerations, fabrication process de-
tails, and measured electrical characteristics are then pre-
sented in turn for the UTB and DG structures. Ultimate limits
for CMOS scaling are discussed, and practical consideration
is then given to the effects of process-induced variations on
transistor performance and their implications for manufac-
turing processes.
in the off-state leakage current specification based on the depletion effect, which increases the effective dielectric
expectations of bulk-Si MOSFET scaling. thickness, and dopant penetration through the dielectric,
Thin-body devices essentially improve the tradeoff be- which can degrade oxide reliability and shift the device
tween gate delay and energy consumption. Given a delay threshold voltage.
specification, the advantage of thin-body MOSFETs can Over the last few years, research in metal gate CMOS
be expressed in terms of energy consumption, since the technology has led to the identification of several candidate
power supply voltage can be reduced to match the delay metals for this application. Several high melting point re-
of a bulk-Si device. Since energy is a quadratic function fractory metals, e.g., W, Ti, Ta, Mo, Nb, Re, Ru, and their
of the power supply voltage, this can result in a dramatic binary or ternary metallic derivatives, e.g., WN, TiN, TaN,
improvement in energy. In this scenario, thin-body devices MoN, and TaSiN, have been investigated [19]–[24]. In the
can show up to a 60% reduction in energy consumption most straightforward case, two separate metals with appro-
(Fig. 3). priate work functions need to be used on a single Si substrate
Ideally, since channel dopants are not necessary in in order to obtain low and symmetric devices [25]. For
thin-body MOSFETs, threshold voltage adjustment is minimal process complexity, however, a method for tuning
achieved by gate work function engineering. However, the gate work function over the required range is highly de-
until suitable gate materials become available, alternative sirable. Such a tunable work function gate CMOS technology
methods of controlling the threshold voltage may need to is attractive for bulk-Si and SOI-CMOS devices alike.
be used [11]. The use of channel dopants is one solution to From an integration perspective, ion implantation, whether
control the threshold voltage; however, this brings problems by structural or chemical modification of the gate material, is
with reduced mobility and random dopant fluctuations [18]. the simplest method by which to achieve a tunable gate work
An asymmetric DG structure can also achieve an appropriate function technology. There have been several reports on the
threshold voltage by using n and p polysilicon gates in use of ion implantation to change the work function of thin
the DG device; this is, however, at the cost of increased metal films [19], [26]–[28]. Molybdenum (Mo) is an attrac-
tive candidate for this application given the strong crystalline
transverse electric field, since a built-in potential exists
anisotropy of its work function [29]. Such anisotropy is gen-
through the body due to the asymmetric gate work func-
erally displayed by most metals and is believed to arise from
tions. As a result, both channel doping and an asymmetric
differences in interatomic spacing and atom plane smooth-
DG result in degraded device performance (Fig. 4). This
ness with crystal orientation [30]. Mo is particularly attrac-
emphasizes the need for gate work function engineering as
tive given its compatibility with Si CMOS processing, as it
alternative solutions can negate the performance benefits of
can be deposited by physical vapor deposition (PVD) and
thin-body devices.
chemical vapor deposition (CVD), can be etched by conven-
tional reactive ion etching (RIE) chemistry, and is thermody-
III. METAL GATE CMOS TECHNOLOGY
namically stable on SiO . It has been shown that a high-dose
For thin-body transistors with undoped channels, gate Ar ion implant can selectively amorphize thin Mo films, thus
work functions must be chosen such that the gate Fermi level leading to a significant lowering of the work function [26].
falls between 0.2 V of (intrinsic Si Fermi level) Unfortunately, such a purely structural change is seldom per-
[11]. These work function values are needed for low and manent, and crystallization upon high-temperature annealing
complementary CMOSFET devices. This requirement restores the work function to the unimplanted value. Never-
precludes the use of doped poly-Si as the gate electrode. theless, the possibility of locking in amorphous metal states
Metallic materials are, thus, likely to replace poly-Si for is still a possibility through the simultaneous modification
this application beyond the ITRS 45-nm node. Metal gate of film chemistry (e.g., implanting another element, e.g., Si,
materials also eliminate problems associated with the gate along with Ar).
1862 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Fig. 6. Cross-sectional transmission electron microscopy (TEM)
Fig. 5. Variation of Mo work function with thermal annealing. of a 3-nm UTB MOSFET.
All anneals were 15 min long except for the 900 C anneal (15 s).
V. DOUBLE-GATE FINFET
The DG device is electrostatically more robust than a
single-gate UTB MOSFET because two gates are used
to control the channel from both sides, thus allowing for
additional gate length scaling by at least a factor of two.
The addition of a second gate electrode not only halves the
effect body thickness of the device, but also eliminates pen-
Fig. 9. Measured subthreshold I 0V characteristics for UTB etration of the drain electric field through the buried oxide,
p-channel MOSFETs using pure and nitrogen-implanted Mo gate.
The Vof UTB MOSFETs can be effectively adjusted via gate which improves gate control of the channel. In the past,
work function engineering. numerous methods have been proposed and demonstrated
to fabricate DG devices [45]–[49]; however, many suffer
is 0.2 V, and shifts by approximately 65 mV for every from process complexity. A more practical DG structure,
10 cm increment in the N implant dose. the FinFET, was, thus, proposed [50], [51]. In this device,
In the UTB device structure, the body thickness should the gate straddles a thin, fin-shaped body, which forms
be as thin as possible for ultimate scalability; however, two self-aligned channels along the sidewalls of the fin.
the series resistance of the source and drain regions could This original FinFET structure, however, still required a
1864 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Table 1
Performance Comparison of Published UTB MOSFETs
1866 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
source/drain and metal silicide, the performance of DG
MOSFETs can exceed that of traditional bulk-Si MOSFETs.
Fig. 15. FinFET short-channel effects and GIDL. (a) Threshold voltage rolloff versus L .
(b) Subthreshold swing versus L =W . (c) DIBL versus L =W . (d) GIDL current. The
fabricated FinFET devices show very low GIDL current, which decreases as the fin width is reduced.
that the minimum acceptable body thickness for a thin-body scaling limit for DG MOSFETs can be obtained under
MOSFET will be 5 nm [17]. This is because the series the assumption that body thicknesses cannot be scaled
resistance in the source and drain regions introduced by below 5 nm. With the additional assumption that equivalent
such a thin film may become unacceptable even with oxide thickness scaling will be limited to 1 nm (due to
the incorporation of a raised source/drain technology. In gate leakage current—even with alternative gate dielectric
addition, quantum confinement in the thin body may cause materials), off-state leakage current targets can be met at
an intolerable shift in the device threshold voltage. Fur- gate lengths down to 10 nm [11]. This scaling limit is
thermore, quantum confinement effects could also impact also dependent upon the choice of threshold voltage and
charge scattering and transport in the on-state [16], which the lateral source/drain doping gradient. The value of the
may present a practical limit to device scaling. Thus, a scaling limit based upon off-state leakage criteria becomes
1868 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Table 2
Performance Comparison of Published FinFETs
performance benefit is maximized by using a lightly doped also be taken to remove etch damage and to smoothen the Si
(or undoped) channel to achieve high carrier mobilities. fin sidewalls, as well as to orient the fin channel surfaces in
The use of a lightly doped body requires that the gate order to achieve high drive current.
work function be tunable in the range 4.4 eV to 5.0 eV For very short gate lengths, the body can be so thin
to provide a means for adjusting the transistor threshold that quantum confinement effects become significant. At
voltage. Molybdenum is an attractive candidate for gate- 5 nm, is very sensitive to variations in body thick-
electrode application because of its compatibility with CMOS ness—more so than to variations in . Since can be
processing, and its high work function ( 5 eV) makes it twice as thick for the DG MOSFET as compared to the UTB
ideal as a gate material for lightly doped p-channel UTB and MOSFET (for a given ), the DG MOSFET will be more
DG MOSFETs. The work function of molybdenum can be tolerant of process-induced variations for sub-20-nm gate
lowered to 4.4 eV in a controllable manner by low-energy lengths and, hence, will ultimately be more manufacturable.
nitrogen implantation followed by thermal annealing, which
makes it suitable as a gate material for n-channel UTB and
DG MOSFETs as well. The capability to achieve multiple ACKNOWLEDGMENT
values by selectively adjusting the implant dose is important The authors would like to thank the University of Cali-
because it enables optimization for high-performance versus fornia, Berkeley, Microlab staff for their support in device
low-power applications without the need for any channel fabrication.
doping.
UTB SOI MOSFETs with body thicknesses down to 3 nm
have been successfully demonstrated. It was found that short- REFERENCES
channel effects (reduction in with decreasing , and [1] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and
with increasing drain bias) are effectively suppressed if the H.-S. P. Wong, “Device scaling limits of Si MOSFET’s and their
thickness of the body is smaller than the gate length. application dependencies,” Proc. IEEE, vol. 89, pp. 259–288, Mar.
2001.
Excellent drive current can be achieved with a relatively thick [2] International Technology Roadmap for Semiconductors, 2001.
(2.1 nm) gate oxide, so long as parasitic source/drain resis- [3] J. Welser, J. Hoyt, S. Takagi, and J. F. Gibbons, “Strain dependence
tance is kept low by selectively thickening the source/drain of the performance enhancement in strained-Si n-MOSFETs,” in Int.
Electron Devices Meeting Tech. Dig., 1994, pp. 373–376.
contact regions. Mo gate work function engineering by ni- [4] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A compar-
trogen implantation was shown to be effective for tuning . ative study of advanced MOSFET concepts,” IEEE Trans. Electron
The FinFET offers the superior scalability of a DG Devices, vol. 43, pp. 1742–1753, Oct. 1996.
[5] H.-S. P. Wong, “Beyond the conventional transistor,” in IBM J. Res.
MOSFET structure together with a process flow and layout Develop., 2002, vol. 46, pp. 133–168.
similar to that of the conventional MOSFET. In order to [6] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, “15
effectively suppress short-channel effects, the width of the nm gate length planar CMOS transistor,” in Int. Electron Devices
Meeting Tech. Dig., 2001, pp. 937–939.
Si fin (i.e., the transistor body thickness) must be less than [7] S. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang,
half the gate length. Sublithographic fins (narrower than V. Subramanian, J. Bokor, T.-J. King, and C. Hu, “FinFET: a quasi-
any feature that can be defined by conventional lithography) planar double-gate MOSFET,” in 2001 IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, 2000, pp. 118–119.
can be formed in an SOI film by using spacers, formed [8] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi,
along the sidewalls of a sacrificial patterned layer, as a and M. Bohr, “Scaling challenges and device design requirements for
hard mask. Since the width of the spacers is determined by high performance sub-50 nm gate length planar CMOS transistors,”
in Symp. VLSI Technology Dig. Tech. Papers, 2000, pp. 174–175.
the thickness of the deposited spacer layer, it can be very [9] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality
narrow and uniform across a wafer. This spacer lithography of inversion layer mobility in Si MOSFET’s: part I—effects of sub-
process can be used to achieve very high fin densities for strate impurity concentration,” IEEE Trans. Electron Devices, vol.
41, pp. 2357–2362, Dec. 1994.
efficient layout of wide-channel FinFETs. Sub-20-nm [10] Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS design con-
FinFETs have been successfully demonstrated, with siderations,” in Int. Electron Devices Meeting Tech. Dig., 1998, pp.
tuning possible by using Mo gate technology. As with the 789–792.
[11] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, “Gate-length
UTB device, selective thickening of the source/drain contact scaling and threshold voltage control of double-gate MOSFETs,” in
regions is needed to reduce parasitic resistance. Care must Int. Electron Devices Meeting Tech. Dig., 2000, pp. 719–722.
1870 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
[12] J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, [32] R. J. P. Lander, J. C. Hooker, J. P. van Zijl, F. Roozeboom, M. P.
H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. M. Maas, Y. Tamminga, and R. A. M. Wolters, “A tunable metal
Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. gate work function using solid state diffusion of nitrogen,” in Proc.
E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, ESSDERC, 2002, pp. 103–106.
M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate [33] Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, “Effects of high- gate
and CMOS-compatible Vt asymmetric-gate FinFET devices,” in Int. dielectric materials on metal and silicon gate workfunctions,” IEEE
Electron Devices Meeting Tech. Dig., 2001, pp. 437–440. Electron Device Lett., vol. 23, pp. 342–344, June 2002.
[13] MEDICI v2000.2 User’s Manual, Avant! Corp., 2000. [34] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J.
[14] K. Banoo and M. S. Lundstrom, “Electron transport in a model Si Bokor, and C. Hu, “Ultra-thin body SOI MOSFET for deep-sub-
transistor,” Solid State Electron., vol. 44, no. 9, pp. 1689–1695, Sept. tenth micron era,” in Int. Electron Devices Meeting 1998 Tech. Dig.,
2000. 1999, pp. 919–921.
[15] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechan- [35] S.-D. Kim, C.-M. Park, and J. C. S. Woo, “Advanced model and
ical effects on the threshold voltage of ultrathin-SOI nMOSFETs,” analysis of series resistance for CMOS scaling into nanometer
IEEE Electron Device Lett., vol. 14, pp. 569–571, Dec. 1993. regime—part II quantitative analysis,” IEEE Trans. Electron
[16] S. E. Laux, A. Kumar, and M. V. Fischetti, “QDAME simulation of Devices, vol. 49, pp. 467–472, Mar 2002.
7.5 nm double-gate Si nFET’s with differing access geometries,” in [36] B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kava-
Int. Electron Devices Meeting Tech. Dig., 2002, pp. 715–718. lieros, A. Murthy, and R. Chau, “Transistor elements for 30 nm phys-
ical gate lengths and beyond,” Intel Tech. J., vol. 6, pp. 42–54, May
[17] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simula-
2002.
tion of a 30 nm dual-gate MOSFET: how short can Si go?,” in Int.
[37] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci,
Electron Devices Meeting Tech. Dig., 1992, pp. 553–556.
Z. Ren, F.-F. Jamin, L. Shi, W. Natzle, H.-J. Huang, J. Mezzapelle, A.
[18] D. A. Antoniadis, “MOSFET scalability limits and new frontier
Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H.-S. P.
devices,” in 2002 Symp. VLSI Technology Dig. Tech. Papers,
Wong, and W. Haensch, “Extreme scaling with ultra-thin Si channel
2002, pp. 2–5.
MOSFETs,” in Int. Electron Devices Meeting Tech. Dig., 2002, pp.
[19] R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, “An adjustable work
267–270.
function technology using Mo gate for CMOS devices,” IEEE Elec-
[38] S. Zimin, L. Litian, and L. Zhijian, “Optimization of MOSFET’s
tron Device Lett., vol. 23, pp. 49–51, Jan. 2002.
with polysilicon-elevated source/drain,” in Proc. 5th Int. Conf. Solid-
[20] S. B. Samavedam, H. H. Tseng, P. J. Tobin, J. Mogab, S. Dakshina-
State and Integrated Circuit Technology, 1998, pp. 188–189.
Murthy, L. B. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B.-Y.
[39] W. B. De Boer, D. Terpstra, and J. G. M. Van Berkum, “Selective
Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T.-Y. Luo, R. Garcia,
versus nonselective growth of Si and SiGe,” Mater. Sci. Eng., vol.
P. Abramowitz, M. Moosa, D. C. Gilmer, C. Hobbs, W. J. Taylor,
B67, pp. 46–52, 1999.
J. M. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, [40] Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, “Nanoscale ultrathin body
and M. Azrak, “Metal gate MOSFET’s with HfO gate dielectric,” PMOSFET’s with raised selective germanium source/drain,” IEEE
in 2002 Symp. VLSI Technology Dig. Tech. Papers, June 2002, pp. Electron Device Lett., vol. 22, pp. 447–448, Sept. 2001.
24–25. [41] S. P. Ashburn, M. C. Ozturk, G. Harris, and D. M. Maher, “Phase
[21] V. Misra, H. Zhong, and H. Lazar, “Electrical properties of Ru-based transitions during solid-state formation of cobalt germanide by rapid
alloy gate electrodes for dual metal gate Si-CMOS,” IEEE Electron thermal annealing,” J. Appl. Phys., vol. 74, no. 7, pp. 4455–4460,
Device Lett., vol. 23, pp. 354–356, June 2002. 1993.
[22] B.-Y. Tsui and C.-F. Huang, “Wide range work function modulation [42] S. P. Ashburn, M. C. Ozturk, J. J. Wortman, G. Harris, J. Honeycutt,
of binary alloys for MOSFET application,” IEEE Electron Device and D. M. Maher, “Formation of titanium and cobalt germanides on
Lett., vol. 24, pp. 153–155, Mar. 2003. Si(100) using rapid thermal processing,” J. Electron. Mater., vol. 21,
[23] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. no. 1, pp. 81–86, 1992.
Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, [43] R. Chau, J. Kavalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lion-
and K. Okumura, “High performance metal gate MOSFET’s fabri- berger, D. Barlage, R. Arghavani, B. Roberds, and M. Doczy, “A 50
cated by CMP for 0.1 m regime,” in Int. Electron Devices Meeting nm depleted-substrate CMOS transistor (DST),” in Int. Electron De-
Tech. Dig., 1998, p. 785. vices Meeting 1998 Tech. Dig., 2001, pp. 621–624.
[24] I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, “Dual work function [44] H. van Meer and K. De Meyer, “The spacer/replacer concept: a vi-
metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Elec- able route for sub-100 nm ultrathin-film fully-depleted SOI CMOS,”
tron Device Lett., vol. 23, pp. 200–202, Apr. 2002. IEEE Electron Device Lett., vol. 23, pp. 46–48, Jan. 2002.
[25] Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, [45] H.-S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J.
T.-J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, “Dual- Welser, “Nanoscale CMOS,” Proc. IEEE, vol. 87, pp. 537–570, Apr.
metal gate CMOS technology with ultra-thin silicon nitride gate di- 1999.
electric,” IEEE Electron Device Lett., vol. 22, pp. 227–229, May [46] S.-H. Oh, J. M. Hergenrother, T. Nigam, D. Monroe, F. P. Klemens,
2001. A. Kornblit, W. M. Mansfield, M. R. Baker, D. L. Barr, F. H. Bau-
[26] P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. mann, K. J. Bolan, T. Boone, N. A. Ciampa, R. A. Cirelli, D. J. Ea-
King, “Tunable work function molybdenum gate technology for glesham, E. J. Ferry, A. T. Fiory, J. Frackoviak, J. P. Garno, H. J.
FDSOI-CMOS,” in Int. Electron Devices Meeting Tech. Dig., Dec. Gossmann, J. L. Grazul, M. L. Green, S. J. Hillenius, R. W. Johnson,
2002, pp. 363–366. R. C. Keller, C. A. King, R. N. Kleiman, J. T.-C. Lee, J. F. Miner, M.
[27] D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King, and C. Hu, D. Morris, C. S. Rafferty, J. M. Rosamilia, K. Short, T. W. Sorsch,
“Ultra-thin body silicon-on-insulator (UTB-SOI) MOSFET with A. G. Timko, G. R. Weber, G. D. Wilk, and J. D. Plummer, “50 nm
metal gate work-function engineering for sub-70 nm technology vertical replacement gate (VRG) pMOSFETs,” in Int. Electron De-
node,” in Extended Abstracts 2002 Int. Conf. Solid State Devices vices Meeting Tech. Dig., 2000, pp. 65–68.
and Materials, 2002, pp. 782–783. [47] J.-H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D.
[28] H. Wakabayashi, Y. Saito, K. Takeuchi, T. Mogami, and T. Kunio, A. Antoniadis, “Super self-aligned double-gate (SSDG) MOSFET’s
“A dual-metal gate CMOS technology using nitrogen-concentration- utilizing oxidation rate difference and selective epitaxy,” in Int. Elec-
controlled TiNx film,” IEEE Trans. Electron Devices, vol. 48, pp. tron Devices Meeting Tech. Dig., 1999, pp. 71–74.
2363–2369, Oct. 2001. [48] H.-S. P. Wong, K. K. Chan, and Y. Taur, “Self-aligned (top and
[29] H. B. Michaelson, “The workfunction of the elements and its bottom) double-gate MOSFET with a 25 nm thick silicon channel,”
periodicity,” J. Appl. Physics, vol. 48, no. 11, pp. 4729–4733, in Int. Electron Devices Meeting Tech. Dig., 1997, pp. 427–430.
Nov. 1977. [49] T. Su, J. P. Denton, and G. W. Neudeck, “New planar self-aligned
[30] R. Smoluchowski, “Anisotropy of the electronic work function of double-gate fully-depleted p-MOSFET’s using epitaxial lateral
metals,” Phys. Rev., vol. 60, pp. 661–674, 1941. overgrowth (ELO) and selectively grown source/drain (S/D),” in
[31] T. Amada, N. Maeda, and K. Shibahara, “Degradation in a molyb- Proc. IEEE Int. SOI Conf., 2000, pp. 110–111.
denum gate MOS structure caused by N ion implantation for the [50] D. Hisamoto, T. Kaga, and E. Takeda, “Impact of the vertical SOI
work function control,” in Materials Research Society Symp. Proc., ‘DELTA’ structure on planar device technology,” IEEE Trans. Elec-
vol. 716, 2002, pp. B7.5.1–B7.5.6. tron Devices, vol. 38, pp. 1419–1424, June 1991.
1872 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003
Jeffrey Bokor (Fellow, IEEE) received the B.S. Tsu-Jae King (Senior Member, IEEE) received
degree in electrical engineering from the Massa- the B.S., M.S., and Ph.D. degrees in electrical
chusetts Institute of Technology in 1975 and the engineering from Stanford University, Stanford,
M.S. and Ph.D. degrees in electrical engineering CA, in 1984, 1986, and 1994, respectively.
from Stanford University in 1976 and 1980, re- Her research involved the seminal study of
spectively. polycrystalline silicon–germanium films and
From 1980 to 1993, he was with AT&T their applications in metal–oxide–semiconductor
Bell Laboratories, Holmdel, NJ, where he did technologies.
research on novel sources of ultraviolet and soft From 1992 to 1996, she was a Member
X-ray coherent radiation, advanced lithography, of Research Staff with the Xerox Palo Alto
picosecond optoelectronics, semiconductor Research Center, Palo Alto, CA, researching
physics, surface physics, MOS device physics, and integrated circuit and developing polycrystalline–silicon thin-film transistor technologies
process technology. From 1987 to 1990, he was Head of the Laser Science for high-performance flat-panel display and imaging applications. She is
Research Department at Bell Labs. From 1990 to 1993, he was Head of currently an Associate Professor of Electrical Engineering and Computer
the ULSI Technology Research Department, Bell Labs, Murray Hill, NJ. Sciences, University of California, Berkeley, and the Director of the
Since 1993, he has been Professor of Electrical Engineering and Computer University of California, Berkeley, Microfabrication Laboratory. She
Sciences at the University of California, Berkeley, with a joint appointment has authored or coauthored over 150 publications and holds six U.S.
at the Lawrence Berkeley National Laboratory, Berkeley, CA. His current patents. Her research activities are presently in sub-50-nm Si devices and
research activities include extreme ultraviolet lithography, nanoscale technology, and thin-film materials and devices for integrated microsystems
MOSFET device technology, novel techniques for nanofabrication, and and large-area electronics.
new devices for nanoelectronics.
Dr. Bokor is a Fellow of the American Physical Society and the Optical
Society of America.