High-frequency FinFET model Parameter extraction: Device models for bulk and SOI MOSFETs are

well developed, and they are successfully being applied to digital and
J. Wang, C. Hutchens, J. Popp, J. Rowland and Y. Zhang analogue IC design. The device structure of FinFETs is substantially
different from planer MOSFETs, but they basically share the same
An RF model of FinFET is presented; its transition frequency (fT) and operation principles. The RF model we propose is shown in Fig. 2a,
unit power gain frequency (fmax) can reach 40 and 80 GHz, respec- which includes the complete intrinsic quasi-static MOS model, as well as
tively. The parameter extraction procedure is described. A good the parasitic circuit elements. The intrinsic model is the sub-circuit within
agreement is obtained up to 10 GHz. the three internal nodes (G0, S0 and D0 ). The intrinsic model is embedded
in the extrinsic circuit, which includes the parasitic impedances asso-
Introduction: As the microelectronic industry is approaching the limit ciated with the external nodes and a substrate coupling network.
of bulk CMOS scaling, there are extensive research activities on The parasitic resistance is extracted first at low frequency while the
advanced CMOS structures to extend the limit beyond 65 nm. The device is biased at VGS ¼ VDS ¼ 0 V. Under this bias condition the
double-gate MOSFET (DGFET) structure is a popular choice, since it contribution from the intrinsic circuit vanishes, except the capacitance
can effectively suppress short channel effects for a given equivalent gate between the three internal nodes (Cf and Cds). In addition, at low
oxide thickness [1]. Among various device configurations in the family frequency the parasitic inductance and the substrate coupling can be
of DGFET, the FinFET structure can be fabricated in a way similar to the neglected. The resulting schematic of the zero bias equivalent circuit at
conventional CMOS process without much disruption, thus it is the low frequency is shown in Fig. 2b. The parasitic resistors in the circuit
leading candidate for the next generation MOSFET [2]. A number of can be extracted from the real components of the Z-matrix elements:
models were reported recently for DGFET [3–5], but an RF model for ReðZ11 Þ ¼ Rg þ Rs ð1Þ
FinFET has not yet been developed. In this Letter we propose an RF
model for the FinFET, which is based on the measurements in GHz ReðZ22 Þ ¼ Rd þ Rs ð2Þ
region. ReðZ12 Þ ¼ ReðZ21 Þ ¼ Rs ð3Þ
The FinFETs were fabricated at SPAWAR system centre IC fabrica-
tion facility in San Diego. The gates of the FinFET were e-beam written
at UC Berkeley with a range of 50 to 200 nm, and the gate width for Table 1: Extracted model parameters
each fin is 100 nm. There are 720 fins in this transistor, thus the overall Rg 4.6 O Rs 10 O Rd 10 O Rch 10 O Rds 450 O
gate width is 72 mm. First the DC I-V curves are measured (shown in Rdb 60 O Rsb 60 O Rgb 110 O Rdsb 98 O Cgs 300 fF
Fig. 1). The S-parameters were measured with an Agilent 8510 network Cds 260 fF Cdb 11.2 fF Csb 11.2 fF Cgb 5.6 fF Cf 66 fF
analyser and Cascade RF-1 probe station with ACP GSG probes. The
Lg 100 pH Ls 50 pH Ld 50 pH Gm 0.1 S t 5 ps
data was collected from 45 MHz to 10 GHz.

Fig. 1 I-V characteristics FinFET (W ¼ 72 mm, L ¼ 80 nm)

Fig. 3 Measured (dots) and modelled (lines) S-parameters (VGS ¼ 0.6 V,

VDS ¼ 1.2 V)
a S11, S12 and S22
b S21

In a similar way, the parasitic inductors can be extracted from the

imaginary components [6]. With the knowledge of the parasitic
resistance and inductance, the intrinsic model can be determined.
Fig. 2 FinFET RF model, and equivalent circuit at zero bias First, the S-parameters are measured at low frequency under the bias
a FinFET RF model condition of VGS ¼ 0.6 V and VDS ¼ 1.2 V, and then they are converted
b Equivalent circuit at zero bias to Z-parameters. In the next step, the parasitic resistance terms are

ELECTRONICS LETTERS 31st March 2005 Vol. 41 No. 7

deducted and the intrinsic Z-parameters are obtained. In the intrinsic J. Wang, C. Hutchens and Y. Zhang (Department of Electrical and
model most of the components are in shunt connection to the internal Computer Engineering, 202 Engineering South, Oklahoma State
source node, so the intrinsic Z-parameters are converted to the University, Stillwater, OK 74078, USA)
Y-parameters, and then the circuit elements in the intrinsic model can E-mail: jianning.wang@okstate.edu
be extracted, which is shown in the following equations [7]:
J. Popp and J. Rowland (SPAWAR Systems Center, San Diego, CA
Y 0 ¼ 1=Z 0 ð4Þ 92152, USA)
0
Cf ¼ Cgd ¼ jImðY12 Þj=o ð5Þ
0 0
References
Cgs ¼ ½ImðY11 Þ þ ImðY12 Þ
=o ð6Þ
0 0 1 Solomon, P.M., et al.: ‘Two gates are better than one’, IEEE Circuits
Cds ¼ ½ImðY22 Þ þ ImðY12 Þ
=o ð7Þ Devices Mag., 2003, 19, pp. 48–62
0 2 Nowak, E.J., et al.: ‘Turning silicon on its edge’, IEEE Circuits Devices
rds ¼ 1=ReðY22 Þ ð8Þ
0 0 Mag., 2004, 20, pp. 20–31
gm ¼ jY21  Y12 j ð9Þ
  3 Chan, M., et al.: ‘A framework for generic physics based double-gate
0 0
ImðY21  Y12 Þ MOSFET modeling’. Proc. 2003 Nanotechnology Conf., San Francisco,
t ¼ arctan 0  Y 0 Þ =o ð10Þ CA, February 2003,pp. 270–273
ReðY21 12
4 Chen, Q., Wang, L., and Meindl, J.D.: ‘Physics-based device models for
gmx ¼ gm  ejot ð11Þ nanoscale double-gate MOSFETs’. 2004 Int. Conf. on Integrated Circuit
Design and Technology, Piscataway, NJ, 2004, pp. 73–79
where t is the time delay of the voltage-controlled current source. The 5 Kim, K., Fossum, J.G., and Chuang, C.-T.: ‘Physical compact model for
circuit elements in the substrate network are extracted by fitting with the threshold voltage in short-channel double-gate devices’. 2003 IEEE Int.
measurement results at high frequencies. Conf. on Simulation of Semiconductor Processes and Devices,
Piscataway, NJ, 2003, pp. 223–226
6 Lee, S., et al.: ‘A novel approach to extracting small-signal model
Results: The extracted model parameters are listed in Table 1. To verify parameters of silicon MOSFET’s’, IEEE Microw. Guid. Wave Lett.,
this model, the S-parameters of the circuit are simulated in ADS. Fig. 3 1997, 7, (3), pp. 75–77
shows the comparison between the measured data and the simulation 7 Lovelace, D., Costa, J., and Camilleri, N.: ‘Extracting small-signal model
result, and it can be seen they match quite well in a wide frequency range. parameters of silicon MOSFET transistors’, IEEE MTT-Symp. Dig., 1994,
pp. 865–868

Acknowledgments: The authors wish to thank the SPAWAR system

centre for fabrication support, C.-M. Liu for equipment support and
Oklahoma EPSCoR NanoNet for research assistance.

# IEE 2005 19 November 2004

Electronics Letters online no: 20057665
doi: 10.1049/el:20057665

ELECTRONICS LETTERS 31st March 2005 Vol. 41 No. 7