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9, SEPTEMBER 2011
Abstract—The multilevel multiphase technology combines the the large number of devices that must be controlled [27].
benefits of multilevel converters and multiphase machines. Re- Carrier-based pulsewidth modulation (PWM) is a simple mod-
cently, a new multilevel multiphase space vector pulsewidth mod- ulation technique that individually handles each leg of the con-
ulation algorithm that is valid for any number of levels and phases
was developed. In this paper, a generic digital VHDL module for verter. Therefore, its application multiphase converter is rather
such an algorithm is presented. This module is parameterizable straightforward [28], [29]. The space vector PWM (SVPWM)
in relation to the number of levels, the number of phases, and simultaneously deals with all phases of the converter, and con-
the number of bits of fractional part of the reference vector. It is sequently, the extension of the three-phase SVPWM techniques
also technology independent, reusable, and modular. This circuit to multiphase converters is more involved. In the last years,
has been tested by implementation in a field-programmable gate
array, with the goal of a balance of speed and area optimization. many multiphase SVPWM algorithms have been developed
It was tested by using a five-level five-phase inverter feeding an [30]–[42]. Most of them are devoted to two-level converters,
induction motor. and they make use of the multiple dq space concept [30]–
Index Terms—Field-programmable gate array (FPGA), mul- [38]. The SVPWM techniques in [30] and [31] for five-phase
tilevel converter, multiphase machine, space vector pulsewidth converters, in [32] for seven-phase converters, and in [33] and
modulation (SVPWM), VHDL. [34] for nine-phase converters can only deal with the sinusoidal
output voltage. The SVPWM algorithms presented in [35]
I. I NTRODUCTION and [36] allow us to add small amplitude harmonics to the
output voltage. The extension of the sinusoidal output SVPWM
II. M ULTILEVEL M ULTIPHASE SVPWM A LGORITHM 2) Calculate the permutation matrix P that sorts the
In multiphase converters, the SVPWM is a multidimensional vector vf in descending order in accordance with
problem where the vector selection can be directly carried out in
1 1
a multidimensional space [43]. In [40], the modulation problem P = (4)
vf v̂f
of a P -phase converter is formulated in a P -dimensional space,
and it is solved for multilevel topologies in which the output where v̂f = [v̂f1 , v̂f2 , . . . , v̂fP ]T is the sorted vector in
level of every phase is an integer multiple of a fixed voltage step which
Vdc . Flying capacitor, diode-clamped, cascaded full-bridge, and
hybrid converters are included in such topologies [61]. Since
the switching states of any power converter topology stay at dis- 1 > v̂f1 ≥ · · · ≥ v̂fk−1 ≥ v̂fk ≥ · · · ≥ v̂fP ≥ 0. (5)
crete states, the SVPWM technique in [40] is used to synthesize
a reference voltage vector vr = [vr1 , vr2 , . . . , vrP ]T by means
of a sequence of space vectors during each modulation cycle. 1 All of the details of the mathematical justification of the modulation
1 2 P T
Each space vector vsj = [vsj , vsj , . . . , vsj ] must be applied algorithm can be found in [40].
3948 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 9, SEPTEMBER 2011
D = PT D̂. (7)
Fig. 4. Hierarchical view of the multilevel multiphase SVPWM circuit. (a) NP_SVPWM circuit. (b) 2P_SVPWM circuit.
TABLE II
S IZE OF THE M AIN BASIC C OMPONENTS U SED BY THE I NTERNAL C IRCUITS
swaps have occurred on the last pass. The sorted vector is stored 5) t_calc: This circuit calculates the dwell times tj from
in the RAM Vo(ko), and the final position of each component the sorted vector v̂f in accordance with (9). The result is stored
at the end of the sort process, with respect to its initial position, in the dual-port RAM t(j). The t_calc circuit is composed
is stored in the RAM Id(kid). Both RAMs have two read ports of one counter, two registers that are used to store the minuend
and one write port. The read ports are used by the processing and the subtrahend, one subtracter, one dual-port RAM, and one
unit to access the dual-port RAM and to easily swap the vector FSM. The minuend register is initialized to a value of one to
components with the help of an auxiliary register. The Vf_sort ease the calculation of the first switching time t1 = 1 − v̂f1 .
circuit is composed of two counters, five multiplexers, two 6) Vs_calc: This circuit calculates the final switching vec-
registers, one magnitude comparator, two dual-port RAMs, and tor sequence {vsj } in accordance with (10). The results are
one FSM. stored component by component in the 2-D dual-port RAM
k
3) D_calc: This circuit calculates matrix D in accordance Vs(ks, js). Therefore, to access the component vsj of the final
with (7). Matrix PT reversely rearranges the rows of matrix switching sequence, it is necessary to provide the row address
D̂ with respect to the sort process of the fractional part. For ks and column address js, as with the {vdj } sequence in
example, if the third component of vector vf finally takes the the Vd_extr circuit. The Vs_calc circuit is composed of two
fifth position, then the fifth row of matrix D will finally have counters, one adder, one dual-port RAM, and one FSM.
the value of the third row of the upper triangular matrix D̂. All signals, except Vr(kr), t(j), and Vf(kf), are integer
Consequently, this circuit rearranges the rows of matrix D̂ with numbers represented with the number of bits shown in Fig. 4.
the information stored in Id(kid). Each row of the resulting These three signals are real numbers that are represented in
matrix D is stored in a memory position of the dual-port RAM the fixed-point format. Signal Vr(kr) is represented in two’s
D(row). The first row of matrices D̂ and D̂, which is useful complement using I bits for the integer part and Q bits for the
in algorithm demonstration, was not taken into account in the fractional part. Signal Vf(kf) is a positive real number in the
implementation because this row is always constant, and it is range [0, 1), with all Q bits representing the fractional part.
not needed in extracting the displaced switching vectors vd . Signal t(j) is a real number in the range [0, 1], using one bit
The D_calc circuit is composed of one counter, one register, to represent the integer part and Q bits to represent the frac-
one dual-port RAM, and one FSM. tional part.
4) Vd_extr: This circuit extracts the displaced switching The size of the main basic components used by the internal
vector sequence {vdj } from the coefficient matrix D according circuits is detailed in Table II. It depends basically on the
k
to (8). The values of the components vdj of each vector are number of phases, directly through parameter P , and indirectly
stored bit by bit in the 2-D RAM Vd(kd, jd). This simplifies through variables J and K. The number of bits of the reference
the later calculations of the switching vector sequence {vsj }. vector Q and the number of levels through variable I have a
A parameterizable 2-D dual-port RAM, with row and column lower influence in the circuit size.
addresses, was defined in VHDL. The parameters are the Table III shows the number of clock cycles nclk used by the
row size, the column size, and the number of bits of each internal circuits. Related to this table, it is necessary to highlight
memory position. Physically, the memory is implemented as the following issues.
a conventional RAM in which the actual address is obtained by
combining both the row and column addresses by the equation 1) The number of clock cycles n2 used by the Vf_sort
address = row_address × 2column_size + column_address. The circuit is not constant. It depends on the initial sorting
column address jd is used to access the jth vector of the of the numbers.
displaced vector sequence {vsj }, and the row address kd is 2) The value 2i in every circuit is due to two initial clock cy-
k cles, which simultaneously elapse for all circuits. There-
used to access the k component vdj of that vector. The Vd_extr
circuit is composed of two counters, one register, one dual-port fore, both cycles do not accumulate to the total delay of
RAM, and one FSM. the whole circuit.
3952 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 9, SEPTEMBER 2011
TABLE IV
FPGA R ESOURCES U SED BY THE NP_SVPWM C IRCUIT
to represent the number nine. Any other FPGA with the same
SRAM technology from other manufacturer will give similar
implementation results. As an example, the implementation of
the NP_SVPWM circuit with N = 5, P = 5, and Q = 9 in FPGA
EP2C5F256C6, which is the smallest FPGA of the Cyclone II
family from Altera, uses 242 logic elements (out of 4608),
136 flip-flops (out of 4608), and 768 memory bits (out of
119 808).
Table V shows the maximum converter switching fre-
quency fs that can be achieved with the NP_SVPWM circuit. The
3) The number of clock cycles n5 elapsed by the t_calc value of fs is
circuit has not been added to the total number of clock
1
cycles elapsed by the 2P_SVPWM and NP_SVPWM circuits, fs ≤ (11)
i.e., nclk = n2 + n3 + n4 and nclk = n1 + n2 + n3 + nclk τclk
n4 + n6 . It is because t_calc simultaneously runs with where the number of clock cycles nclk is obtained from Table III
D_calc and Vd_extr, and the sum of the number of and the minimum applicable clock period τclk is extracted
clock cycles used by these two circuits is always greater from the implementation tool report. The maximum switching
than the number of clock cycles used by the t_calc cir- frequency of the modulator circuit in Table V is, in all cases,
cuit (n3 + n4 > n5 ). Fig. 3 shows the number of cycles higher than the typical switching frequencies used with the
elapsed by the circuits in the particular case P = 3. multilevel power converters. The implementation results, i.e.,
Since the circuit is synchronous, the calculation time can be the resources used and the clock delay, can slightly vary from
calculated by taking into account the clock frequency and the one implementation to another, with no circuit modifications
number of clock cycles needed by the modulation algorithm. It due to the nondeterministic nature of the place and route
is also important to remark that only the number of phases P algorithms.
has influence on the circuit speed. The time resolution of the modulation circuit is given by
δ = max(τclk , τm ), where τclk is the clock period applied to the
circuit and τm is the mathematical resolution of the algorithm.
D. Implementation Results The value of τm can be calculated from the converter switching
frequency and the parameter Q as
The parameterizable NP_SVPWM circuit has been imple-
mented in FPGA XC3S200-FT256-4. This FPGA, which
1
belongs to the Spartan 3 family from Xilinx, has basic τm = . (12)
2Q fs
configurable logic block cells called as slices, composed mainly
of two LUTs that are 16 b (16 × 1) and two flip-flops. This is
the second smallest FPGA of the family, which has 1920 slices
IV. V ERIFICATION
(thus, 3840 LUTs and 3840 slice flip-flops).
Table IV shows the resources used by the NP_SVPWM circuit, The NP_SVPWM circuit was tested by simulation and in the
with different parameter values, obtained through the Founda- laboratory with a five-level five-phase converter. Nine bits were
tion ISE 10.1 tool. The parameters that have a major influence considered to represent the fractional part of the reference
are the number of phases P and the number of bits Q. The vector. Therefore, the svpwm_constants.vhd package is con-
number of levels N affects in a lesser extent, and if its increment figured with N = 5, P = 5, and Q = 9, as shown in Table I.
does not require more bits for its representation, it does not
affect the amount of resources used at all. For instance, in the
A. Simulation Results
five-phase case, the resources used by the circuit for five and
seven levels are the same. In the same case, with nine levels, the Figs. 6 and 7 show the simulation results of the multilevel
resources used increase a little because of the extra bit required multiphase SVPWM circuit. All of them have been obtained
ÁLVAREZ et al.: DIGITAL PARAMETERIZABLE VHDL MODULE FOR MULTILEVEL MULTIPHASE SVPWM 3953
Fig. 6. Simulation results for the five-level five-phase NP_SVPWM circuit. (a) Input values for the reference vector vr . (b) Output values for the switching vector
sequence {vsj } and the switching times tj .
a circle in the d1 –q1 plane and a point in the d2 –q2 plane that
corresponds to a pure sinusoidal output, which proves that the
system properly operates.
The NP_SVPWM module was tested with a converter with
externally supported dc sources, which alleviates the voltage
capacitor balancing issue present in a number of applications.
The SVPWM algorithm in [40] is a simple modulation tech-
nique that generates an output phase-to-neutral voltage that is
equal to the reference phase-to-neutral voltage. Consequently,
this multilevel multiphase algorithm does not handle joint-
phase redundancy, and it cannot integrate a general balancing
capacitor technique. Nevertheless, in multilevel topologies with
per-phase redundancy [61], such as flying capacitor and cas-
caded full-bridge converters, the Trigger_signals subcircuit
Fig. 11. Voltages and current of phase a.
in the Trigger auxiliary circuit can be designed to select the
appropriate trigger signals from the switching vectors to the
balance voltage capacitors. If the neutral voltage is not a con-
straint, then the SVPVM algorithm in [41], which handles joint-
phase redundancy, is a more appropriate modulation technique
because it has a degree of freedom that can be used for volt-
age capacitor balancing. Additionally, the NP_SVPWM module
requires balanced dc voltages. In the case of unbalanced dc
voltages, the output voltage distortion can be reduced with the
specific multilevel multiphase feedforward SVPWM technique
in [62].
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motor drive with integrated neural network algorithms,” IEEE Trans. Ind. Since 2004, he has been an Assistant Professor
Electron., vol. 55, no. 2, pp. 551–561, Feb. 2008. with the Department of Electronics Technology, Uni-
[52] M. Hajian, J. Soltani, A. Markadeh, and S. Hosseinnia, “Adaptive non- versity of Vigo. His research interests include the ac
linear direct torque control of sensorless IM drives with efficiency op- power switching converter technology.
timization,” IEEE Trans. Ind. Electron., vol. 57, no. 3, pp. 975–985,
Mar. 2010.
[53] M.-W. Naouar, E. Monmasson, A. A. Naassani, I. Slama-Belkhodja, and
N. Patin, “FPGA-based current controllers for ac machine drives—A
review,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1907–1925,
Aug. 2007.
[54] A. Sathyan, N. Milivojevic, Y.-J. Lee, M. Krishnamurthy, and A. Emadi, Francisco D. Freijedo (M’07) received the M.Sc.
“An FPGA-based novel digital PWM control scheme for BLDC mo- degree in physics from the University of Santiago de
tor drives,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 3040–3049, Compostela, Santiago de Compostela, Spain, in 2002
Aug. 2009. and the Ph.D. degree from the University of Vigo,
[55] Y.-Y. Tzou and H.-J. Hsu, “FPGA realization of space-vector PWM con- Vigo, Spain, in 2009.
trol IC for three-phase PWM inverters,” IEEE Trans. Power Electron., Since 2005, he has been an Assistant Professor
vol. 12, no. 6, pp. 953–963, Nov. 1997. with the Department of Electronics Technology, Uni-
[56] O. López, J. Alvarez, J. Doval-Gandoy, F. D. Freijedo, A. Nogueiras, versity of Vigo. His research interests include qual-
A. Lago, and C. M. Peñalver, “Comparison of the FPGA implementa- ity problems, grid-connected switching converters,
tion of two multilevel space vector PWM algorithms,” IEEE Trans. Ind. ac power conversion, and flexible ac transmission
Electron., vol. 55, no. 4, pp. 1537–1547, Apr. 2008. systems.
[57] E. F. F. Lima, N. P. Filho, and J. O. P. Pinto, “FPGA implementa-
tion of space vector PWM algorithm for multilevel inverters using non-
orthogonal moving reference frame,” in Proc. IEEE IEMDC, Miami, FL,
May 3–6, 2009, pp. 709–716. Jesús Doval-Gandoy (M’99) received the M.Sc.
[58] E. J. Bueno, A. Hernandez, F. J. Rodriguez, C. Giron, R. Mateos, and degree from the Polytechnic University of Madrid,
S. Cobreces, “A DSP- and FPGA-based industrial control with high-speed Madrid, Spain, in 1991 and the Ph.D. degree from
communication interfaces for grid converters applied to distributed power the University of Vigo, Vigo, Spain, in 1999.
generation systems,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 654– From 1991 to 1994, he worked at the industry. He
669, Mar. 2009. is currently an Associate Professor with the Depart-
[59] M. Ben Smida and F. Ben Ammar, “Modelling and DBC-PSC-PWM ment of Electronics Technology, University of Vigo.
control of a three-phase flying capacitor stacked multilevel voltage source His research interests include ac power conversion.
inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2231–2239,
Jul. 2010.