8085 Microrprocessor Lecture Note

Mekelle Institute of Technology Microprocessor Lecture note February 2, 2010
Chapter one
Introduction to Intel 8085 microprocessor
Definition
A microprocessor is a multipurpose, programmable, clock driven, register based electronics
device that reads binary instructions from a storage device called memory, accepts binary data as
input and processes data according to those instructions, and provides results as output.
Application area
Microprocessor is a general purpose electronic device. It is used for monitoring and controlling
electronic devises. Some of the application areas are listed below:
 Measuring instruments such as the oscilloscope, multi-meter, and spectrum analyzer

 Controlling household items such as the microwave oven, door bell, washing machine,
and television.
 Monitoring defense equipments such as missiles and radar
 Computers
 Controlling traffic light
 Controlling speed and direction of stepper motor
 Monitoring medical equipment such as blood pressure and blood analyzer
Important factors used to compare microprocessor

In general, each microprocessor has some strong and weak points compared to the other because
the manufacturers design their microprocessors for certain application areas or specific segment
of the industrial market. It is difficult to comment that one microprocessor is better than the other
because many factors have to be considered before making such comments. Important among
these factors are:
1. Number and type of registers
 Speed
 Cost 2. Addressable memory range
 Power consumption
 Instruction set 3. Control bus functions
Internal Architecture of 8085 Microprocessor
Compiled by Solomon Teklehaimanot Page 1

Fig 1.1 Internal architecture of 8085 microprocessor

Control Unit
Generates signals within microprocessor to carry out the instruction, which has been decoded. In
reality causes certain connections between blocks of the uP to be opened or closed, so that data
goes where it is required, and so that ALU operations occur.
Arithmetic Logic Unit

An arithmetic logic unit functionally consists of an adder, an accumulator, a shift register,
temporary register and status or flag register.
The shift register may transfer data from the accumulator to the bus by either shifting it right or
left, or transfer it directly.
The temporary register is used to hold bus data to or from the ALU and the status register.
Accumulator is an 8-bit register used for arithmetic, logic, I/O and load/store operations. This
register is used to store 8-bit data and to perform arithmetic and logical operations. The result of
an operation is stored in the accumulator. The accumulator is also identified as register A.
N.B Most operations in the ALU involve the accumulator.

Basic function of the ALU is to perform the following arithmetic and logic operations:
Arithmetic operations Logic operations

 Addition  And
 Subtraction  Or
 Increment  Ex-or
 Decrement  Not
 Compare  Compare
 Shift/rotate
Status register
The status (condition) of contents of the accumulator is indicated by 5 flip-flops. The five flags
that indicate the status of the accumulator are shown in the fig. below.
S Z X AC X P X C
Fig 1.2 Status Register
The letter X in the status flags indicates “do n’t “care conditions and these bits are used
internally. These status flags are named as:
- Zero (Z)
- Sign (S)
- Parity (P)
- Carry (C)
- Auxiliary carry (AC)
N.B. The flags and accumulator together is called program status word (PSW).
The flags are SET (ON=1) or RESET (OFF=0) as a result of operations such as addition,
subtraction etc.
Sing flag (S)

The flag is set or reset according to the condition of the MSB or the 7th bit of the accumulator
after arithmetic and logic operations. If any one of the operations make the 7th (D7) bit of the
accumulator high (1), the flag is set otherwise reset. This is useful when singed binary operations
are performed.
Example: subtract C5H from 60H
60H

+ 2BH (2’s complement of C5H)

---------------
8BH
The result of this operation sets the sign flag of the accumulator to signify the content of the
accumulator is negative in signed value operation.
Zero flag
This flag indicates that the result of any operation in the accumulator is zero. If the contents in
the accumulator is zero, this flag is SET (ON=1) otherwise RESET (OFF=0).
Example: Add FFH and 01H
FFH
+01H
-----------------
1 00H
The result in the accumulator is zero. Therefore, Z=1.
Auxiliary Carry Flag

The flag indicates that the operation in the accumulator had a carry from the third bit to the 4th
bit and this flag would be SET (ON=1) otherwise RESET (OFF=0).
Example: Add 0FH and 3AH
0FH
+3AH 0 0 0 0 1 1 1 1
--------------- 0 0 1 1 1 0 1 0
49H 0 1 0 0 1 0 0 1
Parity Flag (P)
This flag indicates whether the total number of 1’s in the accumulator after execution of any
program is odd or even. If the total number of 1’s in the accumulator after execution is even, P=1
and if the number of 1’s is odd, P=0.
Example: Add 60H and 3AH
60H 01100000
+3AH 00111010
------------------ ---------------------
9AH 10011010
The total number of 1’s present in this operation is 4. Hence parity is even. i.e. parity flag will be
SET (ON = 1).

Carry Flag (C)

This flag is SET if there is any over flow from the seventh bit of the accumulator otherwise
RESET after some arithmetic or logic operations.
Example: Add 83H and D2H
1
83H
1 0 0 0 0 0 1 1
+D2H
1 1 0 1 0 0 1 0
--------------
0 1 0 1 0 1 0 1
55H
Instruction Register and Decoder

Temporary stores the current instruction of a program. Latest instruction sent here from memory
prior to execution. Decoder then takes instruction and ‘decodes’ or interprets the instruction.
Decoded instruction then passed to next stage.
Timing and control unit

This unit controls and synchronizes all the operations inside the and outside microprocessor in
any microprocessor systems.
Register section of 8085 microprocessor

The registers available inside the microprocessor are broadly divided into 2-groups:
1. Registers accessible to the programmer
2. Registers not accessible to the programmer
A (8)
Flag Register
B (8) C (8)
D (8) E (8)
E (8) L (8)
SP (Stack Pointer)
PC (Program Counter)
Fig. 1.3 Registers of 8085
Registers accessible to the programmer are further sub-divided into 2 sub-groups.

1. General purpose registers (GPRs), and
2. Special purpose registers (SPRs)

General Purpose Registers (GPRs)

As the name suggests the GPRs can be used for both storing the data as well as the address. The
8085 microprocessor has 6 general purpose registers, namely B, C, D, E, H and L. In 8085
microprocessor, the data size is 8-bit wide and the address size is 16-bit wide. Hence they can be
used in pairs as follows:
 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. Some
instructions may use BC register as a data pointer.
 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. Some
instructions may use DE register as a data pointer.
 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. HL register
usually contains a data pointer used to reference memory addresses.
Special Purpose Registers (SPRs)

These are used for some specific applications designated by the manufacturers. The special
purpose registers of 8085 microprocessor are:
1. Accumulator (A)
2. Program Counter
3. Stack pointer
4. Status Flag Register
Program Counter
This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit
register.
The function of the program counter is to point to the memory address from which the next byte
is to be fetched. When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location. Branching is implemented by making
changes to the program counter (for example, Jump instruction).
Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-
bit address in the stack pointer.
8085 System Buses

The system bus is a communication path between the microprocessor and peripherals;
It is nothing but a group of wires to carry data or address.
Address Bus
Address bus carries address. The address bus consists of 16 wires. That is its width is 16 bit -
wide. Address bus is unidirectional, the numbers are only sent from microprocessor to memory

or ports not the other way. Using this address, 8085 microprocessor can access 64K byte of
memory.
Data Bus
Data Bus carries data in binary form between microprocessor and other external units, such as
memory. The data bus typically consists of 8 wires and is bidirectional. The data bus also carries
instructions from memory to the microprocessor. Therefore, the size of the bus limits the number
of possible instructions to 256.
Control Bus
Control Bus is various lines which have specific functions for coordinating and controlling uP
operations. Eg: Read/Not Write line, single binary digit. Control whether memory is being
‘written to’ (data stored in mem) or ‘read from’ (data taken out of mem) 1 = Read, 0 = Write.
May also include clock line(s) for timing/synchronizing, ‘interrupts’, ‘reset’ etc.
The Control Bus carries control signals partly unidirectional, partly bi-directional. Control
signals are things like "read or write". This tells memory that we are either reading from a
location or writing to a location specified.
Memory
Program, data and stack memories occupy the same memory space. The total addressable
memory size in Intel 8085 microprocessor is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch and call
instructions can be used to jump/branch anywhere within 64 KB.
Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.

8085 Pin description

The 8085 is an 8-bit general-purpose microprocessor capable of addressing 64K of memory. The
device has forty pins, requires a +5V single power supply, and can operate with a 3-MHz single
phase clock.
Fig.1.4. Pin configuration of Intel 8085 Microprocessor

Pin Description
The following describes the function of each pin:
Address Bus: A15-A8, AD7-AD0 (Output 3 States)

The 8085 has 16 signal lines (pins) that are used as the address bus; however, these lines are split
into segments: A15-A8 and AD7-AD0. The eight signal lines, A15-A8, are unidirectional and
used for the most significant bits, called the high order address, a 16 bit address. The AD7-AD0
lines are used for dual purpose.
AD0 - AD7 (Input/output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 addresses) appear on
the bus during the first clock cycle of a machine state. It then becomes the data bus during the
second and third clock cycles. These lines enter into tri-stated during Hold and Halt modes. AD0
- AD7 are a bidirectional: they serve as a dual purpose. They are used as the lower-order address
bus and data bus.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the
address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information.
Data Bus Status (SO, S1 Output)

S0 and S1 are status signals to specify the kind of operation being performed.
Encoded status of the bus cycle

S1 S0
O O HALT
0 1 Memory/IO WRITE
1 0 Memory/IO READ
1 1 Opcode FETCH
RD (Output tri-state)
READ; indicates the selected memory or I/O device is to be read and that the Data Bus is
available for the data transfer.
WR (Output tri-state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory or I/0
locations. Data is set up at the trailing edge of WR. 3 stated during Hold and Halt modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If Ready is low, the CPU will wait for Ready to go high before
completing the read or write cycle.
HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The
CPU, upon receiving the Hold request, will relinquish the use of buses as soon as the completion
of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will
relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed.
The CPU takes the buses one half clock cycles after HLDA goes low.
Interrupts
The processor has 5 interrupts. They are presented below in the order of their priority (from
lowest to highest):
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA will be issued. INTR is maskable interrupt. When the
interrupt occurs, the processor usually fetches one of these instructions:
 8 RST instructions (RST0 - RST7). The processor saves current program counter into
and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7
supplied with the instruction).
 CALL instruction (3 byte instruction). The processor calls the subroutine, address of
which is specified the second and third bytes of the instruction.
INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the
Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or
some other interrupt port.
RST5.5 (Input) is a maskable interrupt. When this interrupt is received the processor saves the
contents of the register into stack and branches to 2Ch (hexadecimal) address.
contents of the register into stack and branches to 34h (hexadecimal) address.
contents of the register into stack and branches to 3Ch (hexadecimal) address.
Trap is a non-maskable interrupt. When this interrupt is received the processor saves the
contents of the register into stack and branches to 24h (hexadecimal) address.
Related links

All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5,
RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable, HLDA flip flops flags
and registers (except the instruction register) are affected. The CPU is held in the reset condition
as long as Reset is applied.
RESET OUT (Output)

Indicates CPU is being reset. It can be used as a system RESET. The signal is synchronized to
the processor clock.
X1, X2 (Input)
X0 and X1 are inputs from the crystal or clock generating circuit. The frequency is internally
divided by 2. So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be
connected to the X0 and X1 pins.
CLK (Output)
CLK pin is an output clock line to drive the clock of the rest of the system.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or I/O during Hold and Halt modes.
SID (Input)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
Vss: Ground reference.

Vcc: +5V power supply.
Instruction and Computer Languages

An instruction is a binary pattern entered through an input device in memory to command the
microprocessor to perform that specific function.
An instruction can be written in a variety of forms. We write instructions using their mnemonic
codes and symbolic address. However a microprocessor can decode and execute only binary
coded instruction. Therefore, for each operation that can be executed by a microprocessor, there
is a binary code.
8085 instruction set consists of the following instructions:

 Data transfer instructions: This group of instructions copy data from a location called
a source to another location called a destination, without modifying the contents of
the source. Input/output instructions are data transfer instructions.

 Arithmetic instructions - These instructions perform arithmetic operations such as

addition, subtraction, increment, and decrement. Addition - Any 8-bit number, or the
contents of a register or the contents of a memory location can be added to the
contents of the accumulator and the sum is stored in the accumulator. No two other 8-
bit registers can be added directly.
 Logic instruction-These instructions perform various logical operations with the
contents of the accumulator such as AND, OR, Exclusive-OR. Any 8-bit number, or
the contents of a register, or a memory location can be logically ANDed, Ored, or
Exclusive-ORed with the contents of the accumulator.
 Rotate- Each bit in the accumulator can be shifted either left or right to the
next position.
 Compare- Any 8-bit number or the contents of a register, or a memory can be
compared for equality, greater than, or less than, with the contents of the
accumulator.
 Complement - The contents of the accumulator can be complemented. All 0s
are replaced by 1s and all 1s are replaced by 0s.
 Control transfer -This group of instructions alters the sequence of program execution
either conditionally or unconditionally.
Jump - Conditional jumps are an important aspect of the decision-making process in
the programming. These instructions test for a certain conditions (e.g., Zero or Carry
flag) and alter the program sequence when the condition is met. In addition, the
instruction set includes an instruction called unconditional jump, Call, Return, and
Restart.
 Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.
Machine Language
A machine language program is written using binary codes and addresses. A microprocessor
only understands machine language programs. Machine language coding is time-consuming and
error-prone. Usually machine language programmers are concerned with hardware details. Every
computer or family of computers has its own machine language; each is machine-dependent
Assembly Language is a symbolic representation of machine language of a specific processor or

is a symbolic, non-binary format instruction (human-readable version of machine language) that
allows mnemonic names to be used for instructions and data. Assembly language is converted to
machine code by an assembler. Usually, each line of assembly code produces one machine
instruction. It is easier to write an assembly language program for a microprocessor than to write
a machine language program.
In short assembly languages:

• Represent a string of ‘0s’ and ‘1s’ for machine language instruction
• More English-like; codes shorter than machine languages
• Assembler translates into machine language

• Advantages of machine or assembly languages

– Programmer in control of hardware
– Programs written in low-level languages run more efficiently
High level languages

High level languages are designed to be easier to understand than assembly languages and allow
a program to run on multiple different kinds of computers. The source code written in high level
languages need to be translated into object code. The two basic approaches are compilers and
interpreters.
ASSEMBLY LANGUAGE OR MACHINE LANGUAGE

To word this simply, you can say that assembly language is a human-readable text, and machine
language is machine-readable binary code. When you program in assembly language, you are
programming on the machine language level. To program directly in machine language is
tedious, so you use assembly language instead, and use an assembler to produce the actual
machine code.
Advantages of higher level programming:

 Ease of learning the language
 Significantly shorter code
 Ease of debugging
 Ease of maintenance
Disadvantages of higher level programming:
 Less control over hardware
 Less efficient memory use
 Program runs more slowly
Compilers convert a finished program (or section of a program) into object code. This is often
done in steps. Some compilers convert high level language instructions into assembly language
instructions and then an assembler is used to create the finished object code.
Interpreters convert each high level instruction into a series of machine instructions and then
immediately run (or execute) those instructions. In some cases, the interpreter has a library of
routines and looks up the correct routine from the library to handle each high level instruction.
Assembler is a program that translates an assembly language program from mnemonics to the
binary machine code. i.e. Converts assembly language programs into object files.
• Object files contain a combination of machine instructions, data, and information needed to
place instructions properly in memory
• Assemblers need to
– translate assembly instructions and pseudo-instructions into machine instructions
– Convert decimal numbers, etc. specified by programmer into binary

Typically, assemblers make two passes over the assembly file

– First pass: reads each line and records labels in a symbol table
– Second pass: use info in symbol table to produce actual machine code for each
line
Linker
Tool that merges the object files produced by separate compilation or assembly and creates an
executable file.
Loader
Part of the OS that brings an executable file residing on disk into memory and starts it running
• Steps
– Read executable file’s header to determine the size of text and data segments
– Create a new address space for the program
– Copies instructions and data into address space
– Copies arguments passed to the program on the stack
– Initializes the machine registers including the stack ptr
– Jumps to a startup routine that copies the program’s arguments from the stack to
registers and calls the program’s main routine.


Chapter Two
8085 INSTRUCTION SET

DATA TRANSFER INSTRUCTIONS
One of the primary functions of the microprocessor is copying data from a register (or IO or
memory) called the source to another register (or IO or memory) called the destination.
Sources and Destination can be Registers, Memory and Devices. I.e. data transfer can take place
between:
1. Registers [from one Register to another]
2. Specific data byte to a register or a memory location
3. Memory a memory location and a register
4. An IO device and the accumulator
Move immediate 8-bit

Table 1 MVI Instruction
MVI instruction is a two byte instruction
Opcode Operand Flag Description

affected
MVI Rd, data None The 8-bit data is stored in the destination register or
memory. If the operand is a memory location, its location
M, data is specified by the contents of the HL registers.
Example: MVI B, 57H; copies the byte 57H into register B

MVI M, 57H; copies 57H to the memory location pointed by HL
Copy from source to destination

Table 2: MOV Instruction
MOV instruction is a one byte instruction
Opcode Operand Flag affected Description

MOV Rd, Rs None This instruction copies the contents of the source
M, Rs register into the destination register; the contents of
Rd, M the source register are not altered. If one of the
operands is memory location, its location is specified
by the contents of the HL registers.
Example: MOV B, C; copies the byte value stored in register C to register B

MOV B, M; the byte value pointed by HL is copied to register B
Possible register combination:

MOV A, B; AB
MOV D, L; DL
MOV H, E; HE
MOV A, C; AC
MOV L, H; LH
Specify the content of registers and the flags as the following instructions are executed.
A B C D S P Z C
MVI A, FFH
MVI B, 58H
MOV C, A
MOV D, B
HLT
Answer
Mnemonics A B C D S-Flag P-Flag Z-Flag C-Flag
MVI A, FFH XX XX XX X X X X
FFH
MVI B, 58H FFH 58H XX XX X X X X
MOV C, A FFH 58H FFH XX X X X X
MOV D, B FFH 58H FFH 58H X X X X
HLT
Load Accumulator
Table 3 LDA Instruction
LDA (Load Accumulator Direct) instruction is a 3 byte instruction

affected
LDA 16-bit address None The contents of a memory location, specified by a
16-bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered.
Example: LDA 2034H; the byte value found in 2034H is copied to register A. Assume the value
at the memory address 2034H is B6H. When the processor executes the above instruction, B6H

will be loaded into Accumulator register. I.e. A<= B6H. The content of the memory location is
not altered.
Table 4: Memory Values
Memory Byte
Location value
2035H XX
2034H B6H
2033H XX
Example-2: Specify the content of register A after the following instruction is being executed.
Assume the byte value at memory location 33FEH is 90H.
MVI B, BDH
MOV A, B
LDA 33FEH
HLT
Table 5: Memory values
Memory Byte
location value
3401H 10H
3400H 32A
33FFH 5AH
33FEH 90H
33FDH 00H
Answer
Mnemonics A B
MVI B, BDH XX BDH

MOV A, B BDH BDH
LDA 33FEH 90H BDH
HLT
Load Accumulator Indirect

Table 6: LDAX Instruction
LDAX (Load Accumulator Indirect) instruction is a 1 byte instruction

affected
LDAX B/D register pair None The contents of the designated register pair point to a
memory location. This instruction copies the
contents of that memory location into the
accumulator. The contents of either the register pair
or the memory location are not altered.
Example-1: LDAX B; byte value pointed by register pair BC is copied to register A. BC holds
the 16-bit address. Assume BH holds 4567H. The processor will load accumulator with the value
in this memory location.
Table 7: Memory Value
Memory Byte
location value
4569H 01H
4568H 23A
4567H 66H
4566H 4FH
4565h CCH

After the microprocessor executes the instruction register A will contain 66H.
Example-2: Specify the content of register A after the following instruction is being executed.
Assume the byte value at memory location F000H is 44H. BC=F000H.
MVI B, F0H
MVI C, 00H
MOV A, B
LDAX B
HLT
Table 8: Memory values
Memory Byte
location value
F002H 10H
F001H 32A
F000H 5AH
EFFFH 90H
EFFEH 00H
Answer
Mnemonics A B
MVI B, F0H XX F0H
MVI C, 00H XX F0H
MOV A, B F0H F0H
LDAX B 5AH 44H
HLT
Load register pair immediate

Table 8: LXI Instruction
LXI (Load Register Pair) instruction is a 3 byte instruction.


affected
LXI Reg. Pair, 16 bit data None The instruction loads 16-bit data in the register
pair designated in the operand.
The second byte is loaded in the higher order register example register B or D and the third byte
is loaded in the lower order register.
Example-1: LXI H, 2034H; loads 20 in register H and 34 in register L
LXI B, 8B0FH; loads 8B in register B and 0F in register C
Example-2: Write a program that loads the value pointed by the 16-bit address value in the
register pair HL to the accumulator register. Assume the value in the register pair HL is 5468H.
LXI H, 5468H;
LDAX H
HLT
Load H and L registers direct

Table 9: LHLD Instruction
LHLD instruction is a three byte instruction.

affected
LHLD 16-bit address None The instruction copies the contents of the memory
location pointed out by the 16-bit address into register L
and copies the contents of the next memory location into
register H. The contents of source memory locations are
not altered.
Example-1: LHLD 2040H; loads the byte value pointed by 2040H into register L and the byte
value found in 2041H into register H.
Answer
L<= [2040H]
H<= [2041H]
Example-2: Assume memory location 8000H contains 20H and 8001 contains FEH. Write a
program that transfers content of memory location 8000H to L and 8001H to H.

Answer
LHLD 8000H
Address Memory
Content Content of register pair HL after the above instruction is being
7FFFH xx executing
8000H 20H Register H Register L
8001H FEH
8002H YY FEH 20H
Store Accumulator Direct

Table 10: STA Instruction
STA (Store Accumulator Direct) is a 3 byte instruction.

affected
STA 16-bit address None The contents of the accumulator are copied into the
memory location specified by the operand. The second
byte specifies the Higher-order address and the third
byte specifies the lower-order address.
Example-1: MVI A, 33
STA 8050H; stores the byte value of the accumulator in memory location pointed by
4050H.
Before execution After execution of

of the STA 8050H the above
instruction instruction Accumulator
Address Value Address Value 33H
804FH XX 804FH XX
8050H XX 8050H 33H
8051H XX 8051H XX

Store Accumulator Indirect
STAX (Store Accumulator Indirect) instruction is a 1 byte instruction.
Table 11: STAX Instruction

affected
STAX Reg. pair None The contents of the accumulator are copied into the memory
location specified by the contents of the operand (register
pair). The contents of the accumulator are not altered.
Example-1: LXI B, 800FH, STAX B; stores the byte value of the accumulator in memory
location pointed by content of the register pair BC.
Before execution of After execution of

the STAX B the above
instruction instruction
Address Value Address Value

Accumulator
800EH XX 800EH XX
A7H
800FH XX 800FH A7H
8010H XX 8010H XX

Store H and L registers direct

Table 12: SHLD Instruction
SHLD (Store HL Register pair Direct) is a 3 byte instruction.

affected
SHLD 16-bit address None The contents of register L are stored into the memory
location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
contents of registers HL are not altered. This is a 3-byte
instruction, the second byte specifies the low-order

address and the third byte specifies the high-order

address.
Example-1: LXI H, 1122H, SHLD 2470H; stores the byte in register L in memory location
2470H and content of register H in 2471H.
Exchange H and L with D and E

Table 13: XCHG Instruction
XCHG instruction is a 1 byte instruction.

affected
XCHG None None The contents of register H are exchanged with the contents of
register D, and the contents of register L are exchanged with the
contents of register E.
Example: LXI H, 2020H

LXI D, 0202H
XCHG; 2020H will be loaded into register pair DE and 0202H into register HL
HLT
Copy H and L registers to the stack pointer
Table 14: SPHL Instruction
SPHL instruction is a one byte instruction.

affected
SPHL None None The instruction loads the contents of the H and L registers into
the stack pointer register, the contents of the H register provide
the high-order address and the contents of the L register provide
the low-order address. The contents of the H and L registers are
not altered.
Example-1: LXI SP, 8088H

LXI H, 9099H
SPHL; 16 bit value of the register pair HL will be loaded into 16-bit stack pointer
register
SPL<=99
SPH<=90
The content of register pair HL is not altered.

Push onto/Pop of the stack

Stack
A stack is a group of memory locations in the R/W memory which is used to store information
temporarily during the execution of a program. Also the stack is used in subroutine calls to store
the return address.
As an example, data generated at a certain point in a program may be needed later in the
program. This data is stored in the stack and retrieved when needed. Because the number of
general purpose registers (GPRs) in a microprocessor is limited–hence not all the temporary data
can be stored in them and this is where the stack plays its part.
The stack is initialized by a 16-bit register, called the stack pointer (SP) register. But initialization
is not a must. If for programs for which any temporary data that are generated can be stored in
GPRs and which don’t require subroutine calls, there is no need to initialize the stack by the SP.
The stack is used by programmer and a system. Programmer uses the stack for storage/retrieval
of data by using the PUSH/POP instructions respectively. On the other hand, the system uses the
stack to store return address whenever subroutine CALL is used.
Stack Initialization
There are two ways to initialize the stack:
(a) Direct way

(b) Indirect way
Example of method (a)
LXI SP, 4400 H; loads the stack pointer with 4400 H so that it points at the memory address
4400 H.
Example of method (b)
LXI H, 16-bit data; load 16-bit data into HL register pair
SPHL; contents of HL register pair is loaded into SP.
In most of the cases the stack pointer is initialized by direct way, but method (b) is sometimes
used when one wants to set the stack pointer by means of programming.
Structure of a stack in 8085 Microprocessor
Stack is a ‘last-in first-out’ or LIFO type of memory. This means that data which is pushed last
into stack is popped out of it first.

Push register-pair onto stack

Table 15: PUSH Instruction
PUSH instruction is a 1 byte instruction.


affected
PUSH Reg. pair None The contents of the register pair designated in the operand are
copied onto the stack in the following sequence. The stack
pointer register is decremented and the contents of the higher
order register (B, D, H, A) are copied into that location. The
stack pointer register is decremented again and the contents of
the low-order register (C, E, L, flags) are copied to that
location.
Example-1: PUSH B
PUSH PSW
Example-2: Assuming the stack pointer SP=1234H, A=55H, Flag Register= 88H, BC= A04FH,
DE= B0A2H and HL = 5089H. Show the contents of the stack as each of the following
instructions is executed.
PUSH PSW
PUSH B
PUSH D
PUSH H
Pop off stack to register pair

POP instruction is a 1 byte instruction.
affected
POP Reg. pair None The contents of the memory location pointed out by the stack
pointer register are copied to the low-order register (C, E, L,
status flags) of the operand. The stack pointer is incremented
by 1 and the contents of that memory location are copied to the
high-order register (B, D, H, A) of the operand. The stack
pointer register is again incremented by 1.
Example-1: POP H
POP PSW

Example-2: Assuming the stack pointer SP=122DH and Content of a stack is as shown below.
Show the contents of the stack and registers as each of the following instructions is executed.
LXI SP, 122DH

POP H
POP D 122D 88H
POP B 122E 55H
POB PSW 122FH 4FH
HLT 1230H A0H
1231H A2H
1232H B0H
1233H 89H
1234H 50H
Fig: Stack memory
Exchange H and L with top of stack

Table 16: XTHL Instruction

affected
XTHL None None The contents of the L register are exchanged with the stack
location pointed out by the contents of the stack pointer register.
The contents of the H register are exchanged with the next stack
location (SP+1); however, the contents of the stack pointer
register are not altered.
Example-1: Assuming stack value at A09CH is 44H and at A09BH is A0H; specify the content
of register pair HL and stack values at memory locations A09CH and A09BH after the following
instruction is being executed.
LXI SP, A09CH

LXI H, F0FEH
XTHL
HLT
Answer
HL<= 44A0H
[A09CH] <=F0H
[A09BH] <=FEH

Output data from accumulator to a port with 8-bit address

affected
OUT 8-bit port address None The contents of the accumulator are copied into the I/O
port specified by the operand.
Example-1: MVI A, 66H

OUT F8H
HLT
Example-2: Load the hexadecimal number FFH in register D and display the number at output
port with the address 20H.
Answer
MVI D, FFH
MOVA, D
OUT 20H
HLT
Input data to accumulator from a port with 8-bit address

affected
OUT 8-bit port address None The contents of the input port designated in the
operand are read and loaded into the accumulator.
Example-1: MVI A, 00H

IN 8CH
HLT
Example-2: If the switch S3 of the input port (in the figure below) connected to the data line D3
is at logic 1 and other switches are at logic 0:

a) Specify the contents of the accumulator when the instruction IN 4FH is executed.
b) Specify the output at port 03H and the contents of register D after executing the
instructions.
MVI B, 00H
MVI A, 99H
IN 4FH
MOV D, A
OUT 03H
HLT
Answer:
a) 08H
b) 08H
Arithmetic Operations
The 8085 microprocessor performs various arithmetic operations, such as addition, subtraction,
increment and decrement. Addition and subtraction operations are performed in relation to the
contents of the accumulator. However, the increment and decrement operations can be performed
in any operand (register or memory).

Addition
The 8085 microprocessor performs addition with 8-bit binary numbers and stores the sum in the
accumulator. Addition can be performed either by adding the contents of a source register or
memory to the contents of the accumulator or a byte value directly to the contents of the
accumulator.
Add register or memory value to accumulator
Operand Flag affected Description

ADD M All flags are The content of the operand (register or memory) is
R modified to reflect added to the contents of the accumulator and the result
the result of the is stored in the accumulator. If the operand is a
addition. memory location, its location is specified by the
contents of the HL registers.
Example -1: Write a program that performs the following functions:
1. Load the number 8BH in register D
2. Load the number located in the memory location 9095H to register C
3. Increment the contents of register C
4. Add the content of registers C and D and display the sum at port 89H
Answer
MVI D, 8BH MVI D, 8BH

LDA 9095H LXI H, 9095H
MOV C, A MOV C, M
MVI A, 01H MVI A, 01H
ADD C ADD C
ADD D ADD D
OUT 89H OUT 89H
HLT HLT
Add register to accumulator with carry
Opcode operand Flag affected Description

ADC M All flags are The contents of the operand (register or memory) and
R modified to reflect the Carry flag are added to the contents of the

the result of the accumulator and the result is stored in the

addition. accumulator. If the operand is a memory location, its
location is specified by the contents of the HL
registers. All flags are modified to reflect the result of
the addition.
Example-1: MVI A, 8DH

MVI B, F0H
MVI C, 01H
ADD B
ADC C
HLT
Add immediate to accumulator
Opcode Operand Flag Affected Description

ADI 8-bit All flags are The 8-bit data (operand) is added to the contents of
data modified to reflect the accumulator and the result is stored in the
the result of the accumulator. All flags are modified to reflect the
addition. result of the addition.
Example: Assume the byte value at memory location 8099H is CFH:
LXI D, 8099H
LDAX D
ADI 45H
HLT
Add immediate to accumulator with carry

ACI 8-bit data All flags are The 8-bit data (operand) and the Carry flag are added
modified to to the contents of the accumulator and the result is
reflect the result stored in the accumulator. All flags are modified to
of the addition. reflect the result of the addition.
Example: Assume the byte values A4H and 39H are found in memory locations 997E, 997FH
respectively. Write a program that adds these values with an immediate value 45H.
Answer:
LDA 997EH
LXI H, 997FH
ADD M
ACI 45H
HLT
Add register pair to H and L registers


DAD Reg. pair If the result is The 16-bit contents of the specified register pair are
larger than 16 added to the contents of the HL register and the sum
bits, the CY flag is stored in the HL register. The contents of the
is set. source register pair are not altered.
No other flags
are affected.
Example-1: Specify the contents of the registers H, L, D and E when the following program is
being executed.
Answer
Mnemonics D E H L
LXI H, 5066H XX XX 50H 66H
LXI D, 4031H 40H 31H 50H 66H
DAD D 40H 31H 90H 97H
HLT
Example-2: Write an 8085 assembly language program that multiply content of register pair HL
by 2.
Answer: LXI H, 16 bit value
DAD H
HLT
Subtraction
The 8085 microprocessor performs subtraction by using the method of 2’s complement. The
value in accumulator register is regarded as the minuend (the number from which to subtract).
The 8085 microprocessor performs the following steps internally to execute subtraction
instruction.
1. Converts subtrahend (the number to be subtracted) into its 1’s complement
2. Add 1 to 1’s complemented to obtain 2’s complement of the subtrahend.
3. Add 2’s complement to the minuend (the contents of the accumulator)
4. Complements the carry flag

Subtract register or memory from accumulator

SUB R All flags are The contents of the operand (register or memory) are
M modified to subtracted from the contents of the accumulator, and
reflect the result the result is stored in the accumulator. If the operand
of the is a memory location, its location is specified by the
subtraction. contents of the HL registers.
Example-1: Register D has 89H and the accumulator has F2H. Write a program that subtracts
the contents of register D from the contents of the accumulator.
Answer
MVI D, 89H
MVI A, F2H
SUB D
HLT
Example-2: Write an 8085 assembly language program that performs the following functions:
1. Load the number 72H in register C and 96H in register B
2. Subtract 96H from 72H
3. Display the answer at port address 8FH
Answer:
MVI C, 72H
MVI B, 96H
MOV A, C
SUB B
OUT 8FH
HLT
Example-3: Write instructions to add the contents of the memory location 8090H to
accumulator, and subtract the contents of the memory location 8091H from the sum. Assume the
accumulator has 40H, the memory location 8090h has 4AH and the location 8091H has F7H.
Answer
MVI A, 40H
LXI H, 8090H
ADD M
MOV B, A
LDA 8091H
MOV C, A
MOV A, B

SUB C
HLT
Subtract source and borrow from accumulator

SBB R All flags are The contents of the operand (register or memory) and
M modified to the Borrow flag are subtracted from the contents of
reflect the result the accumulator and the result is placed in the
of the accumulator. If the operand is a memory location, its
subtraction. location is specified by the contents of the HL
registers.
Example: SBB B or SBB M
Subtract immediate from accumulator

SUI 8-bit data All flags are The 8-bit data (operand) is subtracted from the
modified to contents of the accumulator and the result is stored in
reflect the result the accumulator.
of the
subtraction.
Example:
LXI B, F000H
LDAX
SUI 45H
HLT
Subtract immediate from accumulator with borrow

SBI 8-bit data All flags are The 8-bit data (operand) and the Borrow flag are
modified to reflect subtracted from the contents of the accumulator
the result of the and the result is stored in the accumulator.
subtraction.
Example-1:
MVI A, 30H
SUI 45H
SBI 01H
HLT

Increment register or memory by 1

INR R All flags except a The contents of the designated register or
M carry flag is affected memory) are incremented by 1 and the result is
stored in the same place. If the operand is a
memory location, its location is specified by the
contents of the HL registers.
Example-1: MVI D, 44H

MOV B, D
INR B
HLT
Example-2 Assume the value at memory location F07AH is 7FH. Specify the value of memory
location after INR M instruction is being executed.
Answer
H L Value of memory location F07AH
LXIH, F07AH F0H 7AH 7FH
INR M F0H 7AH 80H
HLT
Increment Register pair by 1

INX R None The contents of the designated register pair are
incremented by 1 and the result is stored in the
same place.
Example-1: Assume byte value at memory location 909FH is 00H and at memory location
90A0H is FFH. What is the content of register B when MOV B, M instruction is being executed?
LXI H, 909FH
INX H
MOV B, M
HLT
Answer: B=FFH
Example-2: Write the instruction to load the number 5020H in the register pair BC. Increment
the number using the instruction INX B and illustrate whether the INX B is equivalent to the
instructions INR B and INR C.

Answer
LXI B, 5020H
INX B
HLT
After the above instruction has been executed register pair BC will contain 5021H.
LXI B, 5020H
INR B
INR C
HLT
Register pair BC will hold 5121H.
Decrement register or memory by 1

DCR R All flags except a The contents of the designated register or memory
M carry flag is affected are decremented by 1 and the result is stored in
the same place. If the operand is a memory
location, its location is specified by the contents
of the HL registers.
Example-1:
MVI C, 00H
MOV B, C
DCR B
MOV C, B
HLT
Example-2: Write instructions that load 40H in memory location 8091H, and decrement the
contents of the memory location 8091H.
Answer:
LXI B 8091H
MVI A, 40H
STAX B
LXI H, 8091H
DCR M
HLT
Decrement Register pair by 1

DCX R None The contents of the designated register pair are
decremented by 1 and the result is stored in the
same place.

Example:
LXI H, 9A70H
DCX H
HLT
Contents of register pair HL after the above instructions have been executed is 9A6FH.
Decimal Adjust Accumulator

DAA None S, Z, AC, P, CY The contents of the accumulator are changed from
flags are altered to a binary value to two 4-bit binary coded decimal
reflect (BCD) digits. This is the only instruction that uses
the results of the the auxiliary flag to perform the binary to BCD
operation conversion, and the conversion procedure is
described below.
 If the value of the low-order 4-bits in the
accumulator is greater than 9 or if AC flag
is set, the instruction adds 6 to the low-
order four bits.
 If the value of the high-order 4-bits in the
accumulator is greater than 9 or if the
Carry flag is set, the instruction adds 6to
the high-order four bits.
Example: obtain the value after DAA instruction is executed on the following additions.
a) MVI A, 03H b) MVI A, 09H c) MVI A, 08H

MVI C, 05H MVI B, 06H MVI D, 05H
ADD C ADD B ADD D
DAA DAA DAA
HLT HLT HLT
Answer
a) 08 in decimal
b) 15 in binary coded decimal
c) 13 in binary coded decimal
BCD Subtraction

When subtracting two BCD numbers, the instruction DAA cannot be used to decimal adjust the
result of two packed BCD numbers. The DAA instruction applies only to addition. Therefore, it
is necessary to device a procedure to subtract two BCD numbers. Two BCD numbers can be
subtracted using the procedure of 100’s complements.
To subtract two BCD numbers, in short add 100’s complement of the subtrahend to a minuend
and then adjust it using DAA instruction.
Example: 82-48 (= 34) can be performed as follows:
100’s complement of 48 is 52 i.e. 100-48=52
Then add it with the minuend (82)
82 + 52 = D4H, the higher nibble is greater than 9, so add 60H.
D4H + 60H = 1/34, discard the carry => 34H
However, in 8-bit microprocessor, it is not possible to find 100’s complement of a subtrahend

(100BCD requires twelve bits). Therefore, in writing a program, 100’s complement is obtained by
finding 99’s complement and adding 01.
Example: Subtract 01 from 90 in BCD
MOV B, 90H
MOV C, 01H
MVI A, 99H
SUB C, Find 99’s complement of Subtrahend
INR A, Find 100’s complement of subtrahend
ADD B, Add minuend to 100’s complement of subtrahend
DAA, Adjust for BCD
HLT

BRANCHING INSTRUCTIONS
Jump instructions
Jumps are of two types namely; unconditional and conditional.
Jump Unconditionally
The unconditional jump instruction is a 3-byte instruction with the first byte containing the
Opcode and the second and the third bytes containing the address. When the unconditional jump
instruction is executed, the second and the third address bytes are loaded in the PC counter. The
microprocessor will fetch next instruction from the memory at the new address.

JMP instruction is three byte instruction.

Affected
JMP 16-bit address None The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand.
Example-1: Identify the memory locations that are cleared by the following instructions:
MVI B, 00H
LXI H, 9005H
JMP XXXX
MOV M, B
XXXX: INX H
MOV M, B
INX H
INX H
MOV M, B
HLT
Jump conditionally
All conditional jump instructions are three byte instructions. The program sequence is transferred
to the memory location specified by the 16-bit address given in the operand based on the
specified flag of the PSW as described below. I.e. conditional jump instructions are executed if
the specified condition is satisfied or otherwise control proceeds in the sequence.
Opcode Operand Flag status Flag Affected Description

JC CY = 1 None Jump if Carry
JNC CY = 0 None Jump if no Carry
JP S=0 None Jump if positive
JM S=1 None Jump if minus
JZ Z=1 None Jump if zero
JNZ Z=0 None Jump if no zero
JPE P=1 None Jump if parity is even
JPO P=0 None Jump if parity is odd
Example-1 Write an assembly language program to add N byte binary numbers stored from
location X+1, where N is stored at location X. Store the result in location Y and Y+1.
Store the program starting from F000H
Store the count at location F100H

Store the data starting from F101H

Store the result in location F200H and F201H
Answer
LXI H, F000H
MOV C, M
MVI B, 00H
MVI A, 00H
YYYY: INX H
ADD M
JNC XXXX
INR B
XXXX: DCR C
JNZ YYYY
STA F200H
STA F201H
HLT
Example-1: Write an assembly language program to find the product of two unsigned binary
numbers stored at location X and X+1 using successive addition.
Store the program starting from 9000H

Store the data in memory location F101H and F102H
Store the result in memory locations F203H and F204H
Answer
LXI D, F101H
LDAX D
INX D
MOV C, A
LDAX D
MVI E, 00H
MOV B, A
SUB A
YYYY: ADD B
JNC XXXX
INR E
XXXX: DCR C
JNZ YYYY
STA F103H

MOV A, E
STA F104H
HLT
Example-3: Explain how many times the following loop will be executed.
MVI B, 02H
MVI A, FCH
XXXX: ADD B
JC XXXX
STA 809FH
HLT
Example-4: The following instructions are intended to clear five memory locations starting from
memory location F00AH. Explain why a large memory block will be cleared.
LXI H, F00AH
YYYY: MVI B, 04H
MVI M, 00H
INX H
DCR B
JNZ YYYY
LOGICAL INSTRUCTIONS
Compare instructions
The 8085 instruction set has two types of compare operations: CMP and CPI.
 CMP: Compare with accumulator
 CPI: Compare immediate value with accumulator
The microprocessor compares a data byte (memory or register value) with the contents of the
accumulator by subtracting the data from A, and indicates whether the data byte is <, >, or = by
modifying the flags. However the contents are not modified.
Compare register or memory value with accumulator

-CMP is a one byte instruction.
CMP M Carry and The contents of the operand (register or memory) are compared
R Zero flags are with the contents of the accumulator. Both contents are
affected preserved. The result of the comparison is shown by setting the
flags of the PSW as follows:
if (A) < (R/M): carry flag is set
if (A) = (R/M): zero flag is set
if (A) > (R/M): carry and zero flags are reset

Example-1: 20 values are stored in memory locations starting at F00FH. Write an 8085 ALP that stores
value between 30H and 45H exclusive starting at F100H.
Answer
MVI C, 14H
LXI H, F00FH
LXI D, F100H
Again: MVI A, 30H
CPM M
JNC NXT
MVI A, 45H
JNC NXT
MOV A, M
STAX D
INX D
NXT: INX H
DCR C
JNZ Again
HLT
Compare immediate value with accumulator

-CPI is a two byte instruction.
CPI 8-bit data Carry and Zero The second byte (8-bit data) is compared with the contents of
flags are the accumulator. The values being compared remain
affected unchanged. The result of the comparison is shown by setting
the flags of the PSW as follows:
if (A) < immediate 8-bit data: carry flag is set
if (A) = immediate 8 bit data: zero flag is set
if (A) > immediate 8-bit data: carry and zero flags are reset
Example-1: A set of current readings is stored in memory locations starting at F000H. The end
of the data byte is indicated by the data 00H. Add the set of readings. The result may be larger
than FFH. Write a program that displays the entire sum at port addresses F1H and F2H.
LXI H, F000H
SUB A
MOV B, A
MOV C, B
NXTR: MOV A, M
CPI 00H
JZ display
ADD B
JC NXT
INR C

NXT: MOV B, A
INX H
JMP NXTR
Display: MOV A, B
OUT F1H
MOV A, C
OUT F2H
HLT
Logical AND register or memory with accumulator

-ANA is a one byte instruction.
ANA M S, Z, P are The contents of the accumulator are logically ANDed with
R modified to reflect M the contents of the operand (register or memory), and the
the result of the result is placed in the accumulator. If the operand is a
operation. CY and memory location, its address is specified by the contents of
AC are reset. HL registers.
Example-1: Write an 8085 ALP that masks lower nibble of 10 values found in memory location
starting F000H.
MVI C, 0AH
LXI H, F000H
NXT: MVI A, F0H
ANA M
MOV M, A
INX H
DCR C
JNZ NXT
HLT
Logical AND immediate with accumulator

-ANI is a two byte instruction.
ANI 8-bit value S, Z, P are The contents of the accumulator are logically ANDed with
modified to reflect the 8-bit data (operand) and the result is placed in the
the result of the accumulator.
operation. CY and
AC is reset.
Example-1:
MVI B, 00H
MOV A, B

ANI FFH
HLT
Exclusive OR register or memory with accumulator

-XRA is a one byte instruction.
XRA R S, Z, P are modified The contents of the accumulator are Exclusive
M to reflect the result ORed with the contents of the operand (register or
of the operation. CY memory), and the result is placed in the
accumulator. If the operand is a memory location,
and AC are reset.
its address is specified by the contents of HL
registers.
Example-1: What operations can be performed by using the instruction XRA A? Specify the
status of Z and CY flags.
XRA A will clear contents of register A. I.e. A=00H. Z = 1 and CY = 0
Exclusive OR immediate with accumulator

-XRI is a two byte instruction.
XRI 8-bit value S, Z, P are modified to reflect The contents of the accumulator are
the result of the operation. CY Exclusive ORed with the 8-bit data (operand)
and AC are reset. and the result is placed in the accumulator
Logical OR register or memory value with accumulator

-ORA is a one byte instruction.
ORA M S, Z, P are modified to The contents of the accumulator are logically ORed
R reflect the result of the with the contents of the operand (register or
operation. CY and AC memory), and the result is placed in the accumulator.
are reset. If the operand is a memory location, its address is
specified by the contents of HL registers.
Example-1: Identify the contents of the accumulator and the flag status as the following instructions are
executed.
A S Z CY
MVI A, 82H 82H X X X
ORA A 82H 1 0 0
CPI B3H 82H 1 0 1
HLT

Example-2: Explain the type of the number that can be displayed at the output port 00H.
LXI H, 9000H
MVI C, 20H
NXT: MOV A, M
ORA A
JP Display
XRA A
Display: OUT 00H
INX H
DCR C
JNZ NXT
HLT
Logical OR immediate with accumulator

-ORI is a two byte instruction.
ORI 8-bit value S, Z, P are modified to The contents of the accumulator are logically
reflect the result of the ORed with the 8-bit data (operand) and the result
operation. CY and AC are is placed in the accumulator.
reset.
Example-1: Write an 8085 ALP that reads the switch connected to port address FFH continuously, set
D6, D2 and D1 of the readings and display it at port address 50H.
NXT: IN FFH
ORI 46H
OUT 50H
JMP NXT
HLT
Rotate accumulator left

-RLC is a one byte instruction.
RLC None CY is modified according Each binary bit of the accumulator is rotated left
to bit D7. S, Z, P, by one position. Bit D7 is placed in the position
AC are not affected of D0 as well as in the Carry flag.
Example-1: Explain the mathematical function that is performed by the following instructions.
MVI B, 05H; Load five into register B
MOV A, B; Copy the value in B to A
RLC ; Rotate left through carry once: - A contains 0AH
MOV B, A; Copy the value contained in A to B
RLC ; Rotate left through carry once: A contains 14H
RLC ; Rotate left through carry once: A contains 28H
ADD B ; add 28H and 0AH: A=32H which is 50 in decimal
HLT

Therefore, the mathematical function of the above segment of codes is multiplying by 10 the value
initially contained in register B.
Rotate accumulator right

-RRC is a one byte instruction.
RRC None CY is modified according Each binary bit of the accumulator is rotated right
to bit D0. S, Z, P, AC are by one position. Bit D0 is placed in the position of
not affected D7 as well as in the Carry flag.
Example-1: Assume the accumulator contents are AAH and carry flag=0. Illustrate the accumulator
contents after the execution of RRC instruction twice.
Answer
A= 10101010 in binary and CY=X
RRC
A=01010101, CY =0
RRC
A=10101010, CY =1
Rotate accumulator left through carry

-RAL is a one byte instruction.
RAL None CY is modified according Each binary bit of the accumulator is rotated left by
to bit D7. S, Z, P, AC are one position through the Carry flag. Bit D7 is
not affected. placed in the Carry flag, and the Carry flag is
placed in the least significant position D0.
Example-1: Assume the accumulator contents are AAH and CY =0. Illustrate the accumulator
contents after the execution of the instruction RAL twice.
Answer
A=10101010, CY =0
RAL
A=01010100, CY =1
RAL
A=10101001, CY=0
Rotate accumulator right through carry

-RAR is a one byte instruction.
RAR None CY is modified according Each binary bit of the accumulator is rotated right
to bit D0. S, Z, P, AC are by one position through the Carry flag. Bit D0 is
not affected. placed in the Carry flag, and the Carry flag is
placed in the most significant position D7.

Example-1: Identify the contents of register A after the last RAR instruction is being executed.
MVI A, 81H
STC
RAR
CMC
RAR
HLT
Answer
A=10000001, CY=1
RAR
A=11000000, CY=1
CMC
A=11000000, CY=0
RAR
A=01100000, CY=0
Complement accumulator
CMA None No flags are affected. The contents of the accumulator are complemented.
Example-1:
MVI A, 55H
CMA
ADD 55H
HLT
Complement carry
CMC None Carry flag is affected. No other flags The Carry flag is complemented.
are affected.
Example-1:
MVI FEH
ADI 02H
CMC
RAL
HLT
Set Carry

STC None The Carry flag is set to 1. No other Set carry flag to 1.
flags are affected.
Machine CONTROL INSTRUCTIONS
No Operation

NOP None None No operation is performed. The instruction is
fetched and decoded. However no operation is
executed.
Example-1
MVI C, FFH
NXT: NOP
DCR C
JNZ NXT
HLT
Halt

HLT None None The CPU finishes executing the current
instruction and halts any further execution. An
interrupt or reset is necessary to exit from the halt
state.
Example: HLT
Disable interrupts

DI None No flags are The interrupt enable flip-flop is reset and all the
affected. interrupts except the TRAP are disabled.
Example: DI

Enable interrupts

No flags are The interrupt enable flip-flop is set and all
affected. interrupts are enabled. After a system reset or the
acknowledgement of an interrupt, the interrupt
enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to re-
enable the interrupts (except TRAP).
Example: EI
Addressing modes of 8085
The 8085 has 5-addressing modes:
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Inherent or Implied Addressing
Direct Addressing Mode
In this addressing mode, the operand resides in the memory address directly specified as part of
the instruction. Instructions included under a direct addressing mode require three bytes of
storage: one for the instruction code, and two for the 16-bit address.
Example: Jump instructions include a 16-bit address as part of the instruction. For example, the
instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current
contents of the program counter with the new value 1000H.
Example-2:
LDA F00FH
STA F000H
Register Indirect Addressing Mode

Register indirect instructions reference memory via a register pair. I.e. In this addressing mode a
register pair of the microprocessor contains the address of the operand in the memory.
Example-1: The instruction MOV M, C moves the contents of the C register into the memory
address stored in the H and L register pair.

Example-2: The instruction LDAX B loads the accumulator with the byte of data specified by
the address in the B and C register pair.
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself.
Example-1: The instruction CPI 46H may be interpreted as ‘compare the contents of the
accumulator with the 46H. When assembled, this instruction has the hexadecimal value FE43.
Hexadecimal 43 is the internal representation for the letter C. When this instruction is executed,
the processor fetches the first instruction byte and determines that it must fetch one more byte.
The processor fetches the next byte into one of its internal registers and then performs the
compare operation. Notice that the names of the immediate instructions indicate that they use
immediate data.
Example-2: The MVI (move immediate) instruction can move its immediate data to any of the
working registers including the accumulator or to memory. Thus, the instruction MVI D, OFFH
moves the hexadecimal value FF to the D register.
Example-3: The LXI instruction (load register pair immediate) is even more unusual in that its
immediate data is a 16-bit value. This instruction is commonly used to load addresses into a
register pair. As mentioned previously, your program must initialize the stack pointer; LXI is the
instruction most commonly used for this purpose. The instruction LXI SP, 3OFFH loads the
stack pointer with the hexadecimal value 30FF.
Implied Addressing Mode

The addressing mode of certain instructions is implied by the instruction’s function. For
example, the STC (set carry flag) instruction deals only with the carry flag, the DAA (decimal
adjust accumulator) instruction deals with the accumulator.
Register Addressing Mode

In this addressing mode, the operand resides in the 8-bit register of the microprocessor. With
these instructions, you must specify one of the registers A through E, H or L as well as the
operation code. With these instructions, the accumulator is implied as a second operand. For
example, the instruction CMP E may be interpreted as 'compare the contents of the E register
with the contents of the accumulator. Most of the instructions that use register addressing deal
with 8-bit values. However, a few of these instructions deal with 16-bit register pairs. For
example, the PCHL instruction exchanges the contents of the program counter with the contents
of the H and L registers.
Subroutine
A subroutine is a group of instructions written separately from the main program to perform a
function that occurs repeatedly in the main program.
Example-1:
MVI A, 80H

OUT CWR
MVI A, 01H
OUT PORT A
LXI H, FFFFH
XX : DCX H
MOV A, L
ORA H
JNZ XX
MVI A, 02H
OUT PORT A
LXI H, FFFFH
XY: DCX H
MOV A, L
ORA H
JNZ XY
MVI A, 03H
OUT PORT A
LXI H, FFFFH
YX: DCX H
MOV A, L
ORA H
JNZ YX
HLT
The following segment of code is repeated three times. Therefore, subroutine is used to avoid
such type repetition.
LXI H, FFFFH
TT: DCX H
MOV A, L
ORA H
JNZ TT
8085 uses two unconditional branching instructions to implement subroutine: CALL and RET
instructions.
Unconditional CALL instruction

It is a three byte instruction.

CALL 16-bit address None The call instruction is used in main program to call
the subroutine written outside the main program. The

program sequence is transferred to the memory

location specified by the 16-bit address given in the
operand. Before the transfer, the address of the next
instruction after call (the contents of the program
counter) is pushed on top of a stack.
Unconditional RET instruction
It is a one byte instruction.

RET None None When Ret instruction is executed at the end of the
subroutine, the sequence of execution is transferred
to the main program. The two bytes from the top of
the stack are copied onto the program counter (PC),
and program execution begins at the new address.
Example-2: illustrate the exchange of information between the stack and the program counter for
the following program if the available user memory ranges from 2000H to 23FFH.
Memory address instructions Memory address Instructions

2000H LXI SP, 2400H 2070H Start of a subroutine
. . . .
. . . .
. . . .
2040H CALL 2070 207FH RET

2041H
2042H
2043H NEXT instruction
. .
. .
. .
205FH HLT
When the processor encounters the CALL 2070H, the processor automatically pushes 20H and
43H in 23FFH and 23FEH respectively. PC will hold 2070H. At the end of the subroutine the
processor will execute RET instruction and pops the value on top of the stack to the PC counter
and continue executing the instructions in the main program.

Example-3: Example one can be implemented as follows:
Starting Address of Starting Address of

main program Subroutine
XXXX MVI A, 80H YYYY LXI H, FFFFH
OUT CWR Tt: DCX H
MVI A, 01H MOV A, L
OUT Port A ORA H
CALL YYYY JNZ Tt
MVI A, 02H RET
OUT Port A
CALL YYYY
MVI A, 03H
OUT Port A
CALL YYYY
HLT
What happens when a subroutine is called?
1. It stores the current contents of the program counter in a stack
2. Decrements the value of the SP by 2
3. Loads the 16-bit address operand which is available in the CALL instruction to the PC ( Program
Counter)
4. Microprocessor switches to the subroutine and executes it.
5. At the end of the subroutine execution, a single instruction tells the microprocessor original
contents of the PC (Program Counter)

6. Accordingly it returns back to the main program
Conditional call and Return instruction
The conditional call and return instructions are based on-four flag conditions: Carry, Zero, sign and parity
flags. The condition is tested by checking the respective flags.
Call conditionally
All conditional call instructions are three byte instruction and have a 16-bit address operand.
The program sequence is transferred to the memory location specified by the 16-bit address given in the
operand based on the specified flag of the PSW as described below. Before the transfer, the address of the
next instruction after the call (the contents of the program counter) is pushed onto the stack.
Example: CZ 2034H or CZ XYZ
Opcode Description Flag Status

CC Call on Carry CY = 1
CNC Call on no Carry CY = 0
CP Call on positive S=0
CM Call on minus S=1
CZ Call on zero Z=1
CNZ Call on no zero Z=0
CPE Call on parity even P=1
CPO Call on parity odd P=0
Return from subroutine conditionally

All conditional return instructions are one byte instructions.
The program sequence is transferred from the subroutine to the calling program based on the specified
flag of the PSW as described below. The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
Example: RZ
Opcode Description Flag Status

RC Return on Carry CY = 1
RNC Return on no Carry CY = 0
RP Return on positive S=0
RM Return on minus S=1
RZ Return on zero Z=1
RNZ Return on no zero Z=0
RPE Return on parity even P=1
RPO Return on parity odd P=0
Example-4: Write an 8085 ALP that reads value through Ports A, B and C of U4 of 8255 PPI and sends to
ports A, B, and C of U3 of 8255 PPI after performing the following manipulation continuously.
outU3= (inputU4 +33H)*10H/24H

Solution:
Starting Address of Starting Address of

main program Subroutine
XXXX MVI A, 9BH YYYY ADI 33H
OUT DBH MVI C, 0FH
MVI A, 80H MOV B, A
OUT F3H Add: ADD B
Again: IN D8H DCR C
CALL YYYY JNZ Add
OUT F0H Sub: SUI 24H
CALL YYYY INR C
IN D9H CPI 24H
OUT F1H JNC Sub
CALL YYYY MOV A, C
IN DAH RET
OUT F2H
JMP Again
Types of Subroutine
1. Multiple-calling of a subroutine
Subroutines are normally called more than once by the main program. Calling a subroutine more than
once by the main program is called multiple calling of a subroutine.

2. Nesting of subroutines
The process of a subroutine calling a second subroutine and the second subroutine in its turn
calling a third one and so on is called nesting of subroutines.
Theoretically speaking, the number of subroutines that can be called by this process is infinite
but, in practice it is limited by the size of memory.
Nested subroutines can be classified as
 Re-entrant subroutine
In nested subroutines, many subroutines are there. In such a case, if a latter subroutine
calls an earlier one, then it is known as re-entrant subroutine. As an example, say a main
program has two subroutines. The main program calls subroutine 1, then subroutine 1
calls subroutine 2. If now subroutine 1 is called from subroutine 2, then this falls under the
category of re-entrant subroutines.

Recursive subroutine
A recursive subroutine is a subroutine which is called by itself and is used with complex data
structures, known as ‘trees. For the flow diagram shown, if the subroutine is called with n = 4
(known as ‘recursive depth’), then until n becomes 0 it will stay within the recursive subroutine.
Below is shown the flow diagram for a recursive subroutine.
If n _ 0
Decrement n
Call SR recursive
else
return.

3. Multiple ending subroutines
Multiple ending subroutine is a subroutine that has one or more conditional return
instruction and one unconditional return instruction.
Techniques of ending a subroutine
There are two methods of ending a subroutine—multiple ending and common ending. The
example of each type follows:

Example: Write an 8085 ALP that converts 32 ASCII characters available starting at 9000H
memory location to their binary equivalent. Write the converter function outside the main
program.
Answer:
LXI H, 9000H
MVI C, 10H
NXT: MOV A, M
CALL TTYY
INX H
DCR C
JNZ NXT
HLT
TTYY: SUI 30H

CPI 0AH
RC
SUI 07H
RET
Parameter passing
Subroutines are scattered at many places in the memory and that they may be called from
different locations in the main program. In such cases, various types of information/data re
exchanged between the main program and the subroutine. This ‘passing’ of data/address
variable is referred to as passing parameters to the subroutine.
There are four ways in which this ‘passing’ can be done, as mentioned below:
(a) by using registers
(b) by using pointers
(c) by using memory
(d) by using stack.

Counter and Time Delays

Counter
A counter is designed by loading an appropriate number into one of the registers and using the
INR or DCR instructions. A loop is established to update the count, and each count is checked to
determine whether it has reached the final number, if not, the loop is repeated.
Time Delay
A register is loaded with a number depending on the time delay required, and then the register is
decremented until it reaches zero by setting up a loop with a conditional jump instruction. The
loop causes the delay, depending upon the clock period of the system.
Calculating Clock Period

The period is calculated from clock frequency of a microprocessor.
Clock Period (T) =1/clock frequency of a system.
Each instruction has its own T-states (Clock Periods). Using these T-states, one can calculate the
time required to execute each instruction.
Example-1: Calculate the time required to execute MVI instruction on 8085-based

microcomputer. The instruction MVI requires 7 T-states.
Answer
Given: Clock frequency of the system= 2MHz
T-states (Clock periods) = 7
T=1/2MHz=0.5µ second
Time to execute MVI= 7*0.5µ second= 3.5µ seconds
Important points
 Every instruction requires some time to be executed. The amount of time is not constant.
It varies from instruction to instruction. The time required to execute each instruction is
referred as T-states or Clock periods.
 Execution of instruction depends on the speed (clock frequency) of the microprocessor.
Execution time is small for processor with large clock frequency and vise versa.\
Example-2: Calculate the time required to execute the following segment of codes on
8085 microprocessor with clock frequency 4MHz. assume the value at memory location
899FH is BCH.

T-state required
MVI B, 34H 7
MOV A, B 4
LXI H,899FH 10
ADD M 7
JC NXT 7 if condition is not true
MVI A, 00H Otherwise 10
OUT FFH 10
MVI A, 01H 7
NXT:OUT FFH 10
HLT 5
Delay calculation using register pair
Example-3: Calculate the time required to execute the following functions. Clock frequency=
4MHZ.
T-state required
LXI B, 0064H 10
Nxt: DCX B 6
MOV A, B 4
ORA C 4
JNZ NXT 7 if condition is not true
HLT Otherwise 10
5
Answer
T=1/F=1/4MHz=0.25 µs
T-states outside the loop = 15
T-sates inside the loop = 24 for 99 times and 21 for one times
Time required to executed instructions outside the loop = 15 * 0.25 µs = 3.75µs
Time required to executed instructions inside the loop = (24 * 99+21) *0.25µs=599.25µs
Total time = 599.25µs + 3.75µs = 603µs

Delay Calculation using loop within loop Technique
Example-4: Calculate the time required to execute the following segment of codes on a processor
with clock frequency of 2MHz.
T-state required
MVI D, 38H 7
NXT1: MVI B, FFH 7
NXT2: DCR B 4
JNZ NXT2 10/7
DCR D 4
JNZ NXT1 10/7
HLT 5
Answer
Inner loop is controlled by register B
Outer loop is controlled by register C
T=1/2MHz = 0.5µs
Time delay for the inner loop
Inner loop is executed 255 times
T-inner = 255*14*0.5µs – 3*0.5µs = 1785µs – 1.5µs = 1783.5µs
Time delay for the outer loop
Inner loop is executed 56 times
T-outer= 56 *(1783.5µs + 0.5µs*21) – 3*0.5µs= 100464µs-1.5µs=100462.5µs
Time required executing instructions outside the loop
12*0.5µs = 6µs
Total time = 6µs + 100462.5µs= 100468.5µs= 100.469ms
Example-5: Calculate the execution time required to execute the following instructions:
T-state required
LXI B, 12FFH 10
NXT: DCX B 6
XTHL 16
XTHL 16
NOP 4
NOP 4
MOV A, C 4
ORA B 4

JNZ NXT 10/7

HLT 5
Example-6: Calculate the count value to be loaded on register B to obtain a 94.5µs delay on a
processor with 2MHz. [Express the value in hexadecimal]
T-state required
MVI B, count 7
NXT: NOP 4
NOP 4
NOP 4
NOP 4
DCR B 4
JNZ NXT 10/7
HLT 5
Answer
Time delay = No T-states *count*period + No T-states outside the loop*period
94.5µs= 30*Count*0.5µs + (12-3)*0.5µs
94.5µs-4.5µs = Count*15µs
90µs=Count*15µs
Count = 6
B=06H
Example-7: Specify the number of times the following loop will be executed.
a) MVI A, 17H
NXT: ORA A
RLC
JNC NXT
HLT
Answer
4 times
b) MVI A, 17H
NXT: RLC
ORA A
JNC NXT
HLT
Answer

Infinite times because logical OR instructions reset the carry flag.

c) LXI B, 0005H
NXT: DCX B
NOP
JNC NXT
HLT
Answer
Infinite times because DRX instruction resets the carry flag
d) MVI A, 64H
NXT: DCR A
NOP
JNC NXT
HLT
Answer
Infinite times because DCR instruction resets the carry flag
Example-8: Write a program to generate a continuous square wave with the period of 500µs.
Assume the system clock period is 325ns, and use bit D0 to output the square wave.
Answer
T-state required
MVI D, 55H 7
ROTATE: MOV A, D 4
RLC 4
MOV D, A 4
ANI 01H 7
OUT FFH 10
MVI B, Count 7
Delay: DCR B 4
JNZ Delay 10/7
JMP ROTATE 10
HLT
5
On-time=Off-time=250µs
On-time = (Count*14 - 3 + 46) * 325ns

250µs = (Count*14 + 43)*325ns

(250/325)*1000= (Count*14 + 43)
769.2308-43=Count*14
Count =726.2308/14= 52 in decimal
Count = 34H
Example-9: Write a program to generate a rectangular wave with a 200µs on-period and a 400µs
off-period. [Clock frequency of the system = 4MHz
Answer
Period = 1/ (System Clock Frequency)

Period = 1/4MHz
Period= 0.25µs
T-state required
NXT: MVI A, 01H 7
OUT FFH 10
MVI B,Count1 7
NXT1: NOP 4
NOP 4
NOP 4
DCR B 4
JNZ NXT1 10/7
MVI A, 00H 7
OUT FFH 10
MVI C, Count2 7
NXT2: NOP
4
NOP
4
NOP
4
DCR C
4
JNZ NXT2
JMP NXT 10/7
HLT 10
5

On-Period = (Count1 - 1)*NoT-States*Period + (NoT-states - 3)*period

NoT-states= 50
200µs = (Count1 - 1)*50*0.25µs + 47*0.25µs
200µs = (Count1 - 1)*12.50µs + 11.75µs
200µs = Count1 *12.50µs -12.50µs + 11.75µs
200µs = Count1 *12.50µs -0.75µs
200.75µs = Count1 *12.50µs
Count1 = 16.06
B= 10H
Off-Period = (Count2 - 1)*(NoT-States)*Period + (NoT-states - 3)*period

NoT-states= 60
400µs = (Count2 - 1)*60*0.25µs + 57*0.25µs
400µs = (Count2 - 1)*15µs + 14.25µs
400µs = Count2 *15µs -15µs + 14.25µs
400µs = Count2*15µs -0.75µs
400.75µs = Count2 *15µs
Count2 = 26.72
C = 1BH

8255 Programmable Peripheral Interface (PPI)
The chip is a 40-pin chip. It is a general purpose used for interfacing parallel IO devices to the
microprocessor. The microprocessor accepts or sends data to or from the IO devices through the interface
modules known as ports. It has three separately accessible ports: A, B, and C. The width of each port is 8-
bit. The ports are divided into as Group-A and Group-B ports: Port-A and 4 MSBs of Port-C together
form Group-A where as Port-B and 4 LSBs of Port-C form Group-B. 8255 PPI has one programmable
register and is called programmable register. It is used to configure the ports in different modes.
Pin layout
Descriptions of each pin and control units
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. Data is
transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control
words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control
or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands
to both of the Control Groups.

Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU
"outputs" a control word to the 8255. The control word contains information such as "mode", "bit set",
"bit reset", etc., that initializes the functional configuration of the 8255. Each of the Control blocks
(Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control
words" from the internal data bus and issues the proper commands to its associated ports.
Pin description
Control sections (RD, WR, RESET and CS)
CS (Chip Select bar)
A "low" on this input pin enables the entire 8255. While CS selects the entire chip, it is A0 and A1 that
selects the specific port. A0 and A1 are used to access ports A, B, C or the control register according the
table below.
CS bar A1 A0 SELECTION
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 CONTROL
1 X X 8255 is disabled
RD (Read bar)
This control signal enables the read operation. A "low" on this input pin enables 8255 to send the data or
status information to the microprocessor on the data bus. In essence, it allows the microprocessor to "read
data from" the 8255 PPI port.
WR (Write bar)
This control signal enables the write operation. A "low" on this input pin enables the microprocessor to
write data or control words into the 8255 PPI port.
RESET
This is an active high signal input to the 8255. A "high" on this input initializes the control register to 00H
and all ports (A, B, C) are initialized as the input ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional
characteristics by the system software but each has its own special features or "personality" to further
enhance the power and flexibility of the 8255.
Port A (PA0-PA7)

This 8 bit port can be programmed as input or all pins as output or all pins as bidirectional port.
Port B (PB7-PB0)
This 8 bit port can be programmed all pins as input or all pins as output.
Port C (PC7-PC0)
One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be
used for the control signal output and status signal inputs in conjunction with ports A and B.
Data Pins (D7-D0)
These pins are connected with the data pins of the microprocessor and used for transferring data between
8255 chip and the microprocessor.
Block Diagram of the 8255 Programmable Peripheral Interface (PPI)

Control word
The control word format of the 8255 is shown in the figure above. The contents of the control register are
called the control word that specifies the input/output functions of each port. The control word can be
accessed to write the control word by selecting AD0 and AD1, in high condition i.e. both ON. This
register is not available for read operation.
Essential steps required to configure the ports
1. Determine address of port A, B, C and control register
2. Write the control word in the control word register
3. Write input/output instructions in order to communicate through ports A, B and C.
Mode Definition Format

BSR (Bit Set/Reset) Mode
To configure the control register in BSR mode, set D7 of the control register to zero (D7=0). In BSR (Bit
Set/Reset) mode, the bits of port C are programmed individually.
BSR Control Word
D3 D2 D1 Pin of
port C
0 0 0 Pin 0
0 0 1 Pin 1
0 1 0 Pin 2
0 1 1 Pin 3
1 0 0 Pin 4
1 0 1 Pin 5
1 1 0 Pin 6
1 1 1 Pin 7

Example-1: Write a program that configures the control register in BSR mode, sets PC5 and Pc3 and then
reset them after some delay.
Solution
To set pin 5 of port C: 0000 1011 = 0BH

To reset pin 5 of port C: 0000 1010 = 0AH
To set pin 5 of port C: 0000 0111 = 07H
To reset pin 5 of port C: 0000 0110 = 06H
MVI C, FFH
MVI A, 0BH
OUT CWR
MVI A, 07H
OUT CWR
NXT: NOP
NOP
NOP
DCR C

JNZ NXT
MVI A, 0AH
OUT CWR
MVI A, 06H
OUT CWR
HLT
Programmable Modes of PPI (when D7=1)
Mode 0 (Simple input/output mode)

This mode is the basic input/output mode. In this mode any ports A, B, and C can be
programmed as input or output. Note that in this mode a given port cannot be both input
and output port at the same time.
One major characteristic of port C is that one can program PC0-PC3 (CL) and PC4-PC7
(CU) independent of each other.
Example-1: Configure 8255 as follows: Port A as input in mode 0, Port B as output in

mode 0, and all pins of Port C as output in mode 0. Determine the contents of the control
register and program the ports to input data from Port A and send it to both B and C.
Answer
a) Contents of the control register
D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 0 0 0

b) MVI A, 90H
OUT CWR
IN Port A
OUT Port C
OUT Port B
HLT
Example-2: Form the control word and write an 8085 ALP to make port a as output port
in mode 0 and the reset of the port as the input ports in mode 0.
Answer
a) Contents of the control register
D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 1 0 1 1

b) MVI A, 8BH
OUT CWR
HLT
Example-3: Configure the ports of 8255 as follows: Port A as input, Port B as output,
PC0-PC3 as input, and PC4-PC7 as output in mode 0. Determine the content of the
control register and write an 8085 ALP to get data from port A and send it to Port B. In
addition, input data from PCL and send it out through PCU.
a)
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 0 0 1
b)
MVI A, 91H
OUT CWR
IN Port B
OUT Port B
IN Port C
ANI 0FH
RLC
RLC
RLC
RLC
OUT Port C
HLT
Example-4: Write an 8085 ALP to toggle all bits of PA continuously with some delay in
mode 0. [Configure all ports as output port and use Port A to send data]
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0
b) MVI A, 80H
OUT CWR
MVI A, AAH

Again: OUT Port A

MVI C, FFH
NXT: NOP
NOP
NOP
DCR C
JNZ NXT
RLC
JMP again
HLT
Example-5: write an 8085 ALP to send data to the DAC to generate a stair-step ramp in
mode 0. [Configure all ports as output port and use Port A to send data]
Answer
a)
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0
b)
MVI A, 80H
OUT CWR
MVI A, 00H
Again: OUT Port A
MVI C, FFH
NXT: NOP
NOP
NOP
DCR C
JNZ NXT
ADI 11H
CPI FFH
JNZ Again
HLT
Exercise-1: Write an 8085 ALP that generates the following signals on the oscilloscope.

a)
b)
c)
d)
Seven Segment LED Display

Seven segment LED display is used to provide information to users. They are commonly used in
calculators and other house hold items. The image shown below is typical seven segment display
with each of the segments labeled with letters ‘a’ through ‘g’. To display digits on these displays
turn on some of the LEDS. For example, when you illuminate segments ‘a’ and ‘c’, our eye
perceives it as number ‘1’. Light up ‘a’, ‘b’, and ‘c’, our eye will see that the number 7.

Common cathode or Anode wiring

Each segment of the 7-segment display is an individual Light Emitting Diode (LED). An LED is
simply a diode that emits light when current flows.
A seven segment display may have 7 or 8 LEDS on the chip. 7 segment LED is categorized as:
 Common cathode type

 Common Anode type
Common Cathode Wiring

The common point is tied to logic ‘0’ and to display a character; logic ‘1’ is applied at the anode
end.

Common Anode Wiring

The common point is tied to logic ‘1’ and to display character logic ‘0’ is applied at the cathode
end.
Example -1: Write an 8085 ALP to display 5 at digit 4 of the multiplexed seven segment display
using common cathode type. [Hint send the code for five through port-A and digit number
through port-C]
Solution:
a)
Configure port-A and port-C as output port
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0
Contents of the control register is 80H

Hex code for five
dp g f e d c b a
0 1 1 0 1 1 0 1
The hex code is 6DH
b) MOV A, 80H
OUT CWR
MVI A, 03H
OUT PortC
MVI A, 6DH
OUT PortA
HLT

Mode-1 I/O with handshaking capability
One of the most powerful futures of the 8255 is the ability to handle handshaking signals.
Handshaking refers to the process of communicating back and forth between two intelligent
devices. Port-A and B are used for input or output while Port-C is used for handshaking signals.
In 8255, the specific lines from Port-C used for handshake signals vary according to the IO
function of a port. Therefore, input and output functions in mode 1 are discussed separately.
Mode-1 Input Control signals

(Strobe Input active low)
This signal (active low) is generated by peripheral device to indicate that it has transmitted a byte
of data. The 8255 in response to generates IBF and INTR.
IBF (Input Buffer Full)

This signal is an acknowledgment by 8255 to indicate that the input latch has received the data
byte. This is reset when the MPU reads the data.
INTR (Interrupt Request)

This is an output signal that may be used to interrupt the MPU. INTR is generated when ,
IBF and INTE are set and reset by falling edge of the signal.
Control word mode-1 Input
Status word mode-1 input

D7 D6 D5 D4 D3 D2 D1 D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
INTE (Interrupt Enable)
This is an interrupt flip flop used to enable or disable the generation of the INTR signal. The two
flip-flops INTEA and INTEB I are set/reset using the BSR mode. PC4 is used to enable or disable
INTEA and PC2 is used to enable or disable INTEB.
PC6, 7
These two lines can be setup either as input or output.
Mode-1 Output Control signals

The following figures show the contents of the control registers and status words when ports A
and B are configured as output ports.
Status word mode-1 output
D7 D6 D5 D4 D3 D2 D1 D0
INTEA 1/0 1/0 INTRA INTEB INTRB

(Output buffer Full)
This is an output signal that goes low when the microprocessor unit writes data into the output
latch of the 8255. This signal indicates to an output peripheral that new data are ready to be read.
It goes high again after the 8255 receives an from the peripheral.
(Acknowledgment)
This is an input signal from a peripheral that must output a low when the peripheral receives the
data from the 8255 port.
INTR (Interrupt Request)
This is an output signal, and it is set by the rising edge of the signal. This signal can be
used to interrupt the microprocessor unit to request the next data byte for output. This INTR is
set when , and INTE are all one and reset by the falling edge of .
INTE (Interrupt Enable)
This is an internal flip-flop to a port and needs to be set to generate the INTR signal. The two
flip-flops INTRA and INTRB are controlled by PC6 and PC2, respectively, through the BSR mode.
PC4, 5
These two lines can be setup either as input or output.
Example calculate the contents of the control register to setup port A as input and port B as
output in mode 1.
Solution:
D7 D6 D5 D4 D3 D2 D2 D0
1 0 1 1 X 1 0 X
Mode-2: Bi-directional I/O with handshaking capability

In this mode data is transferred both in and out via the same port with handshaking capability.
Port A is used as bidirectional port and 5 pins of port C are used for handshaking signals. The
remaining three pins of port C can be configured either as input or output. Port B can be
configured to be in mode 0 or 1.

Table 17: Mode 2 control word Port B in mode 0 as input
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 0 1 1/0
Table 18: Mode 2 control word Port B in mode 1 as output
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1 0 X
Example: determine the contents of the control register for the following configuration:
a) Setup Port a in mode 2, Port B in mode 0 as output port and PC2-PC0 pins as input
b) Setup Port A as bidirectional port and Port B in mode 1 as input port.
Solution:
Mode 2 control word Port B in mode 0 as input PC2‐PC0 as input
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 0 0 1
Port A as bidirectional port, Port B in mode 1 as input
D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X X 1 1 X

8085 interrupts
Interrupt is a process where an external device can get the attention of the microprocessor. When
a device interrupts, it actually wants the microprocessor to give a service which is equivalent r to
asking the microprocessor to call a subroutine. This subroutine is called Interrupt Service
Routine (ISR).
Classification of Interrupts
1. Maskable and Non-maskable Interrupt
Interrupts can be classified into two types:
 Maskable Interrupts (Can be delayed or Rejected)

 Non-Maskable Interrupts (Cannot be delayed or Rejected)
i.e.: Responding to an interrupt may be immediate or delayed depending on whether the interrupt
is maskable or non-maskable and whether interrupts are being masked or not.
The 8085 microprocessor has only one none-maskable interrupt. The non-maskable interrupt is
not affected by the value of interrupt enable flip flop.
2. Vectored and Non-Vectored Interrupts
There are two ways of redirecting the execution to the ISR depending on whether the interrupt is
vectored or non-vectored.
 Vectored: The address of the subroutine is already known to the Microprocessor

 Non Vectored: The device will have to supply the address of the subroutine to the
Microprocessor
What happens when microprocessor is interrupted?
When microprocessor receives an interrupt signal, it suspends the currently executing program
and jumps to an Interrupt Service Routine (ISR) to an incoming interrupt. Each interrupt will
most probably have its own ISR.
The detailed sequence that is common for both vectored and non-vectored interrupts:
 The microprocessor completes its current instruction

 The PC contents are stored on top of a stack
 The PC is loaded with contents of special memory locations
 The next instruction is taken from these memory locations

 Microprocessor executes the ISR

 The microprocessor returns to the main program after executing a RET instruction
at the end of the ISR.
The 8085 interrupt pins
The 8085 microprocessor has five interrupts:
1. The INTR input.
 The INTR input is the only non-vectored interrupt.
 INTR is maskable using the EI/DI instruction pair.
2. RST 5.5, RST 6.5, and RST 7.5
 All are automatically vectored.

 RST 5.5, RST 6.5, and RST 7.5 are all maskable.
RST 5.5, RST 6.5
 RST 6.5 and RST 5.5 are level sensitive.
 The interrupting signal must remain present until the microprocessor checks for
interrupts.
 The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a half).
RST 7.5
 The RST 7.5 interrupt is the only 8085 interrupt that has memory.
 If a signal on RST7.5 arrives while it is masked, a flip flop will remember the
signal.
 When RST7.5 is unmasked, the microprocessor will be interrupted even if the
device has removed the interrupt signal.
 This flip flop will be automatically reset when the microprocessor responds to an
RST 7.5 interrupt.
 It is positive edge sensitive.
 When a positive edge appears on the RST7.5 line, logic 1 is stored in the flip-flop
as a “pending” interrupt.
 Since the value has been stored in the flip flop, the line does not
have to be high when the microprocessor checks for the interrupt to be
recognized.

 The line must go to zero and back to one before a new interrupt is
recognized.
3. TRAP
 TRAP is the only non-maskable interrupt.

 It does not need to be enabled because it cannot be disabled.
 It has the highest priority amongst interrupts.
 It is edge and level sensitive.
 It needs to be high and stay high to be recognized.
 Once it is recognized, it won’t be recognized again until it goes low, then
high again.
 TRAP is usually used for power failure and emergency shutoff
Table 19: the 8085 interrupt pins
Interrupt Masking Triggering

Maskable Vectored Call location Memory
Name Method Method
Level
INTR Yes DI / EI No No No
Sensitive
RST 5.5 / DI / EI Level
Yes Yes 002CH/0034H No
RST 6.5 SIM Sensitive
DI / EI Edge
RST 7.5 Yes Yes 003CH Yes
SIM Sensitive
Level & Edge
TRAP No None Yes 0024H No
Sensitive

Interrupt Vectors and the Vector Table
An interrupt vector is a pointer to where the ISR is stored in memory and all interrupts are
mapped onto a memory area called the Interrupt Vector Table (IVT).
The IVT is usually located in memory page 00 (0000H - 00FFH).The purpose of the IVT is to
hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.
• Example: Let a device interrupts the Microprocessor using the RST 7.5 interrupt line.
– Since the RST 7.5 interrupt is vectored interrupt, Microprocessor knows to which
memory location it has to go using a call instruction to get the ISR address.
RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C
location and will get a JMP instruction to the actual ISR address. The
Microprocessor will then, jump to the ISR location
The 8085 Non-Vectored Interrupt Process
1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA
(Interrupt acknowledge) signal to the device that interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction
on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the
RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt within the program.

8. RET instruction at the end of the ISR allows the MP to retrieve the return address from
the stack and the program is transferred back to where the program was interrupted.
Enable interrupt instruction
Opcode operand Flag Description

affected
EI None None The interrupt enable flip-flop is set to enable the
interrupt process. System reset, DI instruction or an
interrupt disables the interrupt. Requests through
INTR pin are fully enabled by EI instruction but
interrupts through RST pins require additional
instruction (SIM)

Set Interrupt Mask instruction
Opcode operand Flag Description

affected
SIM None None This is a multipurpose instruction and is used to
implement interrupts RST 7.5, RST 6.5 & RST 5.5
and serial data output. The instruction interprets the
accumulator contents as shown in figure below.

SIM and interrupt Mask

1. Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST
7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

2. Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask (D0 to D2).
• If it is set to 0 the mask is ignored and the old settings remain.
• If it is set to 1, the new settings are applied.
N.B
The SIM instruction is used for multiple purposes and not only for setting interrupt masks.
 It is also used to control functionality such as Serial Data Transmission.

 Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt
masks should be modified
3. Bit 5 is not used by the SIM instruction therefore its value is don’t care.
4. SDE (Serial Data Enable)
If this bit is equal to one, it enables the serial output. I.e. to implement serial output, this
bit needs to be enabled.
5. SOD (serial output data)
Bit D7 of the accumulator is latched into the SOD output line of the microprocessor to
make it available to serial peripheral if D6=1.
Example-1: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is
enabled.
Solution
First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0

- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0
- Don’t use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0
SOD SDE D5 RST 7.5 MSE M 7.5 M 6.5 M 5.5

0 0 0 0 1 0 1 0
Contents of the accumulator =0AH.
EI ; Enable interrupts including INTR

MVI A, 0AH ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
HLT

Example-2: Calculate the control word to enable RST 7.5 and RST 6.5 and disables RST 5.5
interrupts and then write an 8085 ALP that performs the above functions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 1
EI
SIM
MVI A, 09H
HLT
Example-3: Calculate the control word to enable (unmask or set) RST 7.5 and RST 5.5 interrupt
and then write an 8085 ALP that performs the above functions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 1 0
EI
SIM
MVI A, 0AH
HLT
Example -4: Sometimes it is desirable to reset (mask or disable) the RST 7.5 service request flip-
flop under program control. Obtain the control word and write an 8085 ALP that performs the
above function.
D7 D6 D5 D4 D3 D2 D1 D0 Hex
value
0 0 0 0 1 1 0 0 0CH
0 0 0 1 1 0 0 0 18H
EI
SIM
MVI A, 0CH
HLT
The 8085 Maskable/Vectored Interrupt Process
1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.
3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the
microprocessor will complete the executing instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call instruction that sends the execution to the
appropriate location in the interrupt vector table.
5. When the microprocessor executes the call instruction, it saves the address of the next
instruction on the stack.
6. The microprocessor jumps to the specific service routine.
7. The service routine must include the instruction EI to re-enable the interrupt process.
8. At the end of the service routine, the RET instruction returns the execution to where the
program was interrupted.
Disable interrupt instruction

DI None None The interrupt enable flip-flop is reset and all
interrupts except TRAP are disabled.
Pending Interrupts
• Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain
pending.
– Using the RIM instruction, it is possible to can read the status of the interrupt
lines and find if there are any pending interrupts.
Read interrupt mask instruction
Opcode operand Flag affected Description

RIM None None Loads the accumulator with 8 bits to indicate the current
status of interrupt mask, the interrupt enable, pending
interrupts and serial input data. Thus, their respective
status can be monitored under program control.
The RIM instruction loads the accumulator register as follows

How RIM sets the Accumulator’s different bits
The RIM Instruction and the Masks
• Bits 0‐2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip-flops.
• They can be used by a program to read the mask settings in order to
modify only the right mask.
• Bit 3 shows whether the maskable interrupt process is enabled or not.
• It returns the contents of the Interrupt Enable Flip Flop.
• It can be used by a program to determine whether or not interrupts are
enabled.

• Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST
5.5
• Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins.
• Bit 6 returns the current value of the RST7.5 memory flip flop.
• Bit 7 is used for Serial Data Input.
• The RIM instruction reads the value of the SID pin on the microprocessor
and returns it in this bit.
Example: Write an 8085 ALP that checks if there is a pending request at interrupt pin RST 7.5.
[If there is a pending interrupt at this pin send FFH through Port A otherwise send 00H through
Port C]
Solution
RIM
ANI 40H
CPI 40H
JNZ XX
MVI A, FFH
OUT Port A
JMP END
XX: MVI A, 00H
OUT Port C
END: NOP
HLT
RST (Restart) Instructions
The 8085 recognizes 8-restart instructions: RST0—RST7. These are one byte call instruction
that transfer the program execution to a specific location on page 00H, i.e. executing each of this
would send the execution to a predetermined hardwired memory location.
Restart instruction Equivalent to

RST 0 CALL 0000H
RST 0 CALL 0008H
RST 0 CALL 0010H
RST 0 CALL 0018H
RST 0 CALL 0020H
RST 0 CALL 0028H

RST 0 CALL 0030H

RST 0 CALL 0038H
Restart Sequence
• The restart sequence is made up of three machine cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor reads the data lines expecting to
receive, from the interrupting device, the opcode for the specific RST
instruction.
– In the 2nd and 3rd machine cycles:
• The 16-bit address of the next instruction is saved on the stack.
• Then the microprocessor jumps to the address associated with the
specified RST instruction.
Issues in Implementing INTR Interrupts
• How long must INTR remain high?

– The microprocessor checks the INTR line one clock cycle before the last T-state
of each instruction.
– The INTR must remain active long enough to allow for the longest instruction.
– The longest instruction for the 8085 is the conditional CALL instruction which
requires 18 T-states.
• Therefore, the INTR must remain active for 17.5 T-states.
If f= 3MHZ then T=1/f and so, INTR must remain active for [(1/3MHZ) * 17.5 ≈ 5.8 micro
seconds].
• How long can the INTR remain high?

– The INTR line must be deactivated before the EI is executed. Otherwise, the
microprocessor will be interrupted again.
– Once the microprocessor starts to respond to an INTR interrupt, INTA becomes
active (=0).
Therefore, INTR should be turned off as soon as the INTA signal is received.
• Can the microprocessor be interrupted again before the completion of the ISR?
– As soon as the 1st interrupt arrives, all maskable interrupts are disabled.
– They will only be enabled after the execution of the EI instruction.
Therefore, the answer is: “only if we allow it to”.
If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.

• How do we allow multiple devices to interrupt using the INTR line?

– The microprocessor can only respond to one signal on INTR at a time.
– Therefore, we must allow the signal from only one of the devices to reach the
microprocessor.
– We must assign some priority to the different devices and allow their signals to
reach the microprocessor according to the priority.
The Intel 8259A Programmable Interrupt Controller (8259A PIC)
The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for
the microprocessor. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It
is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static,
requiring no clock input. The 8259A is designed to minimize the software and real time overhead in
handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of
system requirements. The 8259A is fully upward compatible with the Intel 8259. Software originally
written for the 8259 will operate the 8259A in all 8259 equivalent modes.
Symbol Pin No. Type Name and Function
VCC 28 I SUPPLY: a5V Supply.

GND 14 I GROUND
1 I CHIP SELECT: A low on this pin enables RD and WR communication between the
microprocessor and the 8259A. INTA functions are independent of CS.
2 I WRITE: A low on this pin when CS is low enables the 8259A to accept command
words from the microprocessor.
3 I READ: A low on this pin when CS is low enables the 8259A to release status onto
the data bus for the microprocessor.
D7-D0 4-11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector information is
transferred via this bus.
CAS-CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control a multiple
8259A structure. These pins are outputs for a master 8259A and inputs for a slave

8259A.
16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the
Buffered Mode it can be used as an output to control buffer transceivers (EN).
When not in the buffered mode it is used as an input to designate a master (SP e 1)
or slave (SP e 0).
INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It
is used to interrupt the microprocessor, thus it is connected to the microprocessor's
interrupt pin.
IR0-IR7 18-25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed
by raising an IR input (low to high), and holding it high until it is acknowledged
(Edge Triggered Mode), or just by a high level on an IR input (Level Triggered
Mode).
26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A interrupt-
vector data onto the data bus by a sequence of interrupt acknowledge pulses issued
by the microprocessor.
A0 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins.
Block and Pin Description of 8259A
INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register
(IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting
service; and the ISR is used to store all the interrupt levels which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set in the IRR. The highest priority is selected and
strobed into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR.
Masking of a higher priority input will not affect the interrupt request lines of lower quality. INT
(INTERRUPT) This output goes directly to the microprocessor interrupt input. The VOH level on this
line is designed to be fully compatible with the 8080A, 8085A and 8086 input levels.
(INTERRUPT ACKNOWLEDGE bar)

INTA pulses will cause the 8259A to release vectoring information onto the data bus. The format of this
data depends on the system mode of the 8259A.
DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control
words and status information are transferred through the Data Bus Buffer.
READ/WRITE CONTROL LOGIC

The function of this block is to accept output commands from the CPU. It contains the Initialization
Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various
control formats for device operation. This function block also allows the status of the 8259A to be
transferred onto the Data Bus.
(CHIP SELECT bar)

A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is
selected.
(WRITE bar)
A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A.
(READ bar)
A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In
Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD signals to write commands into the various
command registers, as well as reading the various statuses registers of the chip. This line can be tied
directly to one of the address lines.
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer system are its programmability and the interrupt
routine addressing capability. The latter allows direct or indirect jumping to the specific interrupt routine
requested without any polling of the interrupting devices. The normal sequence of events during an
interrupt depends on the type of CPU being used. The events occur as follows in an MCS-80/85 system:

1. One or more of the INTERRUPT REQUEST lines (IR7-IR70) are raised high, setting the
corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The microprocessor acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the microprocessor, the highest priority ISR bit is set, and the
corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the
8-bit Data Bus through its D7-D0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the
microprocessor.
6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the
Data Bus. The lower 8-bit address is released at the first INTA pulse and the higher 8-bit address is
released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is
reset at the end of the third INTA pulse.
Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt
sequence.
CASCADE MODE
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all 8259A's used in the system. The associated three
pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as
a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0-2 lines. The
slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one
or two consecutive INTA pulses.
The 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to
64 priority levels. The master controls the slaves through the 3 line cascade bus. The cascade bus acts like
chip selects to the slaves during the INTA sequence. In a cascade configuration, the slave interrupt
outputs are connected to the master interrupt request inputs. When a slave request line is activated and
afterwards acknowledged, the master will enable the corresponding slave to release the device routine
address during bytes 2 and 3 of INTA. The cascade bus lines are normally low and will contain the slave
address code from the trailing edge of the first INTA pulse to the trailing edge of the third pulse. Each
8259A in the system must follow a separate initialization sequence and can be programmed to work in a
different mode. An EOI command must be issued twice: once for the master and once for the
corresponding slave. An address decoder is required to activate the Chip Select (CS) input of each 8259A.
The cascade lines of the Master 8259A are activated only for slave inputs, non-slave inputs leave the
cascade line inactive (low).

Serial data Transmission
In serial data transmission, bits of a byte are sent one after another along a single line starting with LSB.
The transmission format is concerned with issues such as synchronization, direction of data flow, speed
errors and medium of transmission.
Direction of data flow
The serial mode of data transmission can take place unilaterally or bilaterally. Usually the data
transmission takes place in any of the following types of digital modes.
 Simplex mode
 Half-duplex mode
 Duplex (full duplex)mode
a) Simplex Mode
The data in simplex mode of transmission flows on a single channel i.e. on pair of wires in only
one direction as illustrated in the figure below.
b) Half-duplex mode of transmission

In half-duplex mode of transmission the data flows on a single channel in both direction but not at
the same time.
Here the data can be transmitted from transmitter A to receiver B or from transmitter B to
receiver A.
c) Duplex (Half-Duplex mode of transmission)

In full duplex mode of transmission the flow of data takes place in both directions at the same
time through 2-different channels. Data transfer takes place in both directions, simultaneously as
shown in the figure below.
Synchronization
The serial data can be transmitted in any of the two modes:
 Synchronously or
 Asynchronously
a) Asynchronous serial data transmission
The asynchronous transmission is character oriented. Each character carries the information of the ‘start
bit’, and then ‘stop bits’ as indicated in the figure

below.
When no data is transmitted in asynchronous mode of transmission, the line is maintained at an

idle value. The idle value is always logic-1. The start bit is logic-0. Start bit i.e. a signal transition from
the idle value to start value (1 to 0) precedes each character. The stop bits are logic 1. The transmission
begins with 1-start bit (0) followed by data character and then 2-stop bits. The asynchronous format is
generally used in low speed transmission (less than 20K baud)
b) Synchronous serial data transmission

In asynchronous mode of data transmission, a clock is used to synchronize both the transmitter
and receiver. The synchronous eliminates the need of start-stop bits for each character. However, this time
interval between characters is fixed. In synchronous mode of transmission, a complete block of characters
is transmitted at one time. Thus, this method is more efficient way of data transmission.
Error detection and correction
During transmission various types of errors can occur. These errors need to be checked an; therefore,
additional information for error checking is sent during the transmission. The receiver can check the
received data against the error check information, if the error is detected, the receiver either correct the
error or request the retransmission of that data segment.
Some of the methods used to detect errors are:
 Parity check
 Check sum
 Cyclic redundancy check
a) Parity check
Probably the most common and oldest method of error detection is the use of parity. While parity is used
in both asynchronous and synchronous data streams, it seems to find greater use in low-speed
asynchronous transmission applications; however, its use is not exclusive to this.
Parity works by adding an additional bit to each character word transmitted. The state of this bit is
determined by a combination of factors, the first of which is the type of parity system employed. The two
types are even and odd parity. The second factor is the number of logic 1 bits in the data character. In an
even parity system, the parity bit is set to a low state if the number of logic 1s in the data word is even. If
the count is odd, then the parity bit is set high. For an odd parity system, the state of the parity bit is
reversed. For an odd count, the bit is set low, and for an even count, it is set high.

EXAMPLE 3-1
What is the state of the parity bit for both an odd and an even parity system for the extended ASCII
character B?
SOLUTION
The extended ASCII character B has a bit pattern of 01000010 (42 H). The number of logic 1s in that
pattern is two, which is an even count. For an even parity system, the parity bit would be set low and for
an odd parity system, it would be set high.
To detect data errors, each character word that is sent has a parity bit computed for it and appended after
the last bit of each character is sent as illustrated in Figure 3-1. At the receiving site, parity bits are
recalculated for each received character. The parity bits sent with each character are compared to the
parity bits the receiver computes. If their states do not match, then an error has occurred. If the states do
match, then the character may be error free.
EXAMPLE 3-2
The ASCII character B is transmitted with an even-parity bit appended to it. Illustrate how the receiver
would detect an error.
SOLUTION
As shown in Figure 3-2a, the state of the even-parity bit for the ASCII B is low, so the complete data
stream for the character sent, starting with the least significant bit (LSB) is: 010000100. Notice, there are
now nine bits—eight bits for the extended ASCII character B and one for the parity bit. The breakdown of
the data stream is:
LSB MSB Parity

0 1 0 0 0 0 1 0 0
Suppose that the LSB becomes corrupted during transmission. The receiver receives the character as:
110000100. When the receiver computes a parity bit for the character data, it results in a high state of the
parity.
This is compared with the transmitted parity, which is a low state. Since they do not agree, the receiver
determines that an error has occurred.
Note that the receiver cannot determine which bit is bad, only that one of them is wrong.
A match between transmitted parity and receiver-calculated parity does not guarantee that the data has not
been corrupted. Indeed, if an even number of errors occurs in a single character, then the parity for the
corrupted data will be the same state as the good data. For instance, suppose the two lowest bits in the
character B were bad. The total number of ones in the data stream would still be an even count and the
parity bit calculated at the receiver would be a low state and would match the one transmitted. This does
not present a major problem, since the occurrence of two errors in an eight-bit character is excessive and
usually indicates a major problem in the system.
Such a problem would cause errors to occur in other characters and one of them would eventually be
detected. Since the occurrence of errors is extremely low, parity is successful in detecting more than 95%
of the errors that occur.
Review Questions
1. What is the state of the parity bit using an odd-parity system for the extended ASCII character M?

2. Why doesn’t a good match between transmitted and received parity bits guarantee that the character is
good?
b) Checksum Error Detection

Another method of error detection uses a process known as checksum to generate an error-detection
character. The character results from summing all the bytes of a message together [discarding any carry-
over from the addition], and then computing 2’s complement of the result. Then the 2’s complement of
the sum is transmitted as a last byte of the message.
The receiver adds all the bytes including the two’s complement of the sum. The result should be zero if
there is no error in the block.
The major advantage of checksum is that it is simple to implement in either hardware or software. The
drawback to checksum is that, unless you use a fairly large checksum (16- or 32-bit instead of 8-bit);
there are several data-bit patterns that could produce the same checksum result, thereby decreasing its
effectiveness. It is possible that if enough errors occur in a message that a checksum could be produced
that would be the same as a good message.
EXAMPLE 3-10
What is the checksum value for the extended ASCII message “Help!”?
SOLUTION
The checksum value is found by adding up the bytes representing the Help! Characters:
H 0 1 0 0 1 0 0 0
e 0 1 1 0 0 1 0 1
l 0 1 1 0 1 1 0 0
p 0 1 1 1 0 0 0 0
! 0 0 1 0 0 0 0 1
Sum 0 0 0 1 0 0 0 0
One’s complement 1 1 1 0 1 1 1 1
Checksum 1 1 1 1 0 0 0 0
Review Questions
1. What is the 16-bit checksum value for the extended ASCII message “That’s a 10-4”? Do not
forget space characters!
2. Why are larger checksums preferred over shorter ones?
c) Baud Rate
The rate at which the bits are transmitted (bits/second) is called baud rate. Baud rate varies from device to
device.
Bit waiting time is calculated from a given baud rate.
Example: Determine the bit time (the delay between any two consecutive bits) if the baud rate of a given
device is 1200.
Answer
1200bits—1 second
1 bit --- 1/1200 second = 0.83ms

Serial output data

SOD pin of an 8085 microprocessor is a bit output port.
The Instruction SIM and SOD pin
In addition to configuring the interrupt pins, the SIM instruction is used to output data serially through the
SOD line.
During serial transmission, D7 and D6 of the accumulator register are interpreted as follows:
In short the SIM instruction checks D6 of the accumulator register to send the bit at D7 of the
accumulator. If D6 is set to 1, the SIM instruction will send the bit at D7 of the accumulator. If D6 is 0,
nothing is transmitted through the SOD line.

Algorithm for Serial Data Transmission
Example: Write a subroutine to transmit an ASCII character stored in register B using the SOD one bit
port.
Solution
MVI C, 0BH
SUB A
NEXTBIT: MVI A, 80H
RAR
SIM

CALL BITTIME
STC
MOV A, B
RAR
MOV B, A
DCR C
JNZ NEXTBIT
RET
Serial Input Data
SID pin of the 8085 microprocessor is a bit input port.
The RIM Instruction and serial Transmission
Besides reading the status of the interrupt pins, RIM instruction is used to input data serially to D7 of the
accumulator register from the SID line of the 8085 microprocessor.

Start
Read SID
Is it
high?
Wait for Half‐Bit Time
Setup Bit Counter
Wait Bit Time
Read SID
Save Bit
Decrement Bit counter
Are all bits
received? Return
Add Bit to previous Bits
Go back to get next bit

Example: Write a subroutine to receive an ASCII character using the 8085 SID pin.
Solution
Check: RIM
RAL
JC Check
CALL HALFTIME
MVI C, 08H
NEXTBIT: RIM
CALL BITTIME
RAL
DCR C
JZ RETURN
MOV A, B
RAR
MOV B, A
JMP NEXTBIT
RETURN: NOP
RET

The 8254 Programmable Interval Timer (PIT)
The 8254 Programmable Interval Timer (PIT) is an intelligent timer/counter. Functionally it is

similar to software designed counters and timers. It generates accurate time delays and can be
used for applications such as a real time clock, an event counter, a digital one-shot, a square
wave and complex wave generator.
The 8254 Programmable Interval Timer (PIT) can be programmed to operate in six modes and
has three 16-bit identical counters that can operate independently in any one of the six modes.
Pin Configuration of the 8254 Programmable Interval Timer (PIT)
Fig. Pin Configuration of 8254
Block diagram of the 8254

Fig. Internal block diagram of 8254
Pin Description of 8253/54 PIT
Read/Write Control Logic
It has five control signal lines, namely; Chip select bar, A0, A1, Read bar and Write bar.
A1, A0
These lines are connected to the address bus of the processor. The address inputs select one of
the four internal registers within the 8254 as follows:
Table 20: Selection of counter registers and a Control Word Register
A1 A2 Function
0 0 Counter 0
0 1 Counter 1
1 0 Counter -2
1 1 Control Register
 (Read bar)
Read causes data to be read from the 8254. A low on this pin informs the 8254 PIT the
microprocessor is ready to accept data in the form of count value.
 (Write bar)
Write causes data to written to the 8254. A low on this pin enables the microprocessor to
configure control register and load the count value to the selected counter.
(Chip Select bar)

Chip select enables the 8254 for programming, reading and writing to a counter. No reading or
writing operations are performed by or on the 8254.
GRD
Ground connects to the system ground bus.
VCC
Power supply (+5.0 V) pin.
CLK
The clock input is the timing source for each of the internal counter.
OUT
Output of a counter (generated wave form) is sent through this pin.
Can have square wave, one shot and other waves for various duty cycles but no sine wave, or
saw tooth wave.
GATE
This pin is used to enable or disable the counter.
D0-D7
The D0-D7 data bus of the 8253/54 is a bidirectional bus connected to D0-D7 of the system data
bus.
Control word register

D0
D0 chooses between a binary number divisor of 0000 to FFFFH or a BCD divisor of 0000 to
9999H.
• The highest number is 216 for binary and 104 for BCD.
• To get the highest count, the counter is loaded with zeros.
D1, D2, and D3

D1, D2 and D3 are used for mode selection.
D3 D2 D1 Mode
0 0 0 Mode 0 Interrupt on terminal count
0 0 1 Mode 1 Programmable one-shot
X 1 0 Mode 2 Rate Generator
X 1 1 Mode 3 Square wave rate generator
1 0 0 Mode 4 Software triggered strobe
1 0 1 Mode 5 Hardware triggered strobe

D4 and D5
D4 and D5 are used for RL0 and RL1. RL0 and RL1 are used to indicate the size of the count
values and counter latching operation. In indicating the size of the count it has 3 options:
1. Read/write MSB only

2. Read/write LSB only
3. Read/write LSB first followed immediately by the MSB.
D7 and D5
D6 and D7 are used to select the 3 counters: counter 0, counter 1, or counter 2 and read back
operation. All counters are down counters and to program a given counter of the 8253/54, one
must send the count value to the specific counter’s register.
8253/54 Operation Modes

The 8253/54 can operate in 6-different modes: mode-0, mode-1, mode-2 v mode-3, mode-4, mode-5, and
mode-6.
• Mode 0: Interrupt on terminal count

The output is initially low, and remain low for the duration of the count if GATE=1. When the terminal
count is reached, the output will go high and remain high until a new control word or new count number
is loaded.
• Width of low pulse = N * T, where T is clock period
• If GATE becomes low at the middle of the count, the count will stop and the output will be low.
The count resumes when the GATE becomes high again. This in effect adds to the total time the
output is low.
Example-1: Write a program that configures the 8254 in mode-0, select counter-0 and counts in BCD.
[COUNT value= 120 in decimal]
Solution
a)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 0 0 1
b) MVI A, 31H

OUT CWRT
MVI A, 20H
OUT CTR1
MVI A, 01H
OUT CTR1
HLT
Example-2: Pin Chip Select bar of a given 8253/54 is activated by binary address A7-A2=100101.
a) Find the port addresses assigned to the counters and control register of 8253/54.
b) Find the configuration for 8253/54 if the control register is performed as follows
MVI A, 36H
OUT CWRT
HLT
Solution
a)
Chip Select bar A1 A2 Port Port Address
A7 A6 A5 A4 A3 A2
1 0 0 1 0 1 0 0 Counter-0 94H
1 0 0 1 0 1 0 1 Counter-1 95H
1 0 0 1 0 1 1 0 Counter-2 96H
1 0 0 1 0 1 1 1 Control register 97H
b)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 1 0
Interpretation of the above accumulator value

1) Counter-0
2) Load 16-bit LSB first then load MSB
3) Mode-3
4) Counts in binary form

• Mode 1: HW triggered / programmable one shot

– The triggering must be done through the GATE input by sending a 0-to-1 pulse to it.
Steps: 1) Load the count register
2) A 0-to-1 pulse must be sent to the GATE input to trigger the count
– In Mode 1, after sending the 0-to-1 pulse to GATE, OUT becomes low and stays low for a
duration of N*T, then becomes high and stays high until the GATE is triggered again.
– If during the activation, a retriggered happened, and then restarts the down counting.
Example-1: Configure control register of 8254 as follows: select counter-1, load 16-bit counter value in
mode-1 as binary counter and then write an 8085 ALP that configures OUT1 to output low pulse for 50µs
if the input clock frequency is 1MHz.
a) Count = Delay/input period = 50µs/ 1µs = 50 in decimal .To maintain a low pulse for 50µs at
the OUT pin of the selected counter; it should be initialized in mode 1.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 0 1 0

b) MVI A, 72H
OUT CWRT
MVI A, 32H
OUT CTR1
MVI A, 00H
OUT CTR1
HLT
• Mode 2: Rate Generator

– In Mode2, if GATE=1, OUT will be high for (N-1)*T, goes low only for one clock pulse, then
counter is reloaded automatically, and the process continues indefinitely.

Example-1: Write an 8085 ALP to generate a pulse every 50µs from counter 0. Configure it to count in
binary. [Input clock frequency is 2MHz]
a) Count = Delay/input period = 50µs/ 0.5µs = 100 in decimal or 64H
To generate a pulse every 50µs from counter 0, it should be initialized in mode 2.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 0 0
0 0 1 1 0 1 0 0
b) MVI A, 14H
OUT CWRT
MVI A, 64H
OUT CTR0
HLT
Or
MVI A, 34H
OUT CWRT
MVI A, 64H
OUT CTR0
MVI A, 00H
OUT CTR0
HLT
Example-2: Write a program to generate a pulse at the rate frequency of 638Hz from counter-2. The input
clock frequency to counter 2 is 1MHz.
a) Count = Delay/input period = 1567µs/ 1µs = 1567 in decimal .To generate a pulse every
1/638 s from counter 2; it should be initialized in mode 2.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 0 1 0 1
b) MVI A, B5H
OUT CWRT
MVI A, 67H
OUT CTR2
MVI A, 15H
OUT CTR2
HLT

• Mode 3: Square wave rate generator

Mode-1 is similar to mode-2 except the output remains high for the first half of the count and becomes
low for the rest half of the count. Thus, it generates a square wave at OUT.
• If the number N loaded into the counter is even, both high and low pulse have the same length,
which is N/2.
• If the number N loaded into the counter is odd, the high pulse is (N+1)/2 and the low pulse is
(N–1)/2.
• If N is odd, the high portion of the output square wave is slightly wider than the low portion.
Example-1: Write an 8085 ALP to generate a 10 KHz square wave from counter-0 with input clock
frequency of 1MHz.
Solution
a) Count = Delay/input period = 1MHz/ 10 KHz = 100 in decimal or 64H
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 1 1 0
b) MVI A, 36H
OUT CWRT
MVI A, 64H
OUT CTR0
MVI A, 00H
OUT CTR0
HLT
Example-2: Write instructions to generate a 1 KHz square wave from counter-1. [Configure it as a binary
counter and the input clock frequency for counter-one is 2MHz]
Solution

a) Count = Delay/input period = 2MHz/ 1 KHz = 2000 in decimal or 07D0H
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 1 1 0
b) MVI A, 76H
OUT CWRT
MVI A, D0H
OUT CTR1
MVI A, 07H
OUT CTR1
HLT
• Mode 4: Software triggered strobe

Similar to Mode2, except that the counter is not reloaded automatically. In Mode4, if GATE=1, the
output will go high when loading the count, it will stay high for duration N*T. After the count reaches
zero, it becomes low for one clock pulse, then goes high again and stays high until a new command word
or new count is loaded. To repeat the strobe, the count must be reloaded
• Mode 5: Hardware triggered strobe

Similar to Mode4, except that the triggering must be done with the GATE input – The count starts only
when a 0-to-1 pulse is sent to the GATE input. If GATE retriggered during the counting, it will restart the
down counting.


8085 Microrprocessor Lecture Note

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Mekelle Institute of Technology Microprocessor Lecture note February 2, 2010

Introduction to Intel 8085 microprocessor

 Measuring instruments such as the oscilloscope, multi-meter, and spectrum analyzer

Important factors used to compare microprocessor

Internal Architecture of 8085 Microprocessor

Compiled by Solomon Teklehaimanot Page 1

Fig 1.1 Internal architecture of 8085 microprocessor

Arithmetic Logic Unit

N.B Most operations in the ALU involve the accumulator.

Compiled by Solomon Teklehaimanot Page 2

Arithmetic operations Logic operations

Fig 1.2 Status Register

Sing flag (S)

Compiled by Solomon Teklehaimanot Page 3

+ 2BH (2’s complement of C5H)

Auxiliary Carry Flag

Example: Add 0FH and 3AH

Compiled by Solomon Teklehaimanot Page 4

Carry Flag (C)

Instruction Register and Decoder

Timing and control unit

Register section of 8085 microprocessor

Registers accessible to the programmer are further sub-divided into 2 sub-groups.

Compiled by Solomon Teklehaimanot Page 5

General Purpose Registers (GPRs)

Special Purpose Registers (SPRs)

Stack Pointer (SP)

8085 System Buses

Compiled by Solomon Teklehaimanot Page 6

Compiled by Solomon Teklehaimanot Page 7

8085 Pin description

Fig.1.4. Pin configuration of Intel 8085 Microprocessor

Compiled by Solomon Teklehaimanot Page 8

Address Bus: A15-A8, AD7-AD0 (Output 3 States)

AD0 - AD7 (Input/output 3state)

Data Bus Status (SO, S1 Output)

Encoded status of the bus cycle

Compiled by Solomon Teklehaimanot Page 9

Compiled by Solomon Teklehaimanot Page 10

RESET OUT (Output)

Vss: Ground reference.

Instruction and Computer Languages

8085 instruction set consists of the following instructions:

Compiled by Solomon Teklehaimanot Page 11

 Arithmetic instructions - These instructions perform arithmetic operations such as

Assembly Language is a symbolic representation of machine language of a specific processor or

In short assembly languages:

Compiled by Solomon Teklehaimanot Page 12

• Advantages of machine or assembly languages

High level languages

ASSEMBLY LANGUAGE OR MACHINE LANGUAGE

Advantages of higher level programming:

Compiled by Solomon Teklehaimanot Page 13

Typically, assemblers make two passes over the assembly file

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8085 INSTRUCTION SET

Move immediate 8-bit

MVI instruction is a two byte instruction

Opcode Operand Flag Description

Example: MVI B, 57H; copies the byte 57H into register B

Copy from source to destination

MOV instruction is a one byte instruction

Opcode Operand Flag affected Description