Synlock v3 Bits v300r003c10 Product Description 01

SYNLOCK V3 BITS(SSU,SASE)
V300R003C10
Product Description
Issue 01
Date 2014-06-30
HUAWEI TECHNOLOGIES CO., LTD.

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Product Description About This Document
About This Document
Product Version
Table 1 Version requirements of U2000 and Synlock V3
Product Name Product Version
iManager U2000 V100R006C02SPC300+CP3203,

V100R006C02SPC300SPC302, or higher
V100R009 is the mainstream version and is
recommended and V100R006 is the second
choice.
MITU control board of Synlock V3 202 or later
Intended Audience
This document describes the positioning, characteristics, system architecture, functions,
configurations, applications, device management, technical specifications, and standards
compliance of the SYNLOCK V3.
This document is intended for:
 Network planning engineers
 Hardware installation engineers
 Installation and commissioning engineers
 Field maintenance engineers
 Data configuration engineers
 System maintenance engineers
 Application developers
Symbol Conventions
Symbols used in this document are described in the following table.
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Symbol Description
Indicates an imminently hazardous situation which, if not

avoided, will result in death or serious injury.
Indicates a potentially hazardous situation which, if not

avoided, could result in death or serious injury.

avoided, may result in minor or moderate injury.

avoided, could result in equipment damage, data loss,
performance deterioration, or unanticipated results.
NOTICE is used to address practices not related to
personal injury.
Notes to important information, best practices and tips.
NOTE is used to address information not related to
personal injury, equipment damage, and environment
deterioration.
Change History
Changes between document issues are cumulative. The latest document issue contains all the
changes in earlier issues.
Updates in V300R003C10 01 (2014-06-30)

Compared with V300R002 02 (2012-09-15), the following changes are made:
Changes:
 The 1588 ACR feature is added.
 The full configuration changes from 3 subracks to 4 subracks.
 The slots for accommodating TODI/PNSU/TODU/TSOU boards are changed.
 LCIM/SRCU/SOCU/TSOU boards do not support cables with 50-ohm resistance.
 The number of boards to be configured when the device functions as a 1588 or an NTP
time server is changed.
 The fan tray needs to be configured when the extended subrack supports high-precision
time synchronization.
 The "Device Management" section is updated.
 Power consumption of boards is changed.
 The "Traditional Time Synchronization Performance Counters" section is updated.
 Port specifications are updated.
 The CCOU board is removed.
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 From V300R003C00, functions that used to be provided by the CCOU board are
provided by the TSOU board.
 Subracks of V300R003C00 still support TSOU and CCOU boards of historical versions.
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Product Description Contents
Contents
About This Document....................................................................................................................ii

1 Product Positioning and Characteristics...................................................................................1
1.1 Product Positioning........................................................................................................................................................1
1.2 Product Characteristics...................................................................................................................................................1
1.2.1 Compact Structure.......................................................................................................................................................2
1.2.2 Flexible Configuration.................................................................................................................................................2
1.2.3 Complete Functions.....................................................................................................................................................2
1.2.4 Superior Performance..................................................................................................................................................2
1.2.5 High Stability and Reliability......................................................................................................................................2
2 Product Architecture.....................................................................................................................4
2.1 Hardware Architecture....................................................................................................................................................4
2.1.1 Appearance and Structure............................................................................................................................................4
2.1.2 Working Principle........................................................................................................................................................5
2.1.3 Power Distribution Principle.......................................................................................................................................6
2.1.4 Ventilation Principle....................................................................................................................................................6
2.1.5 Grounding....................................................................................................................................................................7
2.2 Software Architecture.....................................................................................................................................................7
3 Product Functions..........................................................................................................................9
3.1 Frequency Synchronization............................................................................................................................................9
3.2 Time Synchronization...................................................................................................................................................10
3.3 Board Functions............................................................................................................................................................11
3.3.1 LCIM Board..............................................................................................................................................................11
3.3.2 SRCU/SOCU Board..................................................................................................................................................13
3.3.3 TSOU Board..............................................................................................................................................................16
3.3.4 MITU Board..............................................................................................................................................................16
3.3.5 TODI Board...............................................................................................................................................................18
3.3.6 TDRV Board..............................................................................................................................................................18
3.3.7 PNSU Board..............................................................................................................................................................18
3.3.8 TODU Board.............................................................................................................................................................18
3.4 Characteristics..............................................................................................................................................................19
3.4.1 Compact Structure and Flexible Configuration.........................................................................................................19
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3.4.2 Complete Functions and Flexible Use.......................................................................................................................19

3.4.3 High Reliability and Superior EMC..........................................................................................................................20
3.4.4 Ease-of-Maintenance.................................................................................................................................................20
4 Product Configuration and Application.................................................................................22

4.1 Frequency Synchronization..........................................................................................................................................22
4.1.1 Application Scenario.................................................................................................................................................22
4.1.2 Typical Configuration................................................................................................................................................23
4.1.3 Network Application.................................................................................................................................................25
4.2 Time Synchronization...................................................................................................................................................27
4.2.1 Application Scenario.................................................................................................................................................27
4.2.3 1588 Time Server Networking..................................................................................................................................30
4.2.4 NTP Server Networking............................................................................................................................................31
4.3 Clock Monitoring.........................................................................................................................................................32
4.3.2 Network Application.................................................................................................................................................33
5 Device Management...................................................................................................................35
5.1 Overview......................................................................................................................................................................35
5.2 Centralized Maintenance Terminal Mode....................................................................................................................36
5.2.1 Running Environment...............................................................................................................................................36
5.2.2 Management Functions.............................................................................................................................................37
5.2.3 Typical Networking...................................................................................................................................................37
5.3 CLI Mode.....................................................................................................................................................................39
5.3.1 Running Environment...............................................................................................................................................39
5.3.2 Features......................................................................................................................................................................40
5.4 iManager U2000 Management Mode...........................................................................................................................40
6 Technical Specifications and Standards Compliance..........................................................41

6.1 Technical Specifications...............................................................................................................................................41
6.1.1 Device Parameters.....................................................................................................................................................41
6.1.2 Frequency Synchronization Performance Counters..................................................................................................43
6.1.3 Traditional Time Synchronization Performance Counters........................................................................................51
6.1.4 FE/GE 1588 Performance Counters..........................................................................................................................52
6.1.5 1 PPS+TOD Performance Counters..........................................................................................................................52
6.1.6 Port Specifications.....................................................................................................................................................52
6.1.7 MTBF........................................................................................................................................................................54
6.1.8 EMC..........................................................................................................................................................................55
6.2 Standards Compliance..................................................................................................................................................55
6.2.1 China Standards.........................................................................................................................................................55
6.2.2 ITU-T Recommendations..........................................................................................................................................55
6.2.3 IEEE Recommendations............................................................................................................................................55
6.2.4 ETSI Recommendations............................................................................................................................................56
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6.2.5 RFC Recommendations.............................................................................................................................................56
7 Acronyms and Abbreviations...................................................................................................57
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SYNLOCK V3 BITS(SSU,SASE) Product Positioning and CharacteristicsProduct
Product Description Positioning and Characteristics
1 Product Positioning and Characteristics
About This Chapter

1.1 Product Positioning
1.2 Product Characteristics
1.1 Product Positioning

The SYNLOCK V3 is a building integrated timing supply (BITS) system launched by Huawei
Technologies Co., Ltd. (Huawei for short).
With the development of the Internet Protocol (IP) network, transmission over IP is
implemented for most communication networks. Owing to the asynchronous feature of the IP
network, equipment on the IP network cannot obtain synchronization information through
physical links. Against this backdrop, network equipment is required to provide a
synchronization method for catering to the IP network while at the same time retaining the
legacy synchronization method on the live network.
The market positioning of the SYNLOCK V3 is as follows:
 Meets the high-accuracy time and clock synchronization requirements of the service
equipment on the IP transmission network.
 Meets the high-accuracy time and clock synchronization requirements in different
networking environments (different transport networks and different network scales) by
using subrack-type equipment.
 Supports time and frequency synchronization in the traditional transmission network.
 Provides multiple types of high-density synchronous ports to meet the requirements for
multiple ports at the convergence layer and core layer.
1.2 Product Characteristics

This section describes the major characteristics of the SYNLOCK V3.
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1.2.1 Compact Structure

The SYNLOCK V3 has a compact structure, and it can be installed in a 19-inch cabinet or an
ETSI cabinet. In common applications, the SYNLOCK V3 requires only one subrack with 3-4
types of boards to provide 8-16 input channels, 8-20 monitoring channels, and 20-100 output
channels. With such configurations, the SYNLOCK V3 is able to obtain any stratum of clock
and provide redundancy backup. When all the four subracks are configured (full
configuration), the SYNLOCK V3 is able to provide 400 traditional frequency
synchronization outputs, and 160 high-accuracy time synchronization outputs.
1.2.2 Flexible Configuration

The SYNLOCK V3 supports flexible configurations. By selecting different oscillators and
different satellite modules for its clock board, the SYNLOCK V3 obtains different stratums of
clocks to meet diversified user requirements. With its flexible configurations, the SYNLOCK
V3 provides practical BITS configurations of different capacities and levels for different
users; also its networking is convenient and ports are flexible.
1.2.3 Complete Functions

The SYNLOCK V3 provides all the synchronization functions and ports required in the
synchronization field.
Time Synchronization
 IEEE 1588v2
 DC level shift (DCLS)
 One pulse per second (1 PPS) and time of day (TOD)
 Network Time Protocol (NTP)
Frequency Synchronization
 Ethernet physical-layer synchronization, that is, synchronous Ethernet (Sync-E)
 1588 ACR
 Traditional building integrated timing supply (BITS) physical-layer synchronization
(E1(2048 kbit/s), 2048 kHz)
1.2.4 Superior Performance

The SYNLOCK V3 features superior performance and robustness. Different stratums of
clocks have performance indicators one or two orders of magnitude better than those defined
in related standards.
1.2.5 High Stability and Reliability

Underpinned by advanced technologies, the SYNLOCK V3 has superior reliability, stability,
and online maintainability. It has high reliability indexes (mean time between failures
(MTBF) and DOWNTIME), and good electromagnetic compatibility (EMC) and environment
adaptability.
Specifically, The SYNLOCK V3 provides the following features to ensure its stability and
reliability:
 Distributed control structure

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 Redundancy of all timing channels and no single point failure

 Board hot swapping and effective port isolation protection
 Automatic fault locating to modules
 Backup for all boards and components
 Shielded subrack and good EMC

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Product Description Product ArchitectureProduct Architecture
2 Product Architecture
About This Chapter

2.1 Hardware Architecture
2.2 Software Architecture
2.1 Hardware Architecture

This section describes the hardware information about the SYNLOCK V3, including its
appearance, structure, working principle, power distribution, ventilation, and grounding.
2.1.1 Appearance and Structure

Figure 2-1 shows the appearance of the SYNLOCK V3.
Figure 1.1 Appearance of the SYNLOCK V3
Table 2-1 lists the slots for the boards of the SYNLOCK V3 and Table 2-2 lists the boards of
the SYNLOCK V3.

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Table 1.1 Slots for the boards of the SYNLOCK V3

Slot Board
0 and 12  The SRCU or SOCU board can be installed in the master subrack.
 The TDRV board can be installed in the extended subrack.
1 to 10  The master subrack is input/output-compatible and can accommodate
LCIM, TSOU, TODI, PNSU, and TODU boards.
 TODI, PNSU, TODU, and TSOU boards can be installed in extended
subracks 1 and 2.
NOTE
Extended subracks 1 and 2 cannot be configured with time synchronization boards at
the same time.
 The TSOU board can be installed in extended subrack 3.
11  Only the MITU board can be installed in the master subrack.
 No board is required in the extended subrack.
Table 1.2 Boards of the SYNLOCK V3

Silk Screen Description
MITU Maintenance interface and TOD unit

TSOU Timing signal output unit
LCIM Line clock input and measure unit
SRCU Satellite signal receiver and rubidium clock unit
SOCU Satellite signal receiver and OCXO clock unit
TDRV Timing signal drive unit
TODI TOD interface unit
PNSU Packet networks synchronization unit
TODU TOD unit
2.1.2 Working Principle

The SYNLOCK V3 uses distributed cluster control and its system reliability is greatly
enhanced because of the following features:
1. The clock bus uses multi-hot backup.
2. The control structure employs two buses.
3. The input unit, local clock unit, and clock distribution unit all work in hot backup mode.
4. The power system is mutual-aid.

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The SYNLOCK V3 employs the two-level distribution control mode, which helps greatly
improve the processing capability of the entire system and fault isolation performance of the
hardware system.
Figure 2-2 shows the architecture of the SYNLOCK V3 system.
Figure 1.2 Architecture of the SYNLOCK V3 system
2.1.3 Power Distribution Principle

The SYNLOCK V3 uses two channels of external -48 V DC power supply. These two
channels of power supply input are led to the DC power distribution unit. After the filtering,
load sharing, and lightning-proof processing, the input power supply is distributed to the
lower subrack, and then reaches the lightning-proof and filter module of the backplane and is
finally combined as one -48 V DC power input on the boards. After that, the power input is
able to provide operating voltage for each board.
2.1.4 Ventilation Principle

Boards of the SYNLOCK V3 are vertically installed.
 The master subrack of the SYNLOCK V3 has high power consumption. Because of this,
an independent 2 U fan tray needs to be installed in the lower part of the master subrack
to ensure proper ventilation.

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 When a cabinet accommodates 1 master subrack and 2 extended subracks, no fan tray is
needed on the extended subrack. When a cabinet accommodates 1 master subrack and 1
extended subrack that supports high-precision time synchronization, a 2-U fan tray needs
to be configured in the lower part of the extended subrack to ensure proper ventilation.
2.1.5 Grounding
The SYNLOCK V3 must be grounded properly for lightning release. This also improves the
anti-electromagnetic interference capability of the entire system.
After the subrack is installed in the cabinet, the mounting ears of the subrack are in contact
with the cabinet. In this way, the device is grounded.
Figure 2-3 shows the position of the ground point.
Figure 1.3 Ground point of the subrack
 (1): Positions for securing and grounding the device.

 (2): Ground points when the mounting ears of the device are not in contact with the cabinet, and the
device cannot be grounded, for example, the device is not installed in a cabinet in a test.
2.2 Software Architecture

This section describes the software architecture of the SYNLOCK V3.
The control unit software, running on the MITU board, bridges the system and the
maintenance terminal. It has the following functions:

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 Communicates with the boards for collecting board running status information,
configuring board running parameters, and controlling board running.
 Stores various system historical data for the maintenance terminal query.
 Provides TL1 and SNMP ports to connect to multiple maintenance terminals and the
NMS center concurrently for system maintenance.
The maintenance terminal software, running on the PC, has the following functions:
 Maintains multiple devices concurrently using the serial port or Ethernet port.
 Provides the system monitoring, maintenance, and management ports for device
maintenance engineers.
 Displays various system running status in a graphical way.
 Displays in curves the performance data of various boards collected by the control unit
software.
The board software, running on each board, has the following functions:
 Supports the normal running of the CPU small system.
 Implements the service functions of a board.
Figure 2-4 shows the software architecture of the SYNLOCK V3 system.
Figure 1.4 Software architecture of the SYNLOCK V3 system

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Product Description Product FunctionsProduct Functions
3 Product Functions
About This Chapter

3.1 Frequency Synchronization
3.2 Time Synchronization
3.3 Board Functions
3.4 Characteristics

The SYNLOCK V3 provides various strata of clocks required for the synchronization
network, as listed in Table 3-1.
Table 4.1 Clock strata

Clock Stratum YD/T ITU-T ETSI Standard
Recommendation
Stratum-1 primary 1479–2006 G.811 ETS 300 462-6

reference clock 1011–1999 (DE/TM-3017-6)
(PRC/LPR)
1012–1999
Stratum-2 enhanced G.812 ETS 300 462-4
clock (ST2E/TNC) (DE/TM-3017-4)
Stratum-3 enhanced G.812
clock (ST3E/LNC)
The SYNLOCK V3 uses integrated structure. With different boards, the SYNLOCK V3
provides various clocks required for the synchronization network and also the synchronous
clock solution for the entire network. According to actual network requirements, the
SYNLOCK V3 provides customized configurations for the international exchange, inter-
provincial long-distance office, provincial long-distance office, and especially for the tandem

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office and end office. Also, the SYNLOCK V3 is applicable for sites that cannot obtain the
timing signals from transmission lines, such as the base stations and the equipment room in
the community.
The SYNLOCK V3 provides diversified frequency synchronization-related signal ports, as
shown in Table 3-2.
Table 4.2 Signal ports

Signal Type Physical Port Maximum Maximum Remarks
Outputs Outputs
Supported by Supported by
Boards SYNLOCK
V3
2048 kbit/s, SMB TSOU board: Output: 400 -

2048 kHz, 1024 20-channel channels
kHz/5120 output per
kHz/10240 kHz group
Sync-E/1588 FE electrical PNSU board: 8- Output: 160 The G.8265.1
ACR port/FE optical channel output channels (One frequency
port/GE optical per group of the channels synchronization
port (When the can be is supported.
PNSU board is configured as
inserted into an input
slot 1 or 2, one channel for
of the channels both the PNSU
can be board in slot 1
configured as and the PNSU
an input board in slot 2.)
channel.)

This section describes various signal ports provided by the SYNLOCK V3 for time
synchronization, as listed in Table 3-3.
Table 4.3 Signal ports for time synchronization

Signal Physical Maximum Maximum Description
Type Port Inputs/Outpu Inputs/Outputs
ts Supported Supported by
by Board SYNLOCK V3
IRIG-B SMB TODI board: Input: 4 Accuracy: offset from

DC Output: 12 per (supported by universal time
(DCLS) pair TODI boards in coordinated (UTC) <
slots 3 and 4) ±200 ns
Output: 120

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Signal Physical Maximum Maximum Description

Type Port Inputs/Outpu Inputs/Outputs
ts Supported Supported by
by Board SYNLOCK V3
1 PPS SMB TODI board: Input: not Accuracy: offset from

supported UTC < ±100 ns
Output: 4 per Output: 40
pair
PTP FE electrical PNSU board: Output: 160 (2  In compliance with
(1588 port/FE Output: 8 (1 of channels can be IEEE 1588v2
V2) optical the 8 outputs configured as  Accuracy: offset from
port/GE can be the input input.) UTC < ±100 ns
optical port when boards
are installed in
slots 1 and 2.)
1 RJ45 TODU board: Output: 160 (4 Accuracy: offset from
PPS+T Output: 8 (2 of channels can be UTC < ±100 ns
OD the 8 outputs configured as
can be the input.)
inputs when
boards are
installed in slots
1 and 2.)
NTP RJ45 TODI board: Input: 80  In compliance with
Input/Output: 4 the RFC1305
Output: 80 standard
 ms-level accuracy
3.3 Board Functions

This section describes the functions of each board.
3.3.1 LCIM Board

Input Port
Table 3-4 describes the input port function of the LCIM board.
Table 1.1 Input port function

Channel Signal Type Port Type
Quantity
8 E1 (2048 kbit/s), 2048 kHz, 10240 kHz, 75-ohm or 50-ohm

5120 kHz, 1024 kHz or CC For other impedance, an

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Channel Signal Type Port Type

Quantity
impedance converter is
required.
The signal type can be set on the NMS. Two adjacent LCIM boards can be configured to work
in hot backup mode or non-backup mode as required.
Timing Monitoring
Table 3-5 describes the timing monitoring function of the LCIM board.
Table 1.1 Timing monitoring function

Monitore Monitored Parameter Parameter Setting Date Reporting
d Item Period
Transmissi E1 (2048 kbit/s) (SSM, Real-time monitoring By event

on quality LOS, AIS, OOF, BPV, CRC,
FAS), 2048 kHz, 10240
kHz/5120 kHz/1024 kHz
(LOS), CC
Frequency 1 sampling point/100s Adjustable test Once every 15
offset (300s/1000s/3000s/10ks/1d/ period: 1 second to 1 minutes
user-defined period) day
Time 1 sampling point per - Once every minute
interval second, resolution: 1.25 ns
error (TIE)
Maximum 10 sampling points per Adjustable test Once every 15
time second, resolution: 1 ns period: 50 ms to 10 ks minutes
interval
error
(MTIE)
Time 10 sampling points per Adjustable test
deviation second, resolution: 0.01 ns period: 50 ms to 10 ks
(TDEV)
Phase  Any input signal from terrestrial lines
measureme  Output signals of active clock boards
nt
benchmark
 Output signals from the oscillator of a clock board
The SYNLOCK V3 provides the function of monitoring performance of timing clocks, with
parameters flexible configured. If the measurement result exceeds the preset alarm threshold,
an alarm will be generated in real time. The measurement results are reported periodically.

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3.3.2 SRCU/SOCU Board

Input Port
Table 3-6 describes the input port functions of the SRCU/SOCU board.
Table 1.1 Input port functions

Channel Signal Type Port Type Description
Quantity
4 E1(2048 kbit/s), 75-ohm or 50-ohm Used for simple

2048 kHz, or For other impedance, an configuration
10240 kHz/5120 impedance converter is
kHz/1024 kHz required.
1 GPS, Satellite antenna (2- Used for obtaining the
GPS/GLONASS, level lightning satellite signals from the
or GPS/BeiDou protection) peer board (for example,
the board in slot 0 and the
board in slot 12 are the peer
board for each other).
Selecting the Best Clock Source

Table 3-7 describes the function of selecting the best clock source of the SRCU/SOCU board.
Table 1.1 Selecting the test clock source

Principle Description Function Involved
in Source
Selection
Selection by 1-23 Specifies the priorities of Mandatory

priority different reference
sources.
Selection by LOS Determines whether a Mandatory
availability reference source is
available.
AIS, OOF, BPV, CRC, FAS, Determines the quality of Optional
FREQ, MTIE, TDEV a reference source.
SSM value Determines the input SSM Optional
level.
Majority voting Removes the worst Optional
reference source.
Manual Manually specifying whether Determines the range of Mandatory
blocking a reference source is available available reference
(enable/disable) sources.

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The external input timing signals can be transmitted transparently to the output board without
passing through the clock board. This is to avoid adverse impact brought by clock board
abnormality.
Clock Stratum
Table 3-8 describes the clock stratums of the SRCU/SOCU board.
Table 1.1 Clock stratums

Type Clock Board Satellite Module Redundancy
Configuration
Stratu SRCU GPS/GLONASS, GPS, Yes

m-1 GPS/BeiDou or RGPS
primar
y
refere
nce
clock
(PRC/
LPR)
Stratu SRCU - Yes
m-2
enhan
ced
clock
(ST2E
/TNC)
Stratu SOCU - Yes
m-3
enhan
ced
clock
(ST3E
/LNC)
The SYNLOCK V3 employs advanced hardware platform technology and intelligent software
technology to achieve the high quality clock performance.
The SRCU/SOCU board needs to be configured according to the clock stratum requirements.
For the stratum-3 enhanced clock (ST3E/LNC), the crystal oscillator is configured; for the
stratum-2 enhanced clock (ST2E/TNC), the rubidium clock is configured; for the stratum-1
primary reference clock (PRC/LPR), the rubidium clock and satellite module are configured.
The SRCU/SOCU board has the online fault monitoring function. If a fault is detected, a
board switchover is performed with the phase disturbance within several nanoseconds.

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Precise Clock Control

The SYNLOCK V3 features high-accuracy phase measurement (ns-level), high-speed data
sampling, and intelligent phase-lock software. With such features, the SYNLOCK V3 is able
to adjust the frequency and phase of local clocks more accurately and provide more reliable
locking and holdover performance.
Timing Monitoring
Table 3-9 describes the timing monitoring function of the SRCU/SOCU board.

Monitored Item Monitored Parameter Data
Parameter Setting Reporting
Period
Transmission quality, SSM, FREQ, TIE, For details, see the timing monitoring of the
MTIE, TDEV LCIM board.
When the LCIM board is not configured, the SRCU/SOCU board supports four input signals.
For details about the monitored items, see Table 3-10.

d Item Period
Transmissi E1 (2048 kbit/s) (SSM, Real-time monitoring By event

on quality LOS, AIS, OOF, BPV, CRC,
FAS), 2048 kHz, 10240
(LOS), CC
Frequency 1 sampling point/100s Adjustable test Once every 15
offset (300s/1000s/3000s/10ks/1d/ period: 1 second to 1 minutes
user-defined period) day
Time 1 sampling point per - Once every minute
interval second, resolution: 1.25 ns
error (TIE)
Maximum 10 sampling points per Adjustable test Once every 15
time second, resolution: 1 ns period: 50 ms to 10 ks minutes
interval
error
(MTIE)
Time 10 sampling points per Adjustable test
deviation second, resolution: 0.01 ns period: 50 ms to 10 ks
(TDEV)
Phase  Any input signal from terrestrial lines
measureme  Output signals of active clock boards
nt

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d Item Period
benchmark  Output signals from the oscillator of a clock board
Frequency Synthesis
The SRCU/SOCU board selects the primary reference according to the reference source
selection principle, and outputs stable timing signals after locking and filtering. After
frequency synthesis, the SRCU/SOCU board will generate various types of timing signals
(such as E1(2048 kbit/s), 2048 kHz, 10240 kHz/5120 kHz/1024 kHz, 64 kHz, IRIG-B, and 1
PPS) required for the SYNLOCK V3 to output, and even insert the SSM information into the
E1(2048 kbit/s) signal as required.
3.3.3 TSOU Board

Table 3-11 describes the timing output function of the TSOU board.
Table 1.1 Timing output function

Channel Quantity Signal Type Output Port
20  Master subrack: E1 (2048 75-ohm or 50-ohm

kbit/s), 2048 kHz, T1 For other impedance, an
(1544 kbit/s), 1544 kHz, impedance converter is required.
CC clock, and 10240
signals.
 Extended subracks 1 and 2:
E1 (2048 kbit/s), 2048
kHz, T1 (1544 kbit/s),
1544 kHz, and 10240 kHz
signals.
 Extended subrack 3: E1
(2048 kbit/s) and 2048 kHz
signals.
Different backup schemes (1+1 or 1:1) can be selected for two adjacent output slots. The 20
channels of each TSOU board are independent of each other, and they can select the output
signal type. A TSOU board cannot output T1 (1544 kbit/s), 1544 kHz, E1 (2048 kbit/s), and
2048 kHz signals at the same time. The TSOU board has the online fault monitoring function.
When a fault is detected, an alarm is reported immediately and automatic switchover is
performed. Software switchover or hot swapping can be performed for output boards with
redundancy backup, with the phase disturbance no more than 10 ns.
3.3.4 MITU Board

Maintenance Port
Table 3-12 describes the maintenance port function of the MITU board.

Copyright © Huawei
Table 1.1 Maintenance port function

Physical Port Quantity Rate
RS-232C (DB9) 2 Configurable baud rate

LAN port (RJ45) 1 10/100 Mbit/s
Fan monitoring port 1 9600 bit/s
The SYNLOCK V3 provides both low-speed and high-speed communication ports for
different networking requirements, such as the networking environment involving a large
number of synchronous digital hierarchy (SDH) transmission resources and the widely used
data communication network (DCN) (Ethernet port) networking.
Data Caching
Table 3-13 describes the data caching function of the MITU board.
Table 1.1 Data caching function

Monitored Item Caching of Event, Alarm and Performance data
Event and alarm 8000

information
Transmission Real-time reporting
quality and SSM
TIE 8192 TIE values per channel (5.6 days)
FREQ 512 groups of FREQ data per channel (5.3 days)
MTIE 512 groups of MTIE data per channel (5.3 days)
TDEV 512 groups of TDEV data per channel (5.3 days)
System Maintenance
The local maintenance terminal or remote monitoring center (NMS center) implements online
maintenance of the SYNLOCK V3 by using the MITU board. The MITU board maintains its
continuous communication with all the other boards using the communication bus, issues the
configuration and collects the status data and measurement data of all the other boards, and
then encapsulates the data using TL1 port (or protocol port defined by the vendor). The MITU
board provides powerful data caching capability and data loss avoidance function in case of
power-off, and logs important user operations.
Using TL1 and SNMP

The MITU board uses the industry's universal protocol for monitoring and management. Its
maintenance serial port uses the TL1 protocol and maintenance Ethernet port uses TL1 and
SNMP protocols. With the MITU board using TL1 and SNMP, the SYNLOCK V3 can be
managed by Huawei TL1 centralized maintenance terminal special for BITS equipment or the

Copyright © Huawei
iManager U2000, or be connected to the NMS of a third-party vendor for management of

BITS equipment of different vendors.
3.3.5 TODI Board

The TODI board provides the following functions:
 Supports NTP output from four independent Ethernet ports on the front panel.
 Supports time synchronization signals output from the latter 16 channels. The port type
of the output time synchronization signals includes IRIG-B DC (DCLS), RS-232, and 1
PPS.
 Receives time input from external time synchronization signals DCLS (TTL/RS-232).
 Receives NTP input signals, or obtains DCLS time synchronization signals from the
clock unit. The first four channels of the TODI board can also receive time input from an
external synchronization port for obtaining time synchronization signals.
 Sends the input time synchronization signals into the delay compensation module and
holdover module for related processing. The processed signals are selectively output
after codec, format conversion, driving, and protection.
3.3.6 TDRV Board

The TDRV board achieves clock driving and timing re-distribution for the extended subrack,
and generates various types of clock signals required for the output boards. Generally, TDRV
boards are configured in pairs, which ensures good phase discontinuity performance. The
TDRV board supports online maintenance and hot swapping, and also provides the online
fault monitoring function.
3.3.7 PNSU Board

The PNSU board provides the following functions:
 Complies with 1588v2 for frequency and time synchronization.
 Provides seven SFP GE/FE optical ports and one FE electrical port for PTP
communication.
 Supports the frequency synchronization protocol G.8265.1 and functions as the grand
master or a client.
 Receives external time synchronization signals and restores clock time signals; supports
synchronous Ethernet.
 Provides clock source input for clock boards; receives signals output by clock boards and
outputs such signals after format conversion.
 Locks external time reference sources and provides the holdover function when the input
time synchronization signals are lost.
 Receives input time synchronization signals and outputs such signals after smoothing
processing, and provides delay compensation.
 Monitors and maintains input/output signals and key components.
3.3.8 TODU Board

The TODU board provides the following functions:
 Supports 1 PPS+TOD high-accuracy time synchronization.
 Provides eight 1 PPS+TOD time synchronization ports.

Copyright © Huawei
 Provides clock source input for clock boards; receives signals output by clock boards and
outputs such signals after format conversion.
 Receives input time synchronization signals; provides delay compensation.
 Provide delay compensation for 1 PPS+TOD signal transmission.
 Monitors and maintains input/output signals and key components.
3.4 Characteristics
This section describes the characteristics of the SYNLOCK V3.
3.4.1 Compact Structure and Flexible Configuration

 Compact structure
The SYNLOCK V3 with a single subrack provides a maximum of 100 traditional frequency
synchronization outputs and 80 high-accuracy time synchronization outputs. With all the four
subracks (full configuration), the SYNLOCK V3 provides a maximum of 400 traditional
frequency synchronization outputs and 80 high-accuracy time synchronization outputs,
applicable for any clock stratum. The SYNLOCK V3 can be installed in the 19-inch or ETSI
standard cabinet.
 Flexible configuration
With different boards configured, the SYNLOCK V3 can function as a frequency
synchronization device, high-accuracy time server, or clock monitoring device. With different
oscillators (rubidium or crystal oscillator) and satellite modules (GPS, GPS/GLONASS, or
GPS/BeiDou), the clock boards of the SYNLOCK V3 can obtain different clock stratums.
 Compatible input/output slots
Compatible input/output slots enable users to maximally use slots, expanding the output
capacity or timing monitoring capability. In terms of output, a single subrack supports a
maximum of 100 outputs; for input, a single subrack provides a maximum of 80 monitoring
channels. The SYNLOCK V3 employs precise timing measurement to collect and assess the
network timing performance, which facilitates fault location and network optimization.
3.4.2 Complete Functions and Flexible Use

 Abundant ports
The SYNLOCK V3 provides abundant timing input/output ports and time input/output ports,
with their signal types configurable. Such ports facilitate user operations and improve
resource usability. Also, the SYNLOCK V3 provides various type of maintenance ports that
comply with standard protocols, facilitating networking.
 Comprehensive monitoring functions
The SYNLOCK V3 is able to monitor and measure any input (including satellite benchmark
input) in real time. The items monitored are complete, including LOS, AIS, OOF, BPV, CRC,
SSM, TIE, MTIE, TDEV, and frequency offset. The performance measurement of such items
is precise and related alarm thresholds are configurable.
 Precise monitoring

Copyright © Huawei
The SYNLOCK V3 implements timing performance monitoring that features multiple ports
(eight inputs per board), high accuracy (phase resolution: 1 ns), high real-time (high-speed
sampling, periodic reporting of data or query of data at any time), multiple sampling points
(10 sampling points τI for both MTIE and TDEV), and wide range (τI range: 50 ms to 10 ks).
 Selection of best clock source
The SYNLOCK V3 provides multiple principles of clock source selection (such as selection
by SSM, by priority, by alarm threshold, by majority voting, and by availability). These
principles can be used together for selecting the best primary reference source.
Majority voting achieves voting to abnormal sources with the participation of multiple
primary reference sources. This is to discover in time the degradation of the primary reference
source, deterioration of the clock oscillator, and GPS timing degradation.
3.4.3 High Reliability and Superior EMC

 Redundancy of all timing channels
The SYNLOCK V3 employs the redundancy backup design. With this design, faults of any
board will not cause deterioration, degradation or even interruption of the clock output. The
system has excellent MTBF performance and all boards support hot swapping, hence
imposing no impact on output signals.
 Power supply and heat dissipation
The SYNLOCK V3 uses the DC-DC module for power supply.
The entire system use two -48 V inputs for power supply. Each board of the SYNLOCK V3 is
able to monitor the working status of the power supply and is protected against overvoltage
and overcurrent.
 Advanced manufacturing techniques
The SYNLOCK V3 employs advanced hardware design. Its PCB has a maximum of 12
layers, with high integration and low power consumption. The manufacturing techniques of
the boards are advanced.
 Superior EMC
The SYNLOCK V3 uses the metallic and fully-enclosed subrack. The signal ports and
backplane PCB are integrated for simplifying signal transfer. Techniques and measures such
as cable shielding, isolation protection, match filtering, and port impedance normalization are
employed to ensure that the SYNLOCK V3 has superior EMC performance. Specifically, the
EMC performance of the SYNLOCK V3 meets international EMC standards and passes the
CE certification, enabling the SYNLOCK V3 to have high environment adaptability.
3.4.4 Ease-of-Maintenance
The SYNLOCK V3 uses the TL1 protocol for monitoring and management, and it also
supports the SMMP protocol for monitoring and management. The SYNLOCK V3 can be
connected to Huawei TL1 centralized maintenance terminal special for BITS equipment,
Huawei iManager U2000, or a third-party NMS.
The maintenance terminal, using the user-friendly man-machine interface of the Windows
operating system (OS), efficiently monitors and manages the SYNLOCK V3 and the entire
system with mouse-clicks on menus. By analyzing and processing its collected statistical data,
the maintenance terminal efficiently evaluates the synchronization performance of the

Copyright © Huawei
communication network to master the network running status in real time. Such information
facilitates optimization of synchronization networks.

Copyright © Huawei
SYNLOCK V3 BITS(SSU,SASE) Product Configuration and ApplicationProduct
Product Description Configuration and Application
4 Product Configuration and Application
About This Chapter

This section describes the application scenario, configuration, and networking of frequency
synchronization.
4.3 Clock Monitoring

This section describes the application scenario, configuration, and networking of frequency
synchronization.
4.1.1 Application Scenario

SDH
In SDH transport network environment, timing reference signals of the synchronization
network need to be transmitted by the SDH transport network and at the same time, the
synchronization of the SDH transport network requires support of the synchronization
network. In other words, the SDH transport network is both the user and carrier of the
synchronization network, which means they interrelate with each other.
The three synchronization modes of the synchronization network are proposed with the focus
only on network topology, while the four synchronization modes employed by the SDH
transport network consider both network-wide planning and synchronization performance
provided by the equipment. The equipment synchronization performance is related to the
current working status of the equipment.
In a word, the synchronization function of the SDH transport network is a prerequisite for
network-wide synchronization.

Copyright © Huawei
GSM Base Station

The frequency accuracy of the air interface for the global system for mobile communications
(GSM) wireless base station is required to be ±50 ppb, which is based on the service
requirements of switching mobile phone signals between BTSs. Generally, users can store
data for 10-30 ms. Therefore, a time of 50 ppb later, the service will still be lost. The data can
be saved for as long as about 200-600 thousand seconds. For details about the frequency
synchronization requirement of the GSM base station, see the ESTI TS 145.010 [B3].
UMTS Base Station/ LTE FDD Base Station

The frequency accuracy of the air interface for the Universal Mobile Telecommunication
System (UMTS)/frequency division duplex (FDD) base station is required to be ±50ppb. Both
modes do not have time synchronization requirements.
In conclusion, the wireless frequency synchronization base station requires that its clock
synchronization meet the frequency accuracy of ±50 ppb. For transparent transmission of the
time division multiplexing (TDM) private line service, its synchronization performance needs
to meet the synchronization standards of related service interfaces defined in G.823/G.824.
Traditional packet switched networks, however, are asynchronous networks, which do not
have the synchronous network features like the SDH network. To meet these frequency
synchronous transmission requirements, technologies using packet switched networks to
transmit frequencies are developed, such Ethernet physical layer synchronization and TOP.
For details about the frequency synchronization requirement of the UMTS base station/ LTE
FDD base station, see the TS 125.104 [B4].
4.1.2 Typical Configuration

 Full configuration
In full configuration of the SYNLOCK V3, four subracks (one master subrack and three
extended subracks) and five types of boards are configured. Each subrack has 10 I/O slots and
provides a maximum of 100 outputs (20 x 5). The entire system with three subracks supports
a maximum of 400 outputs. For the clock stratum requirements, different modules are
configured for the SRCU/SOCU board to provide the required stratum-1 primary reference
clock (PRC/LPR), stratum-2 enhanced clock (ST2E/TNC), or stratum-3 enhanced clock
(ST3E/LNC).
 Standard configuration
In standard configuration of the SYNLOCK V3, one master subrack and four types of boards
are configured, which supports flexible clock stratums. The input board is used independently
for monitoring. This configuration meets high-end users' requirements for multiple functions
of BITS.
 Simple configuration
In simple configuration of the SYNLOCK V3, a master subrack and three types of boards are
configured. The input board is not configured, whose function (external reference input) is
provided by the clock board. The SYNLOCK V3 with such configuration provides four inputs
and 100 outputs (all of which have redundancy configuration) and has flexible clock stratums.
This configuration meets low-end users' requirements for low-price BITS.

Copyright © Huawei
PRC/LPR
PRC/LPR is used for the core node or importance node in a network. Table 4-1 lists its typical
configuration.
Table 1.1 PRC/LPR (typical configuration)

Board Type Board Quantity Slot
(Optional) LCIM 2 Slots 1 and 2 of the master subrack

 SRCU+GPS 2 Slots 0 and 12 of the master subrack
 SRCU+GPS/G
LONASS
 SRCU+GPS/B
eiDou
TSOU 8 Slots 3–10 of the master subrack
MITU 1 Slot 11 of the master subrack
ST2E (TNC)
ST2E (TNC) is used for the service convergence node. Table 4-2 lists its typical
configuration.
Table 1.1 ST2E (TNC) (typical configuration)


SRCU 2 Slots 0 and 12 of the master subrack
ST3E (LNC)
ST3E (LNC) is used for the local node. Table 4-3 lists its typical configuration.
Table 1.1 ST3E (LNC) (typical configuration)


SOCU 2 Slots 0 and 12 of the master subrack

Copyright © Huawei
(Optional) LCIM configuration: To facilitate the configuration of the PNSU or TODU board
in the future, it is recommended that the LCIM board not be configured in slot 1 or 2. Instead,
the four expansion inputs of the SRCU/SOCU board are used to achieve the synchronous
frequency input. Alternatively, the LCIM board is configured for the synchronous frequency
input.
1588 ACR Frequency Server

Table 4-4 shows the board configuration of the SYNLOCK V3 that functions as the 1588
ACR frequency server.
Table 1.1 1588 ACR frequency server (typical configuration)

Type Quantity Slot
SRCU 1–2 Slot 0 or 12 of the master subrack

PNSU 1–20 Slots 1–10 of the master subrack and extended
subrack (Slot 1 or 2 can be set to the input mode.)
Stratum-1 Time Server

Table 4-5 shows the board configuration of the SYNLOCK V3 that functions as the stratum-1
time server.
Table 1.1 Stratum-1 time server (typical configuration)

Type Quantity Slot
SRCU (A 2 Slots 0 and 12 of the master subrack

satellite card
needs to be
configured.)
PNSU 1–20 Slots 1–10 of the master subrack and extended
subrack (Slot 1 or 2 can be set to the input mode.)
4.1.3 Network Application

This section covers the topology and description of the network for traditional frequency
synchronization and the network for 1588 adaptive clock recovery (ACR) over IP.
Network Topology of Traditional Frequency Synchronization

Figure 4-1 shows the network topology of traditional frequency synchronization.

Copyright © Huawei
Figure 1.1 Network topology of traditional frequency synchronization
Network Description of Traditional Frequency Synchronization

In SDH transport network environment, timing reference signals of the synchronization
network need to be transmitted by the SDH transport network and at the same time, the
synchronization of the SDH transport network requires support of the synchronization
network. In other words, the SDH transport network is both the user and carrier of the
synchronization network, which means they interrelate with each other.
The SYNLOCK V3 provides the traditional frequency synchronization interface that supports
local primary reference (LPR), transmit node clock (TNC), and local node clock (LNC).
Network Topology of G.8265.1-based 1588 ACR

Figure 4-2 shows the network topology of 1588 ACR.
Figure 1.1 Network topology of 1588 ACR

Copyright © Huawei
Network Description of G.8265.1-based 1588 ACR

The
SYNLOCK V3 functioning as a 1588 ACR master is deployed at the convergence layer or
core layer of the bearer network, through which 1588 ACR are forwarded. A network device
or base station, serving as a 1588 ACR slave, restores frequency from 1588 ACR packets for
synchronization with the master.

This section describes the application scenario, configuration, and networking of time
synchronization.
4.2.1 Application Scenario

Billing System
Time synchronization is required for billing considering two aspects:
 Billing for the communication network itself
 Cross-network billing involving different carriers
Currently, each switch has a call-record-generating module. This module generates call
detailed records (CDRs), with time labels marking the start time, end time, and duration of
calls. It then sends the CDRs to the billing center for processing. Generally, the clock
accuracy of a billing module is 1E-5 or 1E-6 (relatively low), which means that the time
difference between two switches may reach 30s after a month.
Due to the great time difference between MSC switches, different CDRs may be generated for
the same calls, which may cause user complaints. For example, the caller in a call is in
different time stages. Carriers also face issues such as interoperability and cross-network
settlement issues. Against this backdrop, accurate time synchronization is required, which will
greatly improve the accuracy of cross-network settlement and reduce related disputes. With
the billing unit becoming smaller and smaller, the time accuracy of communication devices
such as switches become more and more important.
The time synchronization accuracy for billing in the communication network is required to be
around 500 ms.
NMS of Communication Networks

Currently, most of the communication networks have their own centralized NMS. Such an
NMS collects the network performance data for performance measurement and also collects
the alarm information about various NEs for alarm locating. The alarm information reported
by each device contains the time label marked by their own clocks. If these clocks are
synchronized, the NMS is able to arrange the alarms by time, facilitating fault location.
The time synchronization accuracy for the NMS of communication networks is required to be
around 500 ms.

Copyright © Huawei
SS7 Monitoring System

At the signaling transfer points (STPs) that have heavy signaling traffic, signaling sampling
points need to be set up for accurately locating fault types and points on a communication
network. In addition, a set of signaling system No.7 (SS7) monitoring system is required for
monitoring and analyzing the status of signaling streams. When a fault occurs on the network,
all related signaling streams are sent to the SS7 monitoring system for analysis, processing,
and fast fault locating. To avoid fake information caused by incorrect sequence of signaling
streams, the time information of all signaling streams must be correct. However, the time
labels of signaling streams are provided by different signaling sampling points. In this case,
time synchronization is required for all signaling sampling points.
In addition, when the SS7 monitoring system is used for collecting statistics of put-through
rates and call loss rates in a network, the statistics collected may have errors if the time of
different signaling sampling points is not synchronized. This will affect the performance
evaluation of the entire network.
The time synchronization accuracy for the SS7 monitoring system is required to be around 1
ms.
CDMA2000 Base Station (Frequency Synchronization+Time Synchronization)

The frequency synchronization accuracy of the CDMA2000 base station is required to be ±50
ppb. All CDMA2000 base stations use the unified CDMA system clock, whose time is from
the UTC time of GPS. In addition, it is recommended that the time difference between base
stations be less than 3 μs.
For details about the time synchronization requirement of the CDMA2000 base station, see
the 3GPP2 C.S0010-B and 3GPP2 C S0002-B.
TD-SCDMA Base Station (Frequency Synchronization+Time Synchronization)

The frequency synchronization accuracy of the time division-synchronous code division
multiple access (TD-SCDMA) base station is required to be ±50 ppb; also the time difference
between adjacent base stations is required to be less than 3 μs.
For details about the time synchronization requirement of the TD-SCDMA base station, see
the 3GPP TR 25.836.
High-accuracy time synchronization is required between the preceding base stations.
Specifically, the time accuracy is required to be ±1 μs to ±3 μs, and the frequency accuracy is
required to be ±50 ppb.
Traditional time synchronization links are NTP-based. The biggest disadvantage of NTP is
that its time transmission accuracy reaches only the ms level. This is far from the time
accuracy at the μs level required by the wireless time synchronization base station. Therefore,
to meet the requirement of transmitting high-accuracy time over the packet switched network,
IEEE develops the IEEE 1588v2 protocol, which supports time synchronization at the sub-
microsecond level. The accuracy of 1588v2 is close to that of the GPS scheme, but owing to
its advantages in cost, maintenance, and security, 1588v2 becomes the most popular time
transmission protocol in the industry.
LTE TDD Base Station (Frequency Synchronization+Time Synchronization)

The frequency synchronization accuracy of the LTE time division duplex (TDD) base station
is required to be ±50 ppb; also the time difference between adjacent base stations is required
to be less than 2.5 μs.

Copyright © Huawei
For details about the time synchronization requirement of the LTE TDD base station, see the
ESTI TS 125.105 [B5].

1588v2 Time Server Configuration
When the SYNLOCK V3 functions as a 1588 time server, its boards are configured as listed
in Table 4-6.
Table 1.1 Configuration of boards on the SYNLOCK V3

Board Name Board Quantity Slot
SRCU 1-2 Slot 0 or 12 of the master subrack

TODU 1-20 Slots 1 to 10 of the master subrack or
extended subrack (Slot 1 or 2 can be set to
the input mode.)
PNSU 1-20 Slots 1 to 10 of the master subrack or
extended subrack (Slot 1 or 2 can be set to
the input mode.)
When configured as a stratum-1 time server, the SYNLOCK V3 requires two SRCU boards,
2-20 TODU/PNSU boards, and one MITU board. A satellite card is required for both SRCU
boards.
NTP Time Server Configuration

When the SYNLOCK V3 functions as an NTP time server, its boards are configured as listed
in Table 4-7.
Table 1.1 Configuration of boards on the SYNLOCK V3

Board Name Board Quantity Slot
SOCU/SRCU 1-2 Slot 0 or 12 of the master subrack

TODI 1-20 Slots 1 to 10 of the master subrack or
extended subrack
When configured as a stratum-1 time server, the SYNLOCK V3 requires 1-2 SOCU/SRCU
boards, 2-20 TODI boards, and one MITU board. A satellite card is required for the
SOCU/SRCU board.
When configured as a stratum-2 time server, the SYNLOCK V3 requires 1 to 2 SOCU/SRCU
boards, 1 to 20 TODI boards, and 1 MITU board.

Copyright © Huawei
4.2.3 1588 Time Server Networking

This section describes the network mode, and provides the network topology and network
description for the time synchronization supported by the SYNLOCK V3.
Network Topology
Figure 4-3 shows 1588v2 networking.
Figure 1.1 1588v2 networking
Boundary clock (BC) and ordinary clock (OC) are working device modes defined in IEEE 1588v2.

Copyright © Huawei
 BC: clock device in an intermediate network node. This device provides multiple 1588 ports, with
one functioning as a slave port and the others master ports. The slave port synchronizes the
frequency and time of the system clock to the upper-layer device, and the master ports implement
layer-by-layer time transfer.
 OC: start or end clock device in the network. This device provides only one 1588 port, either slave
or master.
Network Description
As a time server, the SYNLOCK V3 supports 1588v2 networking mode in the entire network.
 All devices in the network implement time synchronization. Devices at the convergence
layer lock BITS, device at the access layer lock devices at the convergence layer, and
devices in base stations lock the access devices.
 Time information can be transmitted to base stations that do not support PTP ports in 1
PPS+TOD mode.
 The BITS transmits time information to devices in the bearer network in 1 PPS+TOD
mode.
 This networking mode supports protection of clock sources. When the working BITS is
faulty, the other BITS (protection BITS) switches to work. To achieve this, the best
master clock (BMC) algorithm needs to be enabled in the network.
 The BC networking scheme for the bearer network is a recommended scheme, which
features highest accuracy, good source protection, and good line protection.
4.2.4 NTP Server Networking

The client/server mode is the most common working mode of the NTP time synchronization
system, enabling the time synchronization system to work in various network topologies. For
example, in a hierarchical time synchronization network, the stratum-1 time server works in
server mode and the stratum-2 time server works in client and server modes. The stratum-2
time server obtains the accurate time from the upper-stratum time server and provides time
signals to a lower-stratum time server or directly to network terminals. As a client, the
stratum-2 server can have multiple upper-stratum time servers at the same time. The NTP
protocol then uses the clock filtering algorithm to calculate the optimal upper-stratum time
server and select this server as the time source.

Copyright © Huawei
Figure 1.1 NTP client/server networking
4.3 Clock Monitoring

This section describes the configuration and networking of clock monitoring.

A clock monitoring system requires one or two SRCU/SOCU boards, one MITU board, and
multiple LCIM boards.
The number of LCIM boards is determined according to the test capacity. Each LCIM board
is able to monitor eight channels of clocks, and a maximum of 10 LCIM boards can be
configured for the system. Therefore, a maximum of 80 channels of clocks can be configured.
For the hardware in the clock monitoring system, SRCU/SOCU and MITU boards are
configured in the corresponding slots, but all the 10 slots are available for the LCIM board.
For the convenience of configuring the TODI, PNSU, or TODU board, it is recommended that
the LCIM board be configured in slots following the priorities in descending order: slots 5, 6,
7, 8, 9, and 10, and then slots 1, 2, 3, and 4. Note that in the clock monitoring system, the
eight channels of hardware jumpers inside the LCIM board must be set to non-backup mode.
The LCIM board in each slot corresponds to different input ports, as listed in Table 4-8.

Copyright © Huawei
Table 1.1 Mapping relationship between LCIM boards and input ports on the front panel
Slot for the LCIM Board SMB Connectors on the Chassis Port Area
1 A1-A8
2 A9-A16
3 B1-B8
4 B9-B16
5 C1-C8
6 C9-C16
7 D1-D8
8 D9-D16
9 E1-E8
10 E9-E16
4.3.2 Network Application

Figure 4-5 illustrates the principle of clock monitoring.
Figure 1.2 Principle of clock monitoring
In the clock monitoring system, the test port of the BITS device is used to lead in signals
output from the service device. These signals are compared with the BITS clock signals and
TIE is tested to calculate MTIE and TDEV. The test result and calculation result are then
reported, through the maintenance port of the BITS device, to the monitoring center for

Copyright © Huawei
centralized processing. In this way, the monitoring center is able to monitor the timing quality
of service devices in the entire network.

Copyright © Huawei
Product Description Device ManagementDevice Management
5 Device Management
About This Chapter

5.1 Overview
5.2 Centralized Maintenance Terminal Mode
5.3 CLI Mode
5.4 iManager U2000 Management Mode
5.1 Overview
You can manage, maintain, and monitor the SYNLOCK V3 using the centralized maintenance
terminal, U2000, and command-line interface (CLI).
 Centralized maintenance terminal
The SYNLOCK centralized maintenance terminal (based on the TL1 language) provides
GUIs to manage Huawei BITS synchronization devices. It is compact, provides
extensive functions, and is easy to use. Besides, it can run in common Windows OSs,
having a low requirements on the hardware and software of the operating system (OS).
The basic software package of the SYNLOCK centralized maintenance terminal can
function as a local craft terminal (LCT) that can manage a local BITS device. The basic
software package together with the extended software package can function as a mini
network management system (NMS) that can manage up to 255 BITS devices,
applicable for regular time synchronization management on small or medium networks.
 CLI
Among the three management modes, CLI has the lowest requirements on operating
environments. Instead of using dedicated software, you can access the SYNLOCK V3
for management and maintenance using the CLI program of the Windows OS (serial port
mode) or through remote login (network port mode). CLI is not as intuitive as GUI and
therefore is commonly used for temporary maintenance and management.
 U2000
The iManager U2000 is a unified GUI NMS platform of Huawei and is implemented
using the SNMP language. It can manage a wide set of mainstream devices in the access
and transport domains, but has high requirements on OS (such as Windows, Linux, and

Copyright © Huawei
UNIX) hardware and software. U2000s with different software and hardware
configurations support different management capacities (ranging from 2,000 to 20,000
BITS devices) and are generally used on large networks for time synchronization
management. The U2000 differs from the SYNLOCK centralized maintenance terminal
in that the U2000 supports the client/server working mode, active/standby server
protection, and northbound interfaces (NBIs).
5.2 Centralized Maintenance Terminal Mode

In centralized maintenance terminal mode, the SYNLOCK centralized maintenance terminal
(based on the TL1 language) is used to manage and maintain the SYNLOCK V3. The
terminal provides GUIs for the monitoring and maintenance of multiple devices, which is
user-friendly.
Based on the support of the centralized maintenance terminal for the lower-layer protocols,
the SYNLOCK V3 can be maintained in two modes:
 Local mode: The centralized maintenance terminal is directly connected to the
SYNLOCK V3 using the serial port or the local area network (LAN), or both.
 Remote mode: The centralized maintenance terminal can remotely log in to the
SYNLOCK V3 through the digital data network (DDN), public switched telephone
network (PSTN), or data communication network (DCN) for maintenance.
The centralized maintenance terminal can maintain multiple (a maximum of 255) SYNLOCK
V3s concurrently. Such BITS devices can be connected to the centralized maintenance
terminal in either of the above-mentioned modes. Considering the network speed and software
performance, it is recommended that one centralized maintenance terminal manage no more
than 20 SYNLOCK V3s.
5.2.1 Running Environment

Hardware Requirement
Table 5-1 lists the minimum configuration of the PC used for the centralized maintenance
NMS.
Table 1.1 Minimum configuration of the PC

Item Minimum Configuration
CPU P4 2.66 GHz

Memory 512 MB
Hard disk 40 GB
Software Requirement
Table 5-2 lists the configuration of the software requirement for the centralized maintenance
NMS.

Copyright © Huawei
Table 1.1 Software requirement

Item Typical Configuration
Software SYNLOCK centralized maintenance terminal software

Operating system Microsoft Windows 2000 Professional, Microsoft Windows
98, Microsoft Windows NT 4.0, Microsoft Windows XP, or
Microsoft Windows 7
Minimum resolution for 1024 x 768
display
Font Small size
5.2.2 Management Functions

Table 5-3 describes the management functions of the centralized maintenance NMS.
Table 1.2 Management functions of the centralized maintenance NMS

Function Description
NE view Network-level management of BITS NEs

User management User rights and password management
Configuration Management of system working parameters, board parameters,
management and output signals; data loading
Monitoring maintenance Board monitoring, monitoring of clock board's work,
monitoring of input reference source board's work, and
monitoring of output signals
Alarm Management of minor alarms, major alarms, critical alarms,
current alarms, and historical alarms; alarm query
Performance Storage and query of historical data; monitoring of
transmission quality; display of offset, TIE, MTIE, and TDEV
measure data
Log management Recording and query of historical operations
Database maintenance Deletion, backup, or restoration of data in the database;
deletion of backup data; maintenance and planning of database
5.2.3 Typical Networking

This section describes two typical networking schemes.
Networking for LAN/DCN

The legacy DCN is used, and the SYNLOCK V3 and the centralized maintenance terminal are
assigned proper network resources (IP addresses and Ethernet physical port). In this way,

Copyright © Huawei
SYNLOCK V3s are able to be monitored and managed in a centralized manner. Figure 5-1
shows the network topology.
Figure 1.1 Network topology for LAN/DCN
E1 Bridging Networking
This networking is based on E1 bridges and transmission links. There is an E1 bridge between
each SYNLOCK V3 node and the centralized maintenance terminal. The E1 bridge is
connected to the transmission device through E1 circuits, and to the SYNLOCK V3 or
centralized maintenance terminal through the Ethernet, as shown in Figure 5-2.

Copyright © Huawei
Figure 1.1 E1 bridging network topology
5.3 CLI Mode

In CLI mode, users can locally log in to the SYNLOCK V3 by using a serial port or remotely
log in to the SYNLOCK V3 by using an Ethernet port for management and maintenance.
5.3.1 Running Environment

In CLI mode, the software of the operating system (OS) or certain simple application software
provides the maintenance interface.
The TL1 physical ports provided by the SYNLOCK V3 includes the Ethernet port and serial
port. The console of the SYNLOCK V3 uses the RS-232 serial port. Users can use the
HyperTerminal of the Windows OS for communication with the SYNLOCK V3 by using a
terminal communication cable.
The following configurations need to be performed on the HyperTerminal:
1. Set Bits per second to 115200, Data bits to 8, Parity to None, Stop bits to 1, and Flow
control to None.
2. Open the HyperTerminal. In the main interface, choose File > Properties.
3. In the dialog box that is displayed, click Settings. On the Settings tab, click ASCII
Setup.
4. In the dialog box that is displayed, select Echo typed characters locally. For other
parameters, use the default settings.
5. Click OK.In addition, the SYNLOCK V3 provides the interface for remote login on
TCP/IP port 3000 for receiving TL1 commands and sending related information.
Copyright © Huawei
5.3.2 Features
The CLI mode has the following features:
 Provides multiple methods for both local and remote maintenance.
 Provides different operation permissions of configuration commands for users of
different rights to prevent illegal intrusion of unauthorized users or incorrect operation.
 Provides abundant commands for configuration, maintenance and debugging, as well as
detailed command prompt messages.
5.4 iManager U2000 Management Mode

The iManager U2000 V100R006C02 or higher can manage SYNLOCK V3 BITS devices in a
comprehensive manner. It supports the client/server working mode, cross-domain (access and
transport domains) management, and NBIs. U2000s with different software and hardware
configurations support different management capacities, ranging from 2,000 to 20,000 BITS
devices. For details, see the iManager U2000 Product Documentation.
The iManager U2000 of a version between V100R005 and V100R006C02, although able to manage the
SYNLOCK V3, is not recommended because its management features are not as comprehensive as the
iManager U2000 of V100R600C02. Patch V100R006C02SPC300+CP3203,
V100R006C02SPC300SPC302, or higher is recommended.
The iManager U2000 V100R006C02 or a later version can well manage the SYNLOCK V3.
It supports the client/server mode, access/transport cross-domain management, and
northbound interfaces. For details, see the iManager U2000 Product Documentation.
 A user can use the U2000 to log in to a BITS device by using the user name and password of the
device. The BITS devices support the administration, maintenance, and monitoring rights for users.
Passwords for administration users, default maintenance users, and maintenance users created by
administration users need to be changed periodically to ensure password security. For how to change
passwords, see section 4.4.3 Setting a BITS User Password in SYNLOCK V3 BITS V300R003C10
Operation Manual.
 The iManager U2000 of a version between V100R005 and V100R006C02, although able to manage
the SYNLOCK V3, is not recommended because its management features are not as comprehensive
as the iManager U2000 of V100R600C02.

Copyright © Huawei
SYNLOCK V3 BITS(SSU,SASE) Technical Specifications and Standards ComplianceTech
Product Description nical Specifications and Standards Compliance
6 Technical Specifications and Standards

Compliance
About This Chapter

6.1 Technical Specifications
6.2 Standards Compliance
6.1 Technical Specifications

This section describes the device parameters and performance indicators of the SYNLOCK
V3.
6.1.1 Device Parameters

Dimensions
Table 6-1 lists the dimensions of the SYNLOCK V3.
Table 1.1 Dimensions of the SYNLOCK V3

Item Dimensions (H x W x D)
N66-22Cabinet  2200 mm x 600 mm x 600 mm (86.81 in. x 23.62 in. x 23.62 in.)
(19-inch  2600 mm x 600 mm x 600 mm (102.36 in. x 23.62 in. x 23.62 in.)
standard cabinet) (An upper enclosure frame with a height of 400 mm is required.)
N63E-22Cabinet  2200 mm x 600 mm x 600 mm (86.81 in. x 23.62 in. x 23.62 in.)
(ETSI cabinet)  2600 mm x 600 mm x 600 mm (102.36 in. x 23.62 in. x 23.62 in.)
(An upper enclosure frame with a height of 400 mm is required.)
Subrack  Without mounting ears: 575 mm x 436 mm x 253 mm (22.64 in. x
17.17 in. x 9.96 in.)
 With mounting ears for the 19-inch cabinet: 575 mm x 482.6 mm x

Copyright © Huawei
Item Dimensions (H x W x D)
253 mm (22.64 in. x 19 in. x 9.96 in.)

 With mounting ears for ETSI cabinet: 575 mm x 530 mm x 253 mm
(22.64 in. x 20.87 in. x 9.96 in.)
Board  SOCU/SRCU/TDRV: 350 mm x 72 mm x 235 mm (13.78 in. x 2.83
in. x 9.25 in.)
 TODI/LCIM/TSOU/MITU/PNSU/TODU: 350 mm x 24 mm x 235
mm (13.78 in. x 0.94 in. x 9.25 in.)
Weight
 Master subrack in full configuration: 18 kg
 Extended subrack in full configuration: 18 kg
Operating Environment
1. Long-term operating
− Temperature: 0 °C to 40 °C
− Humidity: 5%-90% RH
2. Short-term operating (within 24 hours)
− Temperature: -5 °C to +55 °C
− Humidity: 5%-95% RH
Power Supply Parameters

Table 6-2 lists the power supply parameters of the SYNLOCK V3.
Table 1.1 Power supply parameters of the SYNLOCK V3

Parameter Specification
Power supply mode DC

Rated voltage -48/-60 V DC
Operating voltage range -38.4 V DC to -72 V DC
Power Consumption
 Maximum power consumption of the master subrack: 298 W.
 Maximum power consumption of the fan tray: 70 W (N63E-22)
 Power consumption when the fan tray is running normally: 15 W (N83E-22)
 Maximum power consumption of the fan tray: 150 W (N66-22)
 Power consumption when the fan tray is running normally: 30 W (N66-22)
 Maximum power consumption of the extended subrack: 182 W.

Copyright © Huawei
Table 6-3 lists the power consumption of each board.
Table 1.1 Board power consumption

Board Maximum Power Consumption (W)
LCIM 13.6
SRCU 120.3
SOCU 86.1
PNSU 17.7
TODU 11.5
TSOU 6.26
TODI 13.6
TDRV 26.1
MITU 14.1
6.1.2 Frequency Synchronization Performance Counters

Table 6-4 lists the frequency synchronization performance counters.
Table 1.2 Frequency synchronization performance counters

Item ITU-T Requirement SYNLOCK V3Vendor
Requirement
PRC/LPR performance
Wander generation MTIE See Figure 6-1. See Figure 6-1.
(satellite locking)
Wander generation TDEV See Figure 6-2. See Figure 6-2.
(satellite locking)
Frequency accuracy < 1E-11 < 4E-12
Output jitter 24.4 ns Typical value: 5 ns
Phase discontinuity 1/8UI (61 ns) Less than 15 ns
Holdover performance 1E-10 per day 5E-11 per day, 1E-10 per 3 days,
3E-10 per 7 days
ST2E (TNC) and ST3E (LNC)
Free-run frequency ST2E: 1.6E-8 ST2E: 5E-10 per year
accuracy ST3E: 4.6E-6 ST3E: 2E-7 per year
Wander generation See Figure 6-3, Figure 6-4, ST2E: see Figure 6-3 and Figure
Figure 6-6, or Figure 6-7. 6-4.

Copyright © Huawei
Item ITU-T Requirement SYNLOCK V3Vendor

Requirement
ST3E: see Figure 6-6 and Figure

6-7.
Wander transfer See Figure 6-5 or Figure 6- ST2E: see Figure 6-5.
8, ST3E: see Figure 6-8.
Holdover performance ST2E: 1E-10 per day ST2E: 5E-11 per day, 1E-10 per
ST3E: 1E-9 per day 3 days, 3E-10 per 7 days
ST3E: 9E-10 per day, 3E-9 per 3
days
Output port wave shape See sections 6 and 10 in The same as ITU-T
ITU-7 G.703. recommendations.
Pull-in range 1.6E-8, 4.6E-6 1.6E-8, 4.6E-6
Allowed range of input E1(2048 kbit/s) (0, -24 dB) (0, -24 dB)
signal level high-resistance connection (0, -6 dB)
2048 kHz (0, -6 dB)
terminal matching
Jitter generation 0.05U (24.4 ns) < 5 ns
Phase transient See Figure 6-9 or Figure 6- ST2E: see Figure 6-9.
10. ST3E: see Figure 6-10.
holdover-to-locking See Figure 6-11. See Figure 6-11.
Phase discontinuity MTIE (4s to 1000s) < 240 Switching external reference
ns source: no impact
MTIE (1 ms to 4 s) < 120 Reseating or switching
ns redundancy boards: < 15 ns
MTIE (< 1 ms) < 60 ns Reseating the MITU board: no
impact
Maintenance terminal Meets engineering Meets engineering maintenance
management and remote maintenance requirements. requirements.
TL1 language
Input wander tolerance G.812 Complies with G.812.
Static phase difference < 15 ns < 5 ns
between output signals
Alarm capability Meets engineering Meets engineering requirements.
requirements.
Performance monitoring Meets engineering N/A
accuracy requirements.

Copyright © Huawei
Figure 1.2 ITU-T requirement and SYNLOCK vendor requirement for wander generation MTIE
of PRC/LPR
Figure 1.3 ITU-T requirement and SYNLOCK vendor requirement for wander generation TDEV
of PRC/LPR

Copyright © Huawei
of ST2E (TNC)
of ST2E (TNC)

Copyright © Huawei
Figure 1.6 ITU-T requirement and SYNLOCK vendor requirement for wander transfer TDEV of
ST2E (TNC)
of ST3E (LNC)

Copyright © Huawei
of ST3E (LNC)
Figure 1.9 ITU-T requirement and SYNLOCK vendor requirement for wander transfer TDEV of
ST3E (LNC)

Copyright © Huawei
Figure 1.10 ITU-T requirement and SYNLOCK vendor requirement for phase transient of ST2E
(TNC)
Figure 1.11 ITU-T requirement and SYNLOCK vendor requirement for phase transient of ST3E
(LNC)

Copyright © Huawei
Figure 1.12 Holdover-to-locking
Parameter description:
1. The time span (tx in Figure 6-11) in from the time (t1 in Figure 6-11) for the clock to
obtain the good reference to the time (t2 in Figure 6-11) for the clock to confirm the
reference validity (for example, no LOS, OOF, or AIS) meets the requirements specified
in Table 6-5.
Table 12.1 Qualification time (1)

Configuration PRC/LPR ST2E (TNC) ST3E (LNC)
tx N/A 10s ≤ tx ≤ 30s 10s ≤ tx ≤ 30s
2. The time span (tx in Figure 6-11) from the time (t1 in Figure 6-11) for the clock
reference to recover from frequency offset to the time (t2 in Figure 6-11) for the clock to
confirm the reference validity meets the requirements specified in Table 6-6.
Table 12.2 Qualification time (2)

tx N/A tx ≤ 10 minutes tx ≤ 100s
The maximum time (ty in Figure 6-11) for locking meets the requirements specified in
Table 6-7.

Copyright © Huawei
Table 12.3 Maximum time for locking

ty N/A 600s 300s
3. The maximum wander (tz in Figure 6-11) for obtaining locking meets the requirements
specified in Table 6-8.
Table 12.4 Maximum wander for obtaining locking

Configurati PRC/LPR ST2E (TNC) ST3E (LNC)
on
tz NA MTIE ≤ 1 μs MTIE ≤ 1 μs
Phase change rate ≤ 61 Phase change rate ≤ 61 ns/1 ms
ns/1 ms
6.1.3 Traditional Time Synchronization Performance Counters

This section describes the technical specifications of the primary time server and secondary
time server. In client/server mode, the time server on the server side functions as the primary
time server, and the time server on the client side functions as the secondary time server. In
the following description, the technical specifications are applicable to both primary time
server and secondary time server, unless otherwise specified.
1. DCLS output accuracy of the primary time server
The primary time server synchronizes its time with the GPS, and the offset of its DCLS
output compared with the UTC is equal to or less than ≤1 μs.
2. DCLS output accuracy of the secondary time server
The DCLS output accuracy of the secondary time server is related to the DCLS input
accuracy and quality. Compared with input, the output has an offset equal to or less than
≤ 3 μs. In the entire DCLS network (provincial), the output accuracy is between 100 μs
and 1000 μs.
3. NTP output time accuracy
Table 6-9 lists the NTP output time accuracy.
Table 12.5 NTP output time accuracy

Network Output Time Accuracy
LAN 1-30 ms
MAN 10-500 ms
WAN (Internet) 100-1000 ms
4. NTP server load capacity

Table 6-10 lists the load capacity of the NTP server.

Copyright © Huawei
Table 12.6 Load capacity

Parameter Quantity
Maximum number of access and monitoring 400 x 20 (20 TODI boards, each supporting
clients supported by each server a maximum of 400 clients)
5. Resolution of delay compensation

The resolution of delay compensation is 50 ns.
6.1.4 FE/GE 1588 Performance Counters

Table 6-11 lists the FE/GE 1588 performance counters.
Table 12.7 FE/GE 1588 performance counters

Time synchronization accuracy When the GPS is locked, the absolute time
accuracy of the PTP port is within ±150 ns.
When the 1 PPS is locked, the relative time
accuracy of the PTP port is within ±150 ns.
6.1.5 1 PPS+TOD Performance Counters

Table 6-12 lists the 1 PPS+TOD performance counters.
Table 12.8 1 PPS+TOD performance counters

Time synchronization accuracy ±150 ns

Rising time of the rising edge ≤ 50 ns
PPS pulse width 20-200 ms
6.1.6 Port Specifications

Table 6-13 lists the specifications of input ports.
Table 12.9 Specifications of input ports

Para Satellite Terrestrial Reference Source and Terrestrial Measured
mete Reference Source
r Source
Port 1-2 4-84

quant

Copyright © Huawei
Para Satellite Terrestrial Reference Source and Terrestrial Measured

mete Reference Source
r Source
ity
Signa GPS, 64 kbit/s T1 (1544 1544 kHz E1 (2048 2048 10240
l type GLONASS, CC kbit/s) kbit/s) kHz kHz/51
or BeiDou 20
kHz/10
24 kHz
Redu Channel Separate use of adjacent slots or mutual backup of adjacent slots
ndan backup
cy
back
up
Port Satellite 110 ohms 75 ohms
type antenna
Signa  GPS L1: ITU-T ITU-T - ITU-T ITU- ≤ 3.0
l 1.5 GHz G.703 G.703 G.703 T Vpp
stand  GLONAS G.70
ard S L1: 1.6 3
GHz
 BeiDou:
2.6 GHz
Meas N/A ≤ –24dB ≤ –24dB ≤ –6dB ≤ –24dB ≤ -6 ≤ -6 dB
urem dB
ent
thres
hold
Onlin Real-time monitoring of all input ports
e
moni
torin
g
Table 6-14 lists the specifications of output ports.
Table 12.10 Specifications of output ports

Par TSOU Board
am
ete
r
Por 20 per board; 100 in full configuration of a subrack

t
qua
ntit

Copyright © Huawei
Par TSOU Board

am
ete
r
y
Red Mutual backup of adjacent slots (1:1 or 1+1)
und
anc
y
bac
kup
Sig 64 kbit/s T1 (1544 1544 kHz E1 (2048 2048 kHz 10240 kHz/5120
nal CC kbit/s) kbit/s) kHz/1MHz
typ
e
Por 110 ohms 75 ohms
t
typ
e
Sig ITU-T ITU-T - ITU-T ITU-T -
nal G.703 G.703 G.703 G.703
typ
e
6.1.7 MTBF
Table 6-15 lists the MTBF of different boards.
Table 12.11 MTBF

Board MTBF (Year)
LCIM > 20
SRCU/SOCU > 20
PNSU > 20
TODU > 20
TSOU > 20
TODI > 20
MITU > 20
TDRV > 20
Entire system > 20

Copyright © Huawei
6.1.8 EMC
The EMC performance of the SYNLOCK V3 passes the ETSI EN 300 386 (2000) test and
complies with the IEC 61000-4 (1993, 1994, 1995, 1996, and 2000) series, CISPR22 (1997),
ETS EN 300 386, EN55024 (1998), and EN55022 (1998). It also passes the CE certificate.
6.2 Standards Compliance

This section lists the standards that the SYNLOCK V3 complies with.
6.2.1 China Standards

Technical Specifications and Test Methods of Independent Node Clock Equipment in the
Digital Synchronization Network YDT 1011-1999
Digital Synchronization Network Node Clocks and Their Timing Features YDT 1012-1999
Digital Synchronization Network Planning Methods and Organization Principle YDN 117-
1999
6.2.2 ITU-T Recommendations

ITU-T (International Telecommunication Union)
G.803 (06/97) Architecture of transport networks based on the SDH
G.810 (08/96) Definitions and terminology for synchronization networks
G.811 (09/97) Timing characteristics of primary reference clocks
G.812 (06/98) Timing requirements at the outputs of slave clocks suitable for plesiochronous
operation of international digital links
G.822 (11/88) Controlled slip rate objectives on an international digital connection
G.823 (02/00) The control of jitter and wander within digital networks which are based on the
2048 kbit/s hierarchy
1544 kbit/s hierarchy
SDH
G.8261 (2010) Timing and synchronization aspects in packet networks
G.8262 (2010) Timing Characteristics of Synchronous Ethernet Equipment Slave Clock
(EEC)
G.8265.1 (2010)Precision time protocol telecom profile for frequency synchronization
6.2.3 IEEE Recommendations

IEEE 1588V2 a Precision Clock Synchronization Protocol for Networked Measurement and
Control Systems

Copyright © Huawei
6.2.4 ETSI Recommendations

ETS 300 462-1 (DE/TM-3017-1) Part 1: Definitions of terminology
ETS 300 462-2 (DE/TM-3017-2) Part 2: Synchronization Network Architecture, 1995
ETS 300 462-3 (DE/TM-3017-3) Part 3: The Control of Jitter and Wander within
Synchronization Networks
ETS 300 462-4 (DE/TM-3017-4) Part 4: Timing Characteristics of Slave Clocks suitable for
synchronization supply to SDH and PDH equipment
ETS 300 462-5 (DE/TM-3017-5) Part 5: Timing Characteristics of Slave Clocks suitable for
operation in SDH equipment, 1995
ETS 300 462-6 (DE/TM-3017-6) Part 6: Timing Characteristics of Primary Reference Clocks
6.2.5 RFC Recommendations

RFC1305, Network Time Protocol (Version 3) Specification, Implementation and Analysis
RFC2030, Simple Network Time Protocol (SNTP) Version 4

Copyright © Huawei
SYNLOCK V3 BITS(SSU,SASE) Acronyms and AbbreviationsAcronyms and
Product Description Abbreviations
7 Acronyms and Abbreviations
A
ACR adaptive clock recovery
AP access preamble
B
BITS building integrated timing supply
BTS base transceiver station
C
CPU central processing unit
D
DCLS DC level shift
DCN data communication network
DDS direct digital synthesizer
G
GPS global positioning system
I
IP Internet Protocol

Copyright © Huawei
L
LNC Local Node Clock
LPR Local Primary Reference
M
MSC mobile switching center
MTBF mean time between failure
N
NTP Network Time Protocol
P
PDF power distribution frame
PDH plesiochronous digital hierarchy
PPS pulse per second
PSBU packet synchronization backplane unit
PSIU packet synchronization interface unit
PSOU packet synchronization ocxo clock unit
PSRU packet synchronization rubidium clock unit
PTP precision time protocol
R
RNC radio network controller
RTC real time clock
S
SDH synchronous digital hierarchy
T
TD-SCDMA time division-synchronous code division multiple access
TL1 transaction language 1
TNC transit node clock

Copyright © Huawei
TOP timing over packet

TTL transistor-transistor logic
U
UDP User Datagram Protocol
UTC coordinated universal time
W
WCDMA wideband code division multiple access

Copyright © Huawei

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Trademarks and Permissions

Huawei Technologies Co., Ltd.

Huawei Proprietary and Confidential

About This Document

iManager U2000 V100R006C02SPC300+CP3203,

Issue 01 (2014-06-30) Huawei Proprietary and Confidential ii

Indicates an imminently hazardous situation which, if not

Indicates a potentially hazardous situation which, if not

Indicates a potentially hazardous situation which, if not

Indicates a potentially hazardous situation which, if not

Updates in V300R003C10 01 (2014-06-30)

Issue 01 (2014-06-30) Huawei Proprietary and Confidential iii

Issue 01 (2014-06-30) Huawei Proprietary and Confidential iv

About This Document....................................................................................................................ii

Issue 01 (2014-06-30) Huawei Proprietary and Confidential v

3.4.2 Complete Functions and Flexible Use.......................................................................................................................19

4 Product Configuration and Application.................................................................................22

6 Technical Specifications and Standards Compliance..........................................................41

Issue 01 (2014-06-30) Huawei Proprietary and Confidential vi

6.2.5 RFC Recommendations.............................................................................................................................................56

7 Acronyms and Abbreviations...................................................................................................57

Issue 01 (2014-06-30) Huawei Proprietary and Confidential vii

1 Product Positioning and Characteristics

About This Chapter

1.1 Product Positioning

1.2 Product Characteristics

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 1

1.2.1 Compact Structure

1.2.2 Flexible Configuration

1.2.3 Complete Functions

1.2.4 Superior Performance

1.2.5 High Stability and Reliability

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 2

 Redundancy of all timing channels and no single point failure

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 3

About This Chapter

2.1 Hardware Architecture

2.1.1 Appearance and Structure

Figure 1.1 Appearance of the SYNLOCK V3

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 4

Table 1.1 Slots for the boards of the SYNLOCK V3

Table 1.2 Boards of the SYNLOCK V3

MITU Maintenance interface and TOD unit

2.1.2 Working Principle

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 5

Figure 1.2 Architecture of the SYNLOCK V3 system

2.1.3 Power Distribution Principle

2.1.4 Ventilation Principle

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 6

Figure 1.3 Ground point of the subrack

 (1): Positions for securing and grounding the device.

2.2 Software Architecture

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 7

Figure 1.4 Software architecture of the SYNLOCK V3 system

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 8

About This Chapter

3.1 Frequency Synchronization

Table 4.1 Clock strata

Stratum-1 primary 1479–2006 G.811 ETS 300 462-6

Issue 01 (2014-06-30) Huawei Proprietary and Confidential 9

Table 4.2 Signal ports

2048 kbit/s, SMB TSOU board: Output: 400 -