VALLIAMMAI ENGINEERING COLLEGE

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND INSTRUMENTATION ENGINEERING
QUESTION BANK

VII SEMESTER
EC6601-VLSI DESIGN
Regulation – 2013
Academic Year 2018– 2019

Prepared by
Mr.K.R.Ganesh, Assistant Professor(O.G)/EIE
Ms. S.Vanila , Assistant Professor(Sr.G)/EIE
 UNIT I - MOS TRANSISTOR PRINCIPLE
NMOS and PMOS transistors, Process parameters for MOS and CMOS, Electrical properties of
CMOS circuits and device modeling, Scaling principles and fundamental limits, CMOS inverter
scaling, propagation delays, Stick diagram, Layout diagrams
PART – A
S.N
Questions BT Level Competence
o
1 List out lambda based design rules used for layout. BTL- 1 Remember
2 Define body bias effect. BTL- 1 Remember
3 What is Velocity saturation effect? BTL- 1 Remember
4 What is the need for demarcation line? BTL- 1 Remember
5 State channel length modulation. Write down the equation BTL- 1 Remember
for describing the channel length modulation effect in NMOS
transistors.
6 State the 3 modes involved in the operation of an BTL- 1 Remember
enhancement transistor.
7 Express about propagation delay of a CMOS inverter. BTL- 2 Understand
8 Differentiate enhancement and depletion mode devices. BTL- 2 Understand
9 Give the types of scaling in CMOS technology. BTL- 2 Understand
10 Compare the effect of scaling on MOSFET device BTL- 2 Understand
parameters.
11 Define noise margin. Illustrate how it can be obtained from BTL- 3 Apply
the transfer characteristics of a CMOS Inverter.
12 What is latch up? How to prevent Latchup? BTL- 3 Apply
13 Draw the DC transfer characteristics of CMOS inverter. BTL- 3 Apply
14 Point out the types of oxidation. BTL- 4 Analyze
15 Why nMOS transistor is selected as pull down transistor? BTL- 4 Analyze
16 Mention the non-ideal IV effects of MOS transistor. BTL- 4 Analyze
17 Predict the factors influencing the drain current. BTL- 5 Evaluate
18 Compare CMOS and Bipolar technologies. BTL- 5 Evaluate
19 Develop a stick diagram and layout for CMOS inverter. BTL- 6 Create
20 If the nominal threshold voltage of NMOS transistor in an BTL- 6 Create
180nm process is 0.4V and doping level is 8x1017 cm-3.
What is the body voltage?
PART B
1 (i) Describe the equation for source to drain current
in the three regions of operation of a MOS (7) BTL-1 Remember
transistor and draw the VI characteristics.
(ii) Describe in detail about body effect and its
effect in MOS device. (6) BTL-1 Remember

2 (i) Examine about the Non ideal I-V characteristics of

transistor. (7)
BTL-1 Remember
(ii) Describe the important properties used for the
estimation of resistance in MOS resistance (6)
model.
3 Describe the following concepts: (6)
BTL-1 Remember
(i) Device model and device characterization
 (ii) SPICE based circuit simulation (7)
4 Explain the dynamic behaviour of MOSFET transistor
with neat diagram. (13) BTL-1 Remember
5 Write the layout design rules and draw the diagram
(13) BTL-2 Understand
for four input NAND and NOR gate.
6 Discuss about the following MOS capacitance model:
(3)
(i) Simple MOS capacitance model.
(3)
(ii) Detailed MOS gate capacitance model. BTL-2 Understand
(3)
(iii) MOS device capacitance.
(4)
(iv) Detailed MOS diffusion capacitance model.
7 (i) Explain the electrical properties of CMOS. (7)
BTL-2 Understand
(ii) Discuss the scaling principles and its limits. (6)
8 (i) Explain the characteristics of CMOS inverter
with its transfer characteristics. (7)
BTL-3 Apply
(ii) Construct the layout for 2 input NAND and
AND gates using CMOS inverters. (6)
9 Draw the circuit layout and stick diagram for (7)
(i) Two input XOR gate BTL-3 Apply
(ii) CMOS inverter (6)
10 Explain the operation of following MOS transistor: (6)
(i) NMOS enhancement. BTL-4 Analyze
(ii) PMOS enhancement. (7)
11 (i) Explain the different steps involved in n-well CMOS
(7)
fabrication process with neat diagrams. BTL-4 Analyze
(ii) Derive the noise margins for a CMOS inverter. (6)
12 Explain in detail about second order effects of MOS
transistor. (13) BTL-4 Analyze
13 (i) What is meant by Junction leakage and Evaluate the
effect of junction leakage (7)
BTL-5
Evaluate
(ii) Evaluate the effects of Process variations in VLSI
design. (6)
14 Realize the function Y = (A + B + C)D using CMOS
compound gate. Draw the stick diagram and layout (13) BTL-6 Create
diagram.
PART-C
Consider an NMOS having electron mobility of µn
=540cm2/V–Sec. Calculate the process
(i) transconductance for the gate oxide thickness of 12
(7) BTL-5 Evaluate
nm and 8 nm.
An nMOS transistor has the following
parameters: gate oxide thickness= 10nm, relative
1 permittivity of gate oxide=3.9, electron
mobility= 520 cm2/V-sec, threshold voltage= 0.7
(ii) V, permittivity of free space= 8.85 x 10-14 F/cm (8) BTL-5 Evaluate
and (W/L)=8. Calculate the drain current when
(VGS = 2V and VDS =1.2 V) and also compute
the gate oxide capacitance per unit area. Note
that W and L refer to the width and length of the
 channel respectively.

Design a CMOS logic circuit for the given expression

2 X=[(A+B).(C+D)]’ and draw its stick diagram. (15) BTL-6 Create
Consider an nMOS transistor in a 0.6 micrometer
process with W/L =4/2 λ (i.e., 1.2/0.6 micrometer). In
this process, the gate oxide thickness is 100 A and the
3 (15) BTL-5 Evaluate
mobility of electrons is 350 cm2/V· s. The threshold
voltage is 0.7 V. Plot Ids vs. Vds for Vgs =0, 1, 2, 3,
4,and 5 V.
4 Design a CMOS logic circuit for the given expression
Y=[(ABC)+(CD)]’ and draw its stick diagram. (15) BTL-6 Create
UNIT II - COMBINATIONAL LOGIC CIRCUITS
Examples of Combinational Logic Design, Elmore’s constant, Pass transistor Logic, Transmission gates,
static and dynamic CMOS design, Power dissipation – Low power design principles
PART - A
BT
S.No Questions Competence
Level
1. What is a transmission gate? BTL- 1 Remember
2. List the advantages of pass transistor. BTL- 1 Remember
3. Define Transistor Sizing problem. BTL- 1 Remember
4. What are the advantages of using pseudo-nMOS gate instead BTL- 1 Remember
of full CMOS gate?
5. State the types of power dissipation. BTL- 1 Remember
6. What are critical paths? BTL- 1 Remember
7. Define Elmore’s constant and Give Elmore delay expression BTL- 2 Understand
for propagation delay of an inverter.
8. Why is the transmission of logic 1 degraded as it passes BTL- 2 Understand
through a NMOS pass transistor?
9. Write the expressions for the logical effort and parasitic BTL- 2 Understand
delay of n input NOR gate.
10. Estimate how dynamic power can be reduced. BTL- 2 Understand
11. Sketch the structure of 2:1 CMOS MUX using pass BTL- 3 Apply
transistor.
12. Draw the symbol of transmission gate. Mention the BTL- 3 Apply
disadvantages of CMOS transmission gate.
13. Mention the drawbacks of dynamic logic. BTL- 3 Apply
14. Prioritize the criteria needed for low power logic design. BTL- 4 Analyze
15. Point out the factors that produce dynamic power dissipation. BTL- 4 Analyze
16. Analyze about the factors that cause static power dissipation BTL- 4 Analyze
in CMOS circuits.
17. Why single phase dynamic logic structure cannot be BTL- 5 Evaluate
cascaded? Justify.
18. Realize OR and NOR logic function using differential BTL- 5 Evaluate
cascade voltage switch logic.
19. Implement a 2:1 Multiplexer using pass transistor. BTL- 6 Create
20. Develop a 2-input XOR gate using transmission gates. BTL- 6 Create
PART-B
1. What are the sources of power dissipation in CMOS? and
discuss various design techniques to reduce power (13) BTL-1 Remember
dissipation in CMOS.
2. i) Describe the properties and operation of dynamic
CMOS logic with neat diagram. (7) BTL-1 Remember

ii) List the various application of dynamic CMOS logic. (6) BTL-1 Remember
3. i) Explain the static and dynamic power dissipation in
CMOS circuits with necessary diagrams and (7)
expressions. BTL-1 Remember
ii) Derive an nMOS inverter pair delay whose transistor
size is 4:1. (6)
4. Describe the following concepts:
(i) RC delay models. (3)
(i) Elmore delay model. (3) BTL-1 Remember
(ii) Linear delay model. (3)
(iv) Logical effort delay model. (4)
5. i) Compare static and dynamic logic circuit with
example. (7) BTL-2 Understand

ii) Discuss on skew tolerant domino circuits. (6) BTL-2 Understand

6. i) Discuss about the principles of Low power logic
design in CMOS circuits. (7)
BTL-2
Understand
ii) Realize the operation of ratioed circuits with neat
diagram. (6)
7. i) Discuss in detail about the characteristics of CMOS BTL-2
transmission gate. (7) Understand

ii) Express about delay estimation, logical effort and

transistor sizing with example. (6) BTL-3 Apply

8. Draw and explain about realization of inverters and basic

gates using pass transistor logic. (13) BTL-3 Apply

9. With neat sketch, illustrate the operation of pass transistor

DC characteristics. (13) BTL-3 Apply

10. Briefly discuss the signal integrity issues in dynamic

design. (13) BTL-4 Analyze

11. i) Explain the operation, important properties, (7)

advantages and limitations of static CMOS design.
BTL-4 Analyze
ii) Explain about the problem of charge sharing and the (6)
methods to overcome it.
12. i) Explain the domino logic with neat diagram. (7)
ii) Discuss about multiple output and zipper domino BTL-4 Analyze
(6)
logic
13. i) Draw the CMOS logic circuit for the Boolean (8)
expression Z=[A(B+C)+DE]’ and Explain
BTL- 5 Evaluate
ii) Explain the basic principle of transmission gate in
CMOS design (5)
14. (i) Design a D-latch using transmission gate. (7)
(ii) Design a 1-bit dynamic inverting and non-inverting BTL- 6 Create
register using pass transistor. (6)
 PART-C

1. (i) Design a CMOS logic circuit for the given

expression X=[(A+B).(C+D)]’ and draw its stick BTL-6 Create
(8)
diagram.
(ii)

BTL-5 Evaluate
(7)
Obtain the logical effort and path efforts of the given
circuit.
2. Design a four input NAND gate and obtain its delay
during the transition from high to Low. BTL-6 Create
(15)
3. Sketch a transistor-level schematic for a compound
CMOS logic gate for each of the following functions:
a) Y =(ABC +D)’
(5) BTL-6 Create
b) Y =(AB +C) · D)’
(5)
c) Y =AB +C · (A +B))’
(5)
4. An NMOS transistor is used to charge a large capacitor,
as shown in Figure
a. Determine the tpLH of this circuit, assuming an ideal
step from 0 to 2.5V at the input node.
b. Assume that a resistor RS of 5 kohm is used to
discharge the capacitance to ground. Determine L. tpHL.
c. Determine how much energy is taken from the supply
during the charging of the capacitor. How much of this is
dissipated in M1. How much is dissipated in the pull-
down resistance during discharge? How does this change
when RS is reduced to 1 kohm. (15) BTL-5 Evaluate

UNIT III- SEQUENTIAL LOGIC CIRCUITS

Static and Dynamic Latches and Registers, Timing issues, pipelines, clock strategies, Memory
architecture and memory control circuits, Low power memory circuits, Synchronous and
Asynchronous design
PART – A
1. What are the timing parameters for electronic memories? BTL-1 Remember
2. List the timing metrics for sequential circuits. BTL-1 Remember
3. Tabulate the classification of semiconductor memory. BTL-1 Remember
4. Define clock jitter and Clock skew. BTL-1 Remember
5. What is clocked CMOS register? BTL-1 Remember
6. What are synchronizers? Enumerate its features. BTL-1 Remember
7. What is NORA CMOS? BTL-2 Understand
8. Is D-flip-flop applicable for counter applications? Why? BTL-2 Understand
9. Express time borrowing concepts in transparent latches. BTL-2 Understand
10. Compare Registers and Latches. BTL-2 Understand
11. Draw the Voltage Transfer Characteristics of two cascaded BTL 3 Apply
inverters.
12. Mention the advantages of using a block address in memory BTL-3 Apply
design.
13. Draw the block diagram of a Finite State Machine. BTL-3 Apply
14. Classify digital systems based on timing characteristics. BTL-4 Analyze
15. Point out the advantages of two phase clocking scheme. BTL-4 Analyze
16. Point out the concepts of pipelining. BTL-4 Analyze
17. Obtain the functional composition of a PLL. BTL-5 Evaluate

18. Compare and contrast synchronous design and asynchronous BTL-5 Evaluate
design.
19. Develop a switch level schematic of multiplexer based NMOS BTL-6 Create
latch using NMOS only pass transistors.
20. Generalize the peculiarity of a CAM. BTL-6 Create
PART B
1. (i) Describe the architecture of an N-word memory. (7)
(ii) Describe the operation of various memory BTL-1
Remember
peripheral circuitries. (6)
2. (i) Describe the Bi-stability principle associated with
static latches and registers. (7)
(ii) Examine the differences between Static and Dynamic BTL-1 Remember
Memory. (6)
3. (i) What are the different approaches to reduce power
dissipation in memories? (7)
(ii) What are the challenges involved in an asynchronous (6) BTL-1 Remember
design? Can these challenges be overcome using a
self-timed logic?
4. (i) What is the drawback of transmission gate register? (7)
And What is the approach to overcome it?
(ii) Describe the operation of a Dynamic Transmission (6) BTL-1 Remember
Gate Edge Triggered Register
5. (i) Illustrate the impact of clock skew and jitter on the (7)
performance of a sequential system
Understand
(ii) Discuss about the basic concept of clock synthesis and (6) BTL-2
synchronization using Phase –Locked loop.
6. (i) Distinguish various clocking strategies used in chip (7)
design.
BTL-2 Understand
(ii) How can one design a register that is insensitive to (6)
clock-skew?
7. (i) Summarize the concept and implementation of (7)
synchronizers and arbiters.
BTL-2 Understand
(ii) How can we build latches using multiplexers? Discuss (6)
their operation in detail.
8. Discuss about CMOS register concept and design master- (13) BTL-2 Understand
 slave triggered register, Explain its operation with
overlapping periods.
9. (i) Draw and explain the operation of conventional,
pulsed and resettable latches. (7)
(ii) Explain the operation of True single phase clocked BTL-3 Apply
register with a neat diagram. (6)

10. Explain in detail about various static latches and registers. (13) BTL-4 Analyze
11. Explain in detail various pipelining approaches to optimize
sequential circuits.
(13) BTL-4 Analyze

12. Discuss about the design of sequential dynamic circuits and

its pipelining concept.
(13) BTL-4 Analyze

13. Explain the timing basics and clock distribution techniques

in synchronous design in detail
(13) BTL-5 Evaluate
14. Explain the memory architecture and its control circuits in
detail. (13) BTL-6 Create

PART-C
1. (i) Prove the equation:

(8) BTL-5 Evaluate

(ii) Determine the maximum logic propagation delay

available in a cycle for a traditional domino
(7) BTL-5 Evaluate
pipeline using a 500 ps clock cycle. Assume there
is zero clock skew.
2. Design a clock distribution network based on H tree
model for 16 nodes. (15) BTL-6 Create
3. For each of the following sequencing styles, determine
the maximum logic propagation delay available within
a 500 ps clock cycle. Assume there is zero clock skew
and no time borrowing takes place. (15) BTL-5 Evaluate
(i) Flip-flops
(ii) Two-phase transparent latches
(iii)Pulsed latches with 80 ps pulse width
4. Evaluate the design principles to for reducing of clock
skew and jitter. (15) BTL-5 Evaluate
UNIT IV- DESIGNING ARITHMETIC BUILDING BLOCKS
Data path circuits, Architectures for ripple carry adders, carry look ahead adders, High speed
adders, accumulators, Multipliers, dividers, Barrel shifters, and speed and area trade off
PART - A
S.N
Questions BT Level Competence
o
1. What is meant by bit-sliced data path organization? BTL-1 Remember
2. List out the components of data path. BTL-1 Remember
3. What is latency? BTL-1 Remember
4. Define Vector merging adder. BTL-1 Remember
5. Mention the principle of any one fast multiplier. BTL-1 Remember
6. List the uses of Clock gating. BTL-1 Remember
7. Give a neat sketch on Manchester carry gates. BTL-2 Understand
8. Write the full adder output in terms of propagate and
BTL-2 Understand
generate.
9. Draw the structure of 4 X 4 barrel shifter. BTL-2 Understand
10. Give the applications of high speed adder. BTL-2 Understand
11. Draw the schematic for sleep transistors used on both
BTL-3 Apply
supply and ground.
12. Mention the draw backs of a static adder circuit. BTL-3 Apply
13. Calculate the propagation delay of n-bit carry select adder. BTL-3 Apply
14. Compare constant throughput and variable throughput in BTL-4 Analyze
active & leakage mode.
15. Compare dadda multiplier and booth multiplier. BTL-4 Analyze
16. Select the method which is adopted to reduce power in idle
BTL-4 Analyze
mode.
17. Obtain the power minimization techniques in design and Evaluate
BTL-5
sleep mode.
18. Check whether barrel shifter very useful in the designing of Evaluate
arithmetic blocks. BTL-5

19. Create a partial product selection table using modified

BTL-6
booth’s recoding. Create
20. How to design a high speed adder? BTL-6 Create
PART-B
1. (i) Describe ripple carry adder and derive the (7)
worst case delay with example. BTL-1 Remember
(ii) Describe the inversion property of full adder. (6)
2. Explain the operation of a basic 4-bit adder, also Describe
the different approaches of improving the speed of adder. (13) BTL-1 Remember

3. Describe the implementation of a Manchester Carry (13)

chain adder. BTL-1 Remember

4. List the logic design considerations of binary adder

and explain
BTL-1 Remember
(i) Carry skip adder (7)
(ii) Carry save adder (6)
5. (i) Explain the concept of carry look ahead adder with (7)
neat diagram. BTL-2 Understand
(ii) Discuss the details about speed and area trade off. (6)
6. (i) Describe the concept of monolithic and
logarithmic look ahead adder. (7)
BTL-2 Understand
(ii) Discuss the data paths in digital processor
(6)
architectures.
7. (i) Discuss how power can be reduced in the standby
mode in the design of arithmetic unit. (7)
BTL-2 Understand
(ii) Describe in detail about various Run-time power
(6)
management schemes.
8. (i) Demonstrate how to reduce the number of
generated partial products by half. (6)
BTL-3 Apply
(ii) Explain the methods to accumulate partial (7)
products in array form.
9. (i) What are the methods adopted to perform division
in a digital IC? Make a comparison between them. (7)
BTL-3 Apply
(ii) Describe the design approach adopted in a
(6)
logarithmic shifter.
10. Classify circuit design considerations of full adder
and explain
BTL-4 Analyze
(i) Mirror adder (7)
(ii) Transmission gate adder (6)
11. Explain the concept of modified Booth multiplier with a
suitable example.
(13) BTL-4 Analyze

12. Design a 16 bit carry bypass and carry select adder

(13) BTL-4 Analyze
and discuss their features.
13. Explain the operation of Booth multiplication with
suitable examples, And Justify how Booth algorithm (13) BTL-5 Evaluate
speeds up the multiplication process.
14. Design a magnitude comparator To compare two
unsigned numbers A and B of four bit wide. (13) BTL-6 Create

PART-C
1. (i) When adding two unsigned numbers, a carry-
out of the final stage indicates an overflow.
When adding two signed numbers in two’s
complement format, overflow detection is
(8) BTL-6 Create
slightly more complex. Develop a Boolean
equation for overflow as a function of the most
significant bits of the two inputs and the
output.
(ii) Show how the layout of the parity generator of
given Figure can be designed as a linear
column of XOR gates with a tree-routing
channel.

(7) BTL-5 Evaluate

2. Design a ripple carry adder to add four unsigned

numbers A,B,C and D of eight bit wide. (15) BTL-6 Create
3. Evaluate the design of All ones and all zeros on
wide N-bit words (15) BTL-5 Evaluate
4. Present a case study report on comparison of various
adder architectures. (15) BTL-5 Evaluate
UNIT V- IMPLEMENTATION STRATEGIES
Full custom and Semi-custom design, Standard cell design and cell libraries, FPGA building block
architectures, FPGA interconnect routing procedures.
PART - A
S.No Questions BT Level Competence

1. What is the standard cell based ASIC design? BTL-1 Remember

2. What is meant by CBIC? BTL-1 Remember
3. Name the elements in configuration logic block. BTL-1 Remember
4. What is an anti-fuse? State its merits and demerits. BTL-1 Remember
5. List out three main parts of FPGA & what is PMS? BTL-1 Remember
6. Define OEM. BTL-1 Remember
7. Distinguish between PAL and PLA. BTL-2 Understand
8. State the features of full custom design. BTL-2 Understand
9. What are feed through cells? State its uses. BTL-2 Understand
10. What is the role of cell libraries in ASIC design? BTL-2 Understand
11. Mention the objectives and goals of System Partitioning. BTL-3 Apply
12. Illustrate the advantages and disadvantages of FPGA compared
BTL-3 Apply
to ASIC.
13. Show the advantages and disadvantages of cell based design
BTL-3 Apply
methodology.
14. Differentiate between Altera MAX 9000 and Altera FLEX
BTL-4 Analyze
interconnects architecture.
15. Compare FPGA and CPLD. BTL-4 Analyze
16. Compare between fine-grain and coarse-grain architecture of
BTL-4 Analyze
FPGA.
17. Analyze What are the two different types of routing ? BTL-5 Evaluate
18. Evaluate the meaning and merits of ULSI. BTL-5 Evaluate
19. Integrate the concept of segmented Channel routing. BTL-6 Create
20. Design a primitive gate array cell. BTL-6 Create
PART B
1. Describe the following types of ASIC:
(i) Full custom ASIC (7) BTL-1 Remember
(ii) Semi-custom ASIC (6)
2. Describe briefly about Gate-Array based ASIC’s design with
(13) BTL-1 Remember
neat diagrams.
3. (i) Explain the Configurable Logic Block and IO block of (7)
Xilinx XC4000 FPGA. BTL-1 Remember
(ii) List the features of Xilinx XC4000 FPGA. (6)
4. Draw and Explain the building blocks of FPGA. (7) BTL-1 Remember
Discuss the different types of programming technology used
(6) BTL-2 Understand
in FPGA design.
5. With neat sketch explain the CLB, IOB and programmable
(13) BTL-2 Understand
interconnects of an FPGA device
6. Briefly explain the semi-custom ASIC with its classification. (13) BTL-2 Understand
7. Draw and Explain the building blocks of FPGA. (13) BTL-1 Remember
8. (i) Illustrate the concepts of Mask programmable arrays.
(7)
(ii) Identify the components involved in constructing a BTL-3 Apply
(6)
voltage output macro cell.
9. Define and explain briefly about different approaches of
(13) BTL-3 Apply
programmable wiring with neat diagrams.
10. Explain about different types of ASIC with neat diagram.
(13) BTL-4 Analyze
(13)
11. With design flow, explain the sequence of steps involved in
the ASIC design process. (13) BTL-4 Analyze
(13)
12. Explain the interconnect architectures of (7) BTL-5 Evaluate
 (i) Altera Max series (6)
(ii) Xilinx XC40XX series
13. (i) Compare and contrast about EPROM and EEPROM
(7) Evaluate
technology. BTL-5
(6)
(ii) Summarize about programming of PAL
14. (i) Design an LUT-Based Logic Cell. (7)
BTL-6 Create
(ii) Discuss the Classification of prewired arrays. (6)
PART-C
1. An FIR filter for a GSM receiver with sigma-delta
converter as shown in Figure (b) has a single-bit input.
To what structure do the multipliers degenerate? If the
coefficients are a single bit and a 288-tap filter has to
operate at 13 MHz, what architecture would you use for
the overall design? (15)

(15) BTL-5 Evaluate

2. What kind of RAM cell would you use to control a

configurable logic block in an FPGA? Design the cell and (15) BTL-6 Create
outline the reasons for your choice.
3. Explain the trade-offs between using a transmission gate
(15) BTL-5 Evaluate
or a tristate buffer to implement an FPGA routing block.
4. Analyze the pros and cons of various design strategies. (15) BTL-5 Evaluate