Group 3 COA Assignment Section - A

Group 3

COA Assignment :

Presented by :

14 2017HW86506 391475 Shadaan Ahmad

20 2017HW86663 391482 Samixa Santosh Kamat
12 2017HW86532 391473 Divyam Chauhan
7 2017HW86533 391468 Deepak Shukla

Write an assembly language program to add R01 and R02 .Compare the resultant
contents with R03 for the following 2 cases

i) R01=10,R02=20 ,R03 = 40

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Group 3 COA Assignment Section - A

ii) R01=10,R02=20 ,R03 = 20

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Group 3 COA Assignment Section - A

If resultant is greater than R03, then increment R09 else increment R10

a) Explain resultant intermediate General Purpose register values in the

register window after running above program.

Ans. I) R01=10,R02=20 ,R03 = 40

Initially all registers were set to zero.

Value 10 was moved in R01
Value 20 was moved in R02
Value 40 was moved in R03
R01 and R02 were added and the resultant was saved in R02 (second
operand).
Sum of R01 and R02 i.e. R02 was compared with R03.
As R03 was greater than R20 hence program control jumped to label L1.
R09 was incremented by 1 hence value of R09=1.
Program Halted

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Group 3 COA Assignment Section - A

2)R01=10,R02=20 ,R03 = 20

Initially all registers were set to zero.

Value 10 was moved in R01
Value 20 was moved in R02
Value 20 was moved in R03
R01 and R02 were added and the resultant was saved in R02 (second
operand).
Sum of R01 and R02 i.e. R02 was compared with R03.
As R03 was not greater than R20 hence program control didn’t jumped to
label L1.
R10 was incremented by 1 hence value of R10=1.
Program Halted

b) Execute this program 3 times .

Show the contents of instruction cache after end of every iteration in the
table below (total 3 iterations) Show and explain misses Vs cache size
chart (graph) for instruction cache for block size =4 and
cache size = 16 using direct mapping technique. Also explain the below
table for each instruction
I) R01=10,R02=20 ,R03 = 40
Total of 16 instructions can be loaded in the cache. As block size is 4
therefore total 4 instructions would be fetched in each time there is a miss
in the cache.

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Group 3 COA Assignment Section - A

Iteration 1
Address Instruction Hits Misses %Misses
0 MOV #10, R01 0 1 100
6 MOV #20, R02 1 0 50
12 MOV #20, R03 1 0 33.33333
18 ADD R01, R02 1 0 25
23 CMP R02, R03 0 1 40
28 JGT $L1 1 0 33.33333
32 INC R10 1 0 33.33333
35 HLT 1 0 33.33333
36 L1: 0 0 33.33333
36 INC R09 0 1 42.85714
39 HLT 1 0 37.5

When program is executed for the first time, it looks for the instructions in
memory cache. As the cache is empty, there is will be a miss. Hence, 4
instructions would be fetched from the memory to the cache. For next 3
instructions there would be a hit. Again, for the 4th instruction there will be a miss.
Therefore, next 4 instructions will be fetched with 1 miss and 3 hits. So, total 8
instructions will be fetched with 5 hits and 3 misses.

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Group 3 COA Assignment Section - A

Iteration 2
Address Instruction Hits Misses %Misses
0 MOV #10, R01 0 1 33.33333
6 MOV #20, R02 1 0 30
12 MOV #20, R03 1 0 27.27273
18 ADD R01, R02 1 0 25
23 CMP R02, R03 0 1 23.07692
28 JGT $L1 1 0 21.42857
32 INC R10 1 0 21.42857
35 HLT 1 0 21.42857
36 L1: 0 0 21.42857
36 INC R09 0 1 20
39 HLT 1 0 18.75

In second iteration all instructions will be in the Cache hence 0 misses and 8 hits
would be there.

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Group 3 COA Assignment Section - A

Iteration 3
Address Instruction Hits Misses %Misses
0 MOV #10, R01 0 1 6.666667
6 MOV #20, R02 1 0 6.25
12 MOV #20, R03 1 0 5.882353
18 ADD R01, R02 1 0 5.555556
23 CMP R02, R03 0 1 10
28 JGT $L1 1 0 9.52381
32 INC R10 1 0 100
35 HLT 1 0 100
36 L1: 0 0 100
36 INC R09 0 1 13.04348
39 HLT 1 0 12.5

Similarly iteration all instructions will be in the Cache hence 0 misses and 8 hits
would be there. But the total number of hits have increased and misses have
remain same hence hit miss ratio reduces every time we execute same program
again.

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Group 3 COA Assignment Section - A

c) Execute this program 3 times .

Show the contents of instruction cache after end of every iteration in the
table below (total 3 iterations) Show and explain misses Vs cache size
chart (graph) for instruction cache for block size =8 and
cache size = 32 using direct mapping technique. Also explain the below
table for each instruction

Ans.
II) R01=10,R02=20 ,R03 = 40
Total of 32 instruction can be loaded in the cache.As block size is 8
therefore total eight instruction would be fetched in each time there is a
miss in the cache.
Iteration 1
Address Instruction Hits Misses %Misses
0000 MOV #10, R01 0 1 18.18
0006 MOV #20, R02 1 0 16.67
0012 MOV #20, R03 1 0 15.38
0018 ADD R01, R02 1 0 14.29
0023 CMP R02, R03 1 0 13.33
0028 JGT $L1 1 0 12.50
0032 INC R10 1 0 11.76
0035 HLT 1 0 11.11
0036 L1: 0 0 11.11
0036 INC R09 0 1 10.53
0039 HLT 1 0 10.00

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Group 3 COA Assignment Section - A

When program is executed for the first time, it looks for the instructions in
memory cache. As the cache is empty, there is will be a miss. Hence, 8
instructions would be fetched from the memory to the cache. For next
7instructions there would be a hit. So, total 8 instructions will be fetched with 6
hits and 2 misses.

Iteration 2
Address Instruction Hits Misses %Misses
0000 MOV #10, R01 1 1 18.18
0006 MOV #20, R02 2 0 16.67
0012 MOV #20, R03 2 0 15.38
0018 ADD R01, R02 2 0 14.29
0023 CMP R02, R03 2 0 13.33
0028 JGT $L1 2 0 12.50
0032 INC R10 2 0 11.76
0035 HLT 2 0 11.11
0036 L1: 0 0 11.11
0036 INC R09 1 1 10.53
0039 HLT 2 0 10.00

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Group 3 COA Assignment Section - A
In second iteration all instructions will be in the Cache hence 0 misses and 8 hits
would be there.

Iteration 3
Address Instruction Hits Misses %Misses
0000 MOV #10, R01 2 1 9.52
0006 MOV #20, R02 3 0 9.09
0012 MOV #20, R03 3 0 8.70
0018 ADD R01, R02 3 0 8.33
0023 CMP R02, R03 3 0 8.00
0028 JGT $L1 3 0 7.69
0032 INC R10 3 0 7.41
0035 HLT 3 0 7.14
0036 L1: 0 0 7.14
0036 INC R09 2 1 6.90
0039 HLT 3 0 6.67

Similarly iteration all instructions will be in the Cache hence 0 misses and 8 hits
would be there. But the total number of hits have increased and misses have
remain same hence hit miss ratio reduces every time we execute same program
again.

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Group 3 COA Assignment Section - A

d)Show, explain and justify with pipelining and without pipelining stages w.r.t the
below table parameters

R01=10,R02=20 ,R03 = 20 W/o pipelining With pipelining

Clocks 40 17
CPI 5 2.12
SF 1 2.36
Instruction count 8 8
Validity of answer (Answer
correct or not)

When the program is executed without pipeline all the resource are used only by single
instruction hence would sit idle if that instruction has not finished its execution. So would take
longer to complete.

Using pipeline no resources will sit idle and hence would complete the program much faster.

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