ADVANCE : ANALOG ELECTRONICS - REPORTS

Q. 1

Consider the waveform shown below:

If the input is a 100 V peak square wave with a period of 20 ms. The output of the wave is so designed that it has a maximum
value of 25 and minimum of –175 V at the steady state, then the circuit which can perform this function can be represented
as

Solution :
(c)
 D

Q. 2

A diode circuit shown in the figure below consists of two diodes D1 and D2.

The diodes connected are assumed to be ideal diodes, then the transfer characteristic curve of the clipper circuit formed by
the two diodes can be represented as

Solution :
(b)
 C

Q. 3

Consider the circuit shown in the figure below:

Assuming the of the transistor to be very large, the value of the collector voltage VC is equal to

A 6.1

B 2.43 V

C –4.475 V

Solution :
(c)
 ( )

D –2.21 V

Q. 4

Consider an N-MOS transistor shown in the circuit below:

The N-MOS transistor is so constructed that it has   the threshold voltage and

then the value of voltage VDS is equal to

A 7.614 V

Solution :
(a)
 B 4.212 V

C 3.142 V

D 8.624 V

Q. 5

Consider the BJT circuit shown in the figure below:

The transistor is biased in such a way that the transconductance of the transistor gm = 10 mS. If the early voltage
then the value of input resistance Rin (seen by source Vin) is equal to
(Assuming coupling capacitance to be very large).

A 3.62 kΩ

B 4.62 kΩ

C 5.62 kΩ

Solution :
(c)
 D 6.62 kΩ

Q. 6

For a n-channel MOSFET biased in the saturation region, the parameter and

If the value of the drain current flowing inside the MOS transistor is ID = 0.75 mA, then the value of intrinsic gain
of the MOSFET is equal to

A 201.21

B 115.46

C 143.34

D 163.3

Solution :
(d)
Q. 7

At IC = 1 mA and VCE = 10 V, the high frequency parameters at cutoff frequency MHz was measured at
Then the value of capacitance will be equal to

A 1.6 pF

B 2.1 pF

C 2.7 pF

Solution :
(c)

D 3.4 pF

Q. 8

An ideal op-amp circuit with saturation voltage is used to construct the circuit shown in the figure below.

The output of the op-amp is lead into a differentiator circuit with the value of RC << T. The differentiator is followed by an
ideal diode and a lead resistor RL. If the input to the op-amp is a sinusoidal wave with period T, then the output of the circuit
at steady state can be approximately represented as

A
B

Solution :
(c)

D
Q. 9

Consider the circuit shown in the figure below:

A current controlled current source is formed by using of an ideal op-amp circuit. If the output current Io of the circuit which is

measured across the load resistance RL is related to the input as then the value of k is equal to

Solution :
(c)
 D

Q. 10

To idealise a voltage amplifier the type of feedback topology used is

A Voltage series

Solution :
(a)
For an ideal voltage amplifier the input impedance must be very high and output impedance should be low, so we use
series-shunt or voltage series topology.

B Voltage shunt

C Current series

D Current shunt

Q. 11

Consider the circuit shown in the figure below:

Let the forward voltage drop V for the diode. The circuit is connected with two power supplies with values V1 = 10 V
and V2 = 15 V, then the value of current passing through the diode D is equal ______ mA.

0.127 (0.10 - 0.20)

Solution :
0.127 (0.10 - 0.20)
Q. 12

Consider the n-p-n transistor shown in the figure below:

The value of base to emitter voltage when the transistor is working in active region is equal to VBE = 0.7 V. If the of the
transistor is equal to 120, then the value of collector to emitter voltage VCE will be equal to __________ V.

2.547 (2.20 - 2.80)

Solution :
2.547 (2.20 - 2.80)
Q. 13

Consider the instrumentational amplifier circuit shown in the figure below:

The circuit is perfectly matched to given the common-mode voltage gain Acm = 0. The value of output voltage gain for a
differential input voltage i.e. V2 – V1 = Vid = 20 mV is equal to __________ mV.

220

Solution :
220
Q. 14

Consider an inverting amplifier with a normal gain of 1000 constructed from an op-amp with an input offset voltage of 3 mV
and with output saturation level of ±10 V. The value of the peak sine wave that can be applied without any clipping at the
output is equal to _______ mV.

Solution :
7

Q. 15

An amplifier with open loop gain of A = 2000 ±150 is available for operation but for a particular operation it is necessary to
have the amplifier whose voltage gain varies by not more than 0.2%. The close loop feedback gain of the circuit is equal to
____________.

53.33 (53.00 - 53.60)

Solution :
53.33 (53.00 - 53.60)

Q. 16

Consider the figure shown below. If the saturation voltage of the op-amp output is same as the supply voltage, then the width
of the hysteresis loop of the circuit (i e UTP - LTP) will be V
of the hysteresis loop of the circuit (i.e. UTP LTP) will be ___________ V.
(assume op-amp is ideal)

12

Solution :
12

Q. 17

Consider the circuit shown in the figure below:

The diode D1 in the figure shown below can be replaced by a 0.7 V battery when it is forward biased by a voltage greater than
or equal to 0.7 V. If the current source a ramp function i.e. then the output can be represented as

B
 B

Solution :
(d)

Q. 18

Consider the MOS transistor circuit as shown in the figure below:

The two transistors have   but different values of width to length ratio. The
input to the transistor M2 of 5 V creates an output voltage to V0  = 0.1 V. If the value of then the value of is

equal to

A 34.306

B 42.301

C 17.413

D 20.253

Solution :
(d)

Q. 19

Consider the circuit shown in the figure below:

The biasing circuit is omitted which ensures that the circuit operates in active region. Neglecting the early effect the value of

voltage gain i.e. is equal to

Solution :
(c)

D
Q. 20

Consider the circuit shown in the figure below. The biasing arrangement which ensures that both the transistors will work in
active region has been omitted. The two parallel connected transistors are completely identical i.e.
The base of the two transistors are fused as shown in the figure,
then the value of small signal input resistance as seen by the base of the two transistors is equal to

Solution :
(b)
 C

Q. 21

Consider the N-MOS transistor as shown in figure below. The MOSFET has parameters

The transistor is used to amplify the small signal vin  as shown in the figure. If the value of signal
then the value of output signal is equal to

Solution :
(d)
Q. 22

Consider the circuit shown in the figure below:

The D.C. biasing of the circuit is such that the circuit is always in saturation region for all values of small signal input source
. The frequency of the input source is such that all the coupling capacitors acts as short circuit. If the value of the output

resistance RL and the drain resistance (RD) is equal, then the value of current gain is equal to

A 4

B 2
 C 0.5

D 0.25

Solution :
(d)

Q. 23

Consider the difference amplifier as shown in the figure below. Assuming the op-amp to be ideal the CMRR of the circuit is
equal to

A 35.1 dB

B 41.6 dB
 B 41.6 dB

Solution :
(b)

C 74.4 dB

D 89.2 dB

Q. 24

Consider the MOS amplifier shown in the figure below:

Th i i bi di h h h MOS i bi di h i i d h l f h i
The transistor is biased in such a way that the MOS is biased in the saturation region and the value of the processing

parameter If a small signal voltage is applied to the circuit, then

the value of output voltage is equal to

A –10 mV

B –20 mV

C 10 mV

Solution :
(c)

D 20 mV

Q. 25

Consider the non-inverting amplifier shown in the figure below:

The open-loop gain of the amplifier is equal to AOL = 103, assuming the finite open loop gain to be the only non-idealy present
in the op-amp the value of close loop gain of the amplifier is

A 101

B 98.9

C 91.73

Solution :
(c)

D 84.63
Q. 26

Consider the voltage series regulator circuit shown in the figure below. It is assumed that the transistors are biased in active
region with the voltage drop across the base-emitter terminal as VBE = 0.7 V. The current gain of the transistor If the
zener diode is working in the breakdown region with VZ = 8.3 V and the current through zener diode is negligible, then the
output voltage is

A 15.7 V

Solution :
(b)

C 14.7 V

D 14 V

Q. 27

Consider the modified current mirror circuit shown in the figure below :
Consider the modified current mirror circuit shown in the figure below :

All the transistors connected in the circuit are identical with and value of A reference current of 100 mA is
forced into the circuit as shown in the figure. The circuit is used to drive N number of transistors i.e., Q1 to QN which are all
identical to the transistors QR used in mirror circuit. If it is required to maintain a minimum collector current of 99 mA,
through each transistor form Q1 to QN, then the maximum value of ‘N’ that can be achieved is equal to _________.

24

Solution :
24
Q. 28

Consider the op-amp circuit shown in the below figure.

A T-network is connected in the feedback circuit and resistor R3 is kept variable to after the gain of the amplifier. If the value

of then the value of R3 for which the gain of the amplifier is –8 V/V is __________

kΩ.

Solution :
3
Q. 29

Consider the op-amp circuit shown in the figure below.

The value of RF and R1 are 100 kΩ and 1 kΩ respectively. It is an inverting amplifier with input offset voltage drift of
and input offset current drift of 0.5 nA/°C. The amplifier’s circuit output voltage is equal to zero at 25°C for zero input
voltage. If an input voltage of 7 mV is applied to the amplifier then the value of output voltage at 45°C is equal to _________ V.
(Assuming that the input offset voltage is taking at the non-inverting terminal as positive)

-0.67 (-0.90 - -0.50)

Solution :
-0.67 (-0.50 - -0.90)
Q. 30

Consider the multistage amplifier circuit shown in the figure below.

The two transistors are biased such that the transconductance of both the transistors is 20 mA/V. If of the two transistors
is equal to 100, then the value of 3-dB cutoff frequency due to capacitor C is equal to _________ Hz.

1.81 (1.75 - 1.90)

Solution :
1.81 (1.75 - 1.90)
Q. 31

Consider the RC phase shift oscillator as shown in the figure below. The op-amp circuit is assumed to be ideal. The minimum
RF will the circuit have sustained oscillations at a frequency of 100 Hz is _______ kΩ.

188.21 (187 - 190)

Solution :
188.21 (187 - 190)

Q. 32

Consider the amplifier circuit shown below, which is biased with an ideal current source.
If the transistor has of 100 and early voltage VA of 10 V, then the small signal voltage gain will be ________.

(Assume VT = 25 mV).

-400 (-405 - -395)

Solution :
-400 (-405 - -395)

Q. 33

In the circuit shown below, the MOSFET has threshold voltage of 1 V and The body terminal of

the device is shorted to the source terminal and the channel length modulation parameter is zero.

If it is required to keep the MOSFET always in the saturation region, then the maximum value of the gate voltage (Vg) that can
be applied will be _________ V.

2
Solution :
2