Chapter 1

Number Plate Detection

1.1 Introduction

Late examinations in the field of Automatic number plate detection(ANPD) has identified a wide variety of real-
life applications such as traffic law enforcement, parking area get to control, programmed toll gathering, street
traffic observing, electronic installment frameworks, expressway, blood vessel checking frameworks for traffic
investigation and so forth. ANPD has pulled in a considerable measure of consideration of the analysts working
in the territory of picture preparing. ANPD can process the tags as per distinctive condition varieties and plate
varieties, for example, enlightenment, foundation, area, amount, estimate and some more. This paper displays an
enhanced Simulink demonstrate for ANPD, which depends on Histogram Edge handling procedure. In addition,
a reasonable technique has been proposed for an efficient FPGA - based equipment co-simulation of ANPD
framework. Equipment execution of such sort of framework offers parallelism, along these lines diminishes the
preparing time significantly. A Matlab usage of the calculation was utilized as a proof of idea before to the
equipment execution. ANPD has been an issue of worry for two decades.

1.2 Advantages
The advantage of ANPD is that any theft car can easily be detected. Also only one hardware is used to determine
and recognize the number plate.

1.3 METHODOLOGY
1.3.1 Edge-Based Text Extraction
The working methodology consists of six major stages
1. Detection: The first advance of this procedure includes the formation of Gaussian pyramid
which is made by filtering the info picture with a Gaussian bit of size 3 × 3 and after that
determination of the picture is done toward every path considerably. In the wake of
downsampling these pictures are next convolved with directional filters portions which are
utilized for edge discovery in the level 0◦, vertical 90◦ and inclining 45◦,135◦ bearings at various
introductions.
2. Localization: In the following stage, the morphological activity is done named as dilation. A
Very common property of content is that every one of the characters demonstrate near each other
in the picture to make a bunch. Because of enlargement task, pixels of content can be bunched
together and dispose of the pixels which are far from the content districts. The after effect of this
task may have some non-content locales which should be dispensed with. For this, one more task
, a region based filtering is done as such that commotion blobs can be evacuated which is
available in the picture. In this, those areas are keep which have a territory more noteworthy than
or equivalent to 1/20 of the most extreme region locale.
3. Character Extraction: This procedure prompts the information picture to be to such an extent
that the characters can be easily broken down and perceived. The content, characters, and
foundation of the picture ought to be general and foundation to-content complexity ought to be
high. Along these lines this procedure yields a yield picture with white content against a dark
foundation. either vertical or horizontal or diagonal. The whole process is well-known as gap
filling.
1.3.2 Connected Component-Based Text Extraction
The working methodology consists of six major stages
1. Pre-Processing: This area fits in with pre-processing of the calculation. Right off the bat input
shading picture is changed to the YUV shading space picture (luminance + chrominance), and
just the luminance (Y) channel is considered for additionally preparing. The Y channel contains
the shine or power estimation of the picture through the U and the V channels contain genuine
shading data. 1
 2. Edge Detection: This area compares to edge location. In this procedure, this approach is utilized
to deliver likely content districts develop when contrasted with non-content areas. The resultant
edge picture got is honed for pick up differentiate between the identified edges of picture and its
experience, with the goal that content districts can be effectively dialated .
3. Localization: The subsequent stage is centered around registering the level and vertical
projection profiles. The vertical projection profile shows the pixels whole of every section of the
picture. Essentially, the even projection profile shows the pixels total of each line of the picture.
Competitor content locales are portioned in light of flexible limit esteems. The areas which are
fall inside the edge degree are dealt with as contender for content.
4. Enhancement and Gap Filling: This segment relates to picture upgrade. The geometric
proportion of the width and the tallness of the content characters is pondered to cancel likely
non-content districts. After that the following stage is make a hole picture which includes
supplanting of pixel esteem with the foundation esteem if that pixel in the paired edge picture is
encased by dark (foundation) pixels in the all headings in an exhibit. All the divided regions are
prepared both section astute and push insightful to find out the normal area having most extreme
level and vertical histogram esteem, which is known as the locale of intrigue extraction. This is
the required area which really contains the tag.

1.3.3 Histogram based Edge Processing

The working methodology consists of six major stages
1. Pre-Processing: The calculation functions admirably on any picture free of its configuration.
The picture must be two-dimensional dark scale picture. In this way, if the info picture is a three-
dimensional shaded picture, it must be changed over to a grayscale picture for additionally
preparing. Once the pre-handling is done the changed over picture is first enlarged. Expansion is a
morphological procedure through which the limits of locales of white pixels are bit by bit
developed subsequently lessening the extent of openings display in the picture. In addition,
enlargement helps in invalidating different misfortunes that come amid transformation to the
grayscale picture, viz. lighter edges, contrasts in shading, good, luminance, power and so forth.
Presently the expanded picture is filtered with the assistance of Median filter accordingly
decreasing the contortions and evacuating the "salt and pepper" noise show in the picture. In this
work the extent of the portion is set to 3x3.
2. Horizontal and Vertical Edge Processing: In this procedure, flat histogram speaks to section
shrewd histogram while vertical histogram speaks to the column insightful histogram. The two
histograms demonstrate the entirety of contrasts of dark qualities between neighboring pixels of a
picture. For finding the flat histogram, the back to back distinction between two pixels in a
segment is figured. In the event that this distinction surpasses a specific limit, it is added to the
aggregate whole of the distinctions. Toward the end, a cluster containing the section shrewd
aggregate is made. A comparative procedure is done to decide the vertical histogram, in which
lines are considered rather than sections. To forestall loss of vital data histograms are gone
through a low pass smoothing filter. In the wake of smoothing one more advanced filter is
connected over the histograms to expel undesirable zones from the picture. Undesirable zones,
here, implies the lines and segments with histogram esteems lower than a specific limit which is
computed by averaging the general histogram. The yield of this procedure is the histogram
indicating areas having a high likelihood of containing a number plate.
3. Segmentation and Region of Interest Extraction: In this step the handled picture is portioned
and the directions having a high likelihood of having the tag, are put away

2
Chapter 2
FPGA
2.1 INTRODUCTION

FPGA stands for field-programmable gate array.

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a
designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified
using a hardware description language (HDL).
FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that
allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations.
Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like
AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or
more complete blocks of memory.

2.2 ADVANTAGES

FPGA has certain advantages over microprocessor or other programmable logic devices. These are:

Performance—Taking advantage of hardware parallelism, FPGAs exceed the computing power of digital signal
processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle.

Reliability—While software tools provide the programming environment, FPGA circuitry is truly a “hard”
implementation of program execution.

2.3 ARTIX 7
Artix 7 series is an FPGA development board by Xilinx Corporation, an America based manufacturer. The
device used was of Artix 7 family namely XC7A35T-L1CSG324I. Artix-7 gadgets give the most noteworthy
execution per-watt texture, handset line rates, DSP preparing, and AMS reconciliation in a cost-improved FPGA.
Highlighting the MicroBlaze delicate processor and 1,066Mb/s DDR3 bolster, the family is the best an incentive
for an assortment of cost and power-touchy applications including programming characterized radio, machine
vision cameras, and low-end remote backhaul.

3
Chapter 3

System Generator
3.1 INTRODUCTION
System Generator is a system-level modeling tool that facilitates FPGA hardware design. It extends Simulink in
many ways to provide a modeling environment that is well suited to hardware design. The tool provides high-
level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides
access to underlying FPGA resources through low-level abstractions, allowing the construction of highly
efficient FPGA designs.

3.2 ADVANTAGES
System Generator does not replace hardware description language (HDL)-based design, but does makes it
possible to focus our attention only on the critical parts. We start in a higher-level language like C, and write
assembly code only where it is required to meet performance requirements.
Chapter 4
Vivado Hls
4.1 INTRODUCTION

Advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated
than ever before. Vivado High-Level Synthesis included as a no-cost upgrade in all Vivado HLx Editions,
accelerates IP creation by enabling C, C++ and System C specifications to be directly targeted into Xilinx
programmable devices without the need to manually create RTL. Supporting both the ISE and Vivado design
environments Vivado HLS provides system and design architects alike with a faster path to IP creation by :

 Abstraction of algorithmic description, data type specification (integer, fixed-point or floating-point) and
interfaces (FIFO, AXI4, AXI4-Lite, AXI4-Stream)
 Extensive libraries for arbitrary precision data types, video, DSP and more… see the below section
under Libraries
 Directives driven architecture-aware synthesis that delivers the best possible QoR
 Fast time to QoR that rivals hand-coded RTL
 Accelerated verification using C/C++ testbench simulation, automatic VHDL or Verilog simulation and
test bench generation
 Multi-language support and the broadest language coverage in the industry
 Automatic use of Xilinx on-chip memories, DSP elements and floating-point library

4.2 ADVANTAGE

Just by knowing the high-level code in C\C++ we can actually get the RTL level design. These days the
programmer writes code in the high-level language and easy solution rather than thinking on RTL level itself
which is quite tedious.
Chapter 5
Project Design Flow
We developed a Matlab code in order to recognize the number plate detection and our workflow design is that once
the code is written in Matlab the we identified different blocks in the System generator Simulink.

Fig 1- Basys 3 Board

Once the Simulink generated the Vivado code then the RTL level file is executed in Vivado
software and bitstream is generated. The number plate is also detected by Matlab code. Various
steps are used like morphology, dilation , median filtering etc. Pictures of various operation is
taken . Also the blocks of the system generator is identified and also shown in the figure.
The working algorithm for the system generator is shown in the figure . In system generator the
blocks for histogram and segmentation is written in Vivado Hlx.

5
 System Vivado FPGA
Simulink software Board
generator
file Artix7

MATLAB
Code

Fig 2- Design flow of the project

5.1 On Matlab and System generator (for steps see appendix 1)

1. A new Editor is created.

2. Inside the empty workspace, Matlab code was written

3. Required Matlab inbuilt function was used to detect the number plate

4. The code was analyzed and different blocks were sorted out in the Simulink

5. The block are joined as shown in the appendix

5.2 on Vivado HLS and Vivado (for steps see appendix 2)

1. A new project is created

2. A new .h file was created , the code is written in the C language

3. The file was executed and RTL level simulation was exported to Vivado software

4. This RTL level file was then exported to the block of System generator

5. The System Generator file is executed and send to the Vivado software

6. The file was then opened with the help of Vivado software for the RTL level simulation

6
6 On Matlab

The image was taken in Matlab and then processed by the code.

Figure Input image

 Figure Output image

Conclusion

The purpose of the project is achieved using Matlab and System generator and hence the
number plate was detected and shown in the output image using red colored indicator.The
Vivado software is used to generate the hardware on the FPGA. Also Hls is the new
technology which is quite interesting and helpful in developing new hardware just by
knowing the high-level language.

7
References

[1] Anagnostopoulos, Christos-Nikolaos E., et al. “License plate recognition from still images and video
sequences: A survey.” Intelligent Transportation Systems, IEEE Transactions on 9.3 (2008): 377-391.
[2] Kranthi, S., K. Pranathi, and A. Srisaila. “Automatic number plate recognition.” Int. J. Adv. Tech 2.3
(2011): 408-422.
[3] Du, Shan, et al. “Automatic license plate recognition (ALPR): A state-of-the-art review.” Circuits
and Systems for Video Technology, IEEE Transactions on 23.2 (2013): 311-325.
[4] Raut, Neha P., and A. V. Gokhale. “FPGA implementation for image processing algorithms using
Xilinx system generator.” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) 2.4 (2013).
[5] Kamat, Omaha, and Subramaniam Ganesan. “An efficient implementation of the Hough transform
for detecting vehicle license plates using DSP’S.” Real-Time Technology and Applications Symposium,
1995. Proceedings. IEEE, 1995.
[6] Wang, Kongqiao, and Jari A. Kangas. “Character location in scene images from digital camera.”
Pattern Recognition 36.10 (2003): 2287-2299.
[7] Zhong, Yu, Kalle Karu, and Anil K. Jain. “Locating text in complex color images.” Document
Analysis and Recognition, 1995., Proceedings of the Third International Conference on. Vol. 1. IEEE,
1995
[8] Liu, Xiaoqing, and Jagath Samarabandu. “Multiscale edge-based text extraction from complex
images.” Multimedia and Expo, 2006 IEEE International Conference on. IEEE, 2006.
[9] Liu, Xiaoqing, and Jagath Samarabandu. “An edge-based text region extraction algorithm for indoor
mobile robot navigation.” Mechatronics and Automation, 2005 IEEE International Conference. Vol. 2.
IEEE, 2005.
[10] Chen, Chun Yu, et al. “Application of image processing to the vehicle license plate recognition.”
Advanced Materials Research. Vol. 760. 2013.
[11] Sulaiman, Nasri, et al. “Development of automatic vehicle plate detection system.” System
Engineering and Technology (ICSET), 2013 IEEE 3rd International Conference on. IEEE, 2013.
[12] Al-Ghaili, Abbas M., et al. “A new vertical edge detection algorithm and its application.” Computer
Engineering & Systems, 2008. ICCES 2008. International Conference on. IEEE, 2008.
[13] Kate, Rupali. “Number Plate Recognition Using Segmentation.” International Journal of
Engineering Research and Technology. Vol. 1. No. 9 (November-2012). ESRSA Publications, 2012.
[14] Das, M. Swamy, B. Hima Bindhu, and A. Govardhan. “Evaluation of text detection and localization
methods in natural images.” International Journal of Emerging Technology and Advanced Engineering
2.6 (2012): 277-282.

8
 Appendix 1

Elaborated steps for Project Designing

1.1 Creation of project in Matlab
Fig 1.1 shows the creation of new editor in matlab
1.2 Programing the given piece of Task

Fig 1.2 The code is written in the editor

1.3 Creation of System Generator Simulink model
Fig 1.3 Shows the process of creation of Simulink model
Appendix 2

Elaborated steps for Project Designing

Fig2.1 shows the creation of project in Vivado HLS

Appendix 3
Source code

clear;
tic
warning('off');
fac=12;
dilfac=3;
I=imread('C:\Users\Reliance\Desktop\t13.JPG');
I=imresize(I,[640,NaN]);
figure(100000),imshow(I),hold on;
I=imgaussfilt(I);
a=rgb2gray(I);
b=edge(a,'sobel');
%b=imfill(b,'holes');
se1=strel('line',dilfac,90);
se=strel('line',dilfac,0);
b=imdilate(b,se);
b=imdilate(b,se1);
%imshow(b);

avg_size=avgsiz(b);
b=bwareaopen(b,floor(avg_size/fac));
% figure,imshow(b);
c=bwareaopen(b,floor(avg_size*fac));
%figure,imshow(c);
d=imsubtract(b,c);
d=imfill(d,'holes');
se=strel('line',2*dilfac,0);
se1=strel('line',dilfac,90);
d=imdilate(d,se);
d=imdilate(d,se1);
%figure,imshow(d);

avg_size=avgsiz(d);
b=bwareaopen(d,floor(avg_size));
%figure,imshow(b);
c=bwareaopen(d,floor(avg_size*fac));
%figure,imshow(c);
d=imsubtract(b,c);
d=imfill(d,'holes');
%figure,imshow(d);
avg_size=avgsiz(d);
b=bwareaopen(d,floor(avg_size));
%figure(1010101),imshow(b);
[L,num]=bwlabel(b);
bbox=regionprops(L,'BoundingBox');
count=0;
for i=1:num
[row,col]=find(L==i);
width=numel(unique(col));
height=numel(unique(row));

if(width/height>3 && width/height<6 || width/height<2.6 && width/height>.6 )

count=count+1;
this=bbox(i).BoundingBox;
test=I(this(2):this(2)+this(4)-1,this(1):this(1)+this(3)-1,:);
im=test;
% figure(i),imshow(test);
test=rgb2gray(test);
test=histeq(test);
test=imsharpen(test);
T=adaptthresh(test,.5,'ForegroundPolarity','dark');
te=imbinarize(test,T);
te=imcomplement(te);
te=bwareaopen(te,10);
[M,num1]=bwlabel(te);

bb=regionprops(M,'BoundingBox');

temp=[];

for j=1:num1
[row,col]=find(M==j);
this=bb(j).BoundingBox;

width=numel(unique(col));
height=numel(unique(row));
temp=[temp,width/height];
end
char=temp(find(temp>=.3 & temp<=.8));

if(numel(char)>=8 && numel(char)<=13 && var(char)<.01)

fprintf(' %d %d %f\n',i, numel(find(temp>=.3 & temp<=.8)),var(char));
te12=bbox(i).BoundingBox;
rectangle('position',[te12(1),te12(2),te12(3),te12(4)],'Edgecolor','r');
end

end
end
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