Hoy . rs Oper Q Pen loop gain as bunch” oT bree J ~~) inveytine 2 3 Non inverton } ilo wesstance band wide Prey | t @ Summing amp 4 inverting \ Now invert ney —® Trego oy a d : io OO” Di Serenades | prackteal kt ® Didderence ano” ™ 2 op-amp u 2-cp-amp * % op-orp - 4 a | & Voltage to cornnt convertor { me | gpovded f . loag loccting \oad 8 Grvent 20 voHage comertor __ 687 Comparator ‘investing or Schon tt tigger as ; ee vetting [6 No Hoge tiers eer vodky ci eeEE) YBD LINEAR ELECTRONIC CIRCUITS (B.6. EN ££) “s The nodal equation at node N is, vi dy, dy, site, 28-0 of Se R,* dt ot Integrating both sides, we get, i rt dV, =-——_[ Vj dt [oR al™ 1 1 V,(t)=-—— | V(b) dt + V,(0) o(t) mes AG) 90) -1 RiCr times the integral of input, and Rj Cy is the time constant of the integrator. Q.1. The integrators used in analog computation has three modes of operation. Draw the circuit for such an integrator and explain its working. If initial output voltage is set to -1V and input V,= -10V dc is integrated for 10 ms, find V, if RC =0.1sec. where V,(0) is the initial output voltage. Thus the output is Fig. (1) (a) LC. is initial condition voltage S is a switch with three poles, namely 1. Reset 2. Hold 3.Run ply (1) Reset mode :- Switch is in position 1. Capacitor C charges the up to initial voltage. Here V, =LC. R 1000x1073 =- ae HV =2V = Voletoms =2V. \Q.2. Discuss the errors in integrators due to input bias current and input offset voltage. Ans. The de input offset voltage appearing across the input of integrating amplifier will be int ‘egrated and will appear at the out as a linearly increasing voltage. ‘The input bias current will also f* through the feedback capacitor, charging it and producing * additional linearly increasing come ane as ohn 8 hese Ye arf