EXP NO : 07

TESTBENCH WAVEFORM -Mult

SIMULATION WAVEFORM
EXP NO : 05

ESTBENCH WAVE FORM

SIMULATION WAVE FORM

S0-S3
S4-S7

S8-S11
EXP NO : 09

TRAFFIC LIGHT CONTROLLER USING FPGA

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report
 9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "klo.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "klo"

Output Format : NGC

Target Device : xc3s250e-5-pq208

---- Source Options

Top Module Name : klo

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : lut

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : YES

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort :1

Library Search Order : klo.lso

Keep Hierarchy : NO

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator :/

Bus Delimiter : <>

Case Specifier : maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta :5

=========================================================================
=========================================================================

* HDL Compilation *

=========================================================================

WARNING:HDLCompilers:176 - Include directory \Xilinx91i\asd\ does not exist

Compiling verilog file "C:/Xilinx91i/asd/klo.v" in library work

Module <klo> compiled

No errors in compilation

Analysis of file <"klo.prj"> succeeded.

=========================================================================

* Design Hierarchy Analysis *

=========================================================================

Analyzing hierarchy for module <klo> in library <work> with parameters.

S0 = "0000"

S1 = "0100"

S10 = "1010"

S11 = "1011"

S2 = "0010"

S3 = "0011"

S4 = "0100"

S5 = "0101"

S6 = "0110"

S7 = "0111"

S8 = "1000"
 S9 = "1001"

SEC1 = "00000000000000000000000000000011"

SEC5 = "1111"

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing top module <klo>.

S0 = 4'b0000

S1 = 4'b0100

S2 = 4'b0010

S3 = 4'b0011

S4 = 4'b0100

S5 = 4'b0101

S6 = 4'b0110

S7 = 4'b0111

S8 = 4'b1000

S9 = 4'b1001

S10 = 4'b1010

S11 = 4'b1011

SEC5 = 4'b1111

SEC1 = 32'b00000000000000000000000000000011

WARNING:Xst:883 - "C:/Xilinx91i/asd/klo.v" line 77: Ignored duplicate item in case statement.

WARNING:Xst:883 - "C:/Xilinx91i/asd/klo.v" line 169: Ignored duplicate item in case statement.

Module <klo> is correct for synthesis.

=========================================================================

* HDL Synthesis *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <klo>.

Related source file is "C:/Xilinx91i/asd/klo.v".

INFO:Xst:1799 - State 0101 is never reached in FSM <state>.

INFO:Xst:1799 - State 0110 is never reached in FSM <state>.

INFO:Xst:1799 - State 0111 is never reached in FSM <state>.

INFO:Xst:1799 - State 1000 is never reached in FSM <state>.

INFO:Xst:1799 - State 1001 is never reached in FSM <state>.

INFO:Xst:1799 - State 1010 is never reached in FSM <state>.

INFO:Xst:1799 - State 1011 is never reached in FSM <state>.

Found finite state machine <FSM_0> for signal <state>.

-----------------------------------------------------------------------

| States |4 |

| Transitions |8 |

| Inputs |2 |

| Outputs |4 |

| Clock | clk (rising_edge) |

 | Reset | clr (positive) |

| Reset type | asynchronous |

| Reset State | 0000 |

| Encoding | automatic |

| Implementation | LUT |

-----------------------------------------------------------------------

WARNING:Xst - Property "use_dsp48" is not applicable for this technology.

Found 4-bit register for signal <count>.

Found 4-bit adder for signal <count$share0000> created at line 37.

Found 4-bit comparator less for signal <state$cmp_lt0000> created at line 38.

Found 4-bit comparator less for signal <state$cmp_lt0001> created at line 47.

Summary:

inferred 1 Finite State Machine(s).

inferred 4 D-type flip-flop(s).

inferred 1 Adder/Subtractor(s).

inferred 2 Comparator(s).

Unit <klo> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this
design can share the same physical resources for reduced device utilization. For improved clock
frequency you may try to disable resource sharing.

=========================================================================

HDL Synthesis Report

Macro Statistics
# Adders/Subtractors :1

4-bit adder :1

# Registers :1

4-bit register :1

# Comparators :2

4-bit comparator less :2

=========================================================================

=========================================================================

* Advanced HDL Synthesis *

=========================================================================

Analyzing FSM <FSM_0> for best encoding.

Optimizing FSM <state> on signal <state[1:2]> with gray encoding.

-------------------

State | Encoding

-------------------

0000 | 00

0010 | 11

0011 | 10

0100 | 01

0101 | unreached

0110 | unreached

0111 | unreached
1000 | unreached

1001 | unreached

1010 | unreached

1011 | unreached

-------------------

Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx91i.

=========================================================================

Advanced HDL Synthesis Report

Macro Statistics

# FSMs :1

# Adders/Subtractors :1

4-bit adder :1

# Registers :6

Flip-Flops :6

# Comparators :2

4-bit comparator less :2

=========================================================================

=========================================================================

* Low Level Synthesis *

=========================================================================
Optimizing unit <klo> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block klo, actual ratio is 0.

Final Macro Processing ...

=========================================================================

Final Register Report

Macro Statistics

# Registers :6

Flip-Flops :6

=========================================================================

=========================================================================

* Partition Report *

=========================================================================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : klo.ngr

Top Level Output File Name : klo

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : NO

Design Statistics

# IOs : 14

Cell Usage :

# BELS : 19

# GND :1

# LUT2 :5

# LUT2_L :1

# LUT4 :8

# LUT4_L :2

# MUXF5 :1

# VCC :1
# FlipFlops/Latches :6

# FDC :6

# Clock Buffers :1

# BUFGP :1

# IO Buffers : 13

# IBUF :1

# OBUF : 12

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s250epq208-5

Number of Slices: 8 out of 2448 0%

Number of Slice Flip Flops: 6 out of 4896 0%

Number of 4 input LUTs: 16 out of 4896 0%

Number of IOs: 14

Number of bonded IOBs: 14 out of 158 8%

Number of GCLKs: 1 out of 24 4%

---------------------------

Partition Resource Summary:

---------------------------
 No Partitions were found in this design.

---------------------------

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP |6 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

-----------------------------------+------------------------+-------+

Control Signal | Buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
clr | IBUF |6 |

-----------------------------------+------------------------+-------+

Timing Summary:

---------------

Speed Grade: -5

Minimum period: 3.213ns (Maximum Frequency: 311.250MHz)

Minimum input arrival time before clock: No path found

Maximum output required time after clock: 5.621ns

Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 3.213ns (frequency: 311.250MHz)

Total number of paths / destination ports: 40 / 6

-------------------------------------------------------------------------

Delay: 3.213ns (Levels of Logic = 2)

Source: state_FFd2 (FF)

Destination: state_FFd2 (FF)

Source Clock: clk rising

 Destination Clock: clk rising

Data Path: state_FFd2 to state_FFd2

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 12 0.514 0.820 state_FFd2 (state_FFd2)

LUT4:I3->O 1 0.612 0.387 state_FFd2-In_SW2 (N24)

LUT4:I2->O 1 0.612 0.000 state_FFd2-In (state_FFd2-In)

FDC:D 0.268 state_FFd2

----------------------------------------

Total 3.213ns (2.006ns logic, 1.207ns route)

(62.4% logic, 37.6% route)

=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 9 / 5

-------------------------------------------------------------------------

Offset: 5.621ns (Levels of Logic = 2)

Source: state_FFd2 (FF)

Destination: lights<3> (PAD)

Source Clock: clk rising

Data Path: state_FFd2 to lights<3>

Gate Net
 Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 12 0.514 0.969 state_FFd2 (state_FFd2)

LUT2:I0->O 1 0.612 0.357 state_Out31 (lights_3_OBUF)

OBUF:I->O 3.169 lights_3_OBUF (lights<3>)

----------------------------------------

Total 5.621ns (4.295ns logic, 1.326ns route)

(76.4% logic, 23.6% route)

=========================================================================

CPU : 2.79 / 2.87 s | Elapsed : 3.00 / 3.00 s

-->

Total memory usage is 186964 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 4 ( 0 filtered)

Number of infos : 8 ( 0 filtered)

EXP.NO:08

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "swled.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "swled"

Output Format : NGC

Target Device : xc3s500e-5-fg320

---- Source Options

Top Module Name : swled

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : lut

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : YES

Resource Sharing : YES

Asynchronous To Synchronous : NO
Multiplier Style : auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort :1

Library Search Order : swled.lso

Keep Hierarchy : NO

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator :/

Bus Delimiter : <>

Case Specifier : maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta :5

=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling verilog file "swled.v" in library work

Module <swled> compiled

No errors in compilation

Analysis of file <"swled.prj"> succeeded.

=========================================================================

* Design Hierarchy Analysis *

=========================================================================
Analyzing hierarchy for module <swled> in library <work>.

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing top module <swled>.

Module <swled> is correct for synthesis.

=========================================================================

* HDL Synthesis *

=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <swled>.

Related source file is "swled.v".

Unit <swled> synthesized.

=========================================================================

HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================

* Advanced HDL Synthesis *

=========================================================================

Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx91i.

=========================================================================

Advanced HDL Synthesis Report

Found no macro

=========================================================================

=========================================================================

* Low Level Synthesis *

=========================================================================

Optimizing unit <swled> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block swled, actual ratio is 0.

Final Macro Processing ...

=========================================================================

Final Register Report

Found no macro

=========================================================================

=========================================================================

* Partition Report *

=========================================================================

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : swled.ngr

Top Level Output File Name : swled

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : NO

Design Statistics

# IOs :8

Cell Usage :

# IO Buffers :8

# IBUF :4

# OBUF :4

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s500efg320-5

Number of Slices: 0 out of 4656 0%

Number of IOs: 8

Number of bonded IOBs: 8 out of 232 3%

---------------------------

Partition Resource Summary:

---------------------------
 No Partitions were found in this design.

---------------------------

=========================================================================

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -5

Minimum period: No path found

 Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 4.632ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 4 / 4

-------------------------------------------------------------------------

Delay: 4.632ns (Levels of Logic = 2)

Source: sw<3> (PAD)

Destination: led<3> (PAD)

Data Path: sw<3> to led<3>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 1.106 0.357 sw_3_IBUF (led_3_OBUF)

OBUF:I->O 3.169 led_3_OBUF (led<3>)

----------------------------------------

Total 4.632ns (4.275ns logic, 0.357ns route)

(92.3% logic, 7.7% route)

=========================================================================

CPU : 2.89 / 3.00 s | Elapsed : 3.00 / 3.00 s

-->

Total memory usage is 190548 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)