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ABSTRACT
Yield issues are very important and costly in semiconductor manufacturing process as it depends
on the maturity of the process technology involved. To address yield issues and make sure the
silicon device comes out functionally successful requires very high test coverage. In this paper, it
will present the strategy to ensure that high test coverage more than 98% coverage can be
achieved for SOC chip with multimillions of gates.
The work is cover from RTL level up to test pattern generation. It is also discussed further about
how to debug DFT violation and failure in ATPG simulation. Full scan implementation has been
done for testing core design 0.18 um process technology with 3 M gates SOC design.
In this paper also, it is also presented the flow and methodology that used in IC design Lab for
every stage and why the flow in implemented in this work.
Table of Contents
1.0 Introduction………………………………………………………………………………….6
2.0 DFT Challenge and DFT Goal……………………………………………………………...6
2.1 DFT Project Implementation……………………………………………………………….6
2.2 Full Scan Flow and Methodology…………………………………………………………..7
2.3 RTL Cleanup………………………………………………………………………………...9
2.3.1 Common DFT Violation………………………………………………………………...9
2.3.1.2 Latches…………………………………………………………………………...9
2.3.1.3 Uncontrollable Clock…………………………………………………………….9
2.3.1.4 Asynchronous Reset As a data………………………………………………….9
2.3.1.5 Bus Contention………………………………………………………………….10
2.3.1.6 Sensitivity of Feedback Loop…………………………………………………..10
2.3.2 Violation Coding Example……………………………………………………………..11
2.4 Synthesis and Scan-Stitching………………………………………………………………12
2.4.1 Scan Chain Architecture……………………………………………………………….13
2.4.2 Scan Testing Clock……………………………………………………………………...13
2.4.3 Control Signal during Scan Testing…………………………………………………...13
2.4.4 Hookup Test Port……………………………………………………………………….14
2.4.5 Latch Clock Gating……………………………………………………………………..15
2.5 Handling Hard Macro: ARM7TDMI and Memories…………………………………….16
3.0 ATPG Run and Fault Simulation………………………………………………………….16
3.1 Increasing Test Coverage With Data Analysis……………………………………………16
3.2 Blockage Tracking and Debugging………………………………………………………..18
3.3 Fault Simulation with VCS Simulator…………………………………………………….20
3.4 Failure Simulation and Debugging………………………………………………………..23
4.0 Discussion and Conclusion ………………………………………………………………..25
4.1 Discussion……………………………………………………………………………….25
4.2 Conclusion...………………………………………………………………………………...26
5.0 Acknowledgement...………………………………………………………………………...26
6.0 References…………..……………………………………………………………………….26
SNUG Singapore 2008 2 Strategy to Achieve High Test Coverage for SOC
List of Figures
SNUG Singapore 2008 3 Strategy to Achieve High Test Coverage for SOC
List of Tables
SNUG Singapore 2008 4 Strategy to Achieve High Test Coverage for SOC
1.0 Introduction
Semiconductor manufacturing is like any other production process and has inter-related
chemical, electrical and mechanical engineering operations. The yield is defined on the
expectancy of the silicon output without any manufacturing defects or faults.
Test coverage is calculated based on how many faults that can be covered compared to the total
number of possible faults in the chips. Since the complexity of the SOC increases rapidly, there
is no way to test the millions of gates in a chip without help from well- structured test programs.
Objective of the test program should be to generate test patterns that controls and observes
almost all possible fault sites within silicon from chip periphery.
In section 2.0, it is elaborate the method in each stage from coding level until scan stiching. It is
also give an example coding method and how to debug the DFT violation. It is also describes
DFT architecture in SOC for handling clock distribution, reset distribution and bypassing IPs. All
DFT architecture with the correct constraint and the specification for all valid scan path and
invalid scan cell must be listed in DFT work. Debugging method and analysis method is
discussed in Section 3.0. ATPG setting in TETRAMAX determined the success of DFT
performance in verfying scan specification and all the information is important while debugging
failure in scan simulation In Section 4, some points from this prior work need to be discussed as
for the reference and improvement in future work. The conclusion is also including at the end of
the paper.
SNUG Singapore 2008 5 Strategy to Achieve High Test Coverage for SOC
embedded in this SOC design had been bypassed using test mode pin during testing exclude USB
and AMBA module. For USB and AMBA module, the scan chain will be implemented and
integrate with other module in design. In Figure 1, it shows the design diagram of the this
Wireless IC with its BSR(Boundary Scan Register) cell. This design is consist of 256 pads, BSR
cell to support boundary scan testing, JTAG tap controller, core design and some small is
sub_top_core in handling clock and reset.
SNUG Singapore 2008 6 Strategy to Achieve High Test Coverage for SOC
But after achieved the target there is a recommended flow that DFT engineer could follow. The
recommended flow is shown at Figure 2.
SNUG Singapore 2008 7 Strategy to Achieve High Test Coverage for SOC
2.3 RTL Cleanup:
As mentioned at introduction part, the strategy that we emphasized to have a quality result for
DFT performance is ensure all RTL blocks is passing DFT violation. The clean up RTL means
all the violations is need to improve at coding stage. In this stage the code is not only met its
functionality requirement but meet testability requirement.
There is an option in the tool to do automation fix for the DFT violation reported but due to some
violation the tools cannot improve it. It is also not advisable to use this approach as to forbidden
the tools creates its additional logic that could disturb timing requirement. It is also beneficial to
STA team, whereby the clock driven, generated clocks, uncontrollable asynchronous reset and
synchronous reset and feedback path loop can be traced earlier. From this information the timing
constraint and the timing optimization can be debugged earlier while designer doing the RTL
coding.
2.3.1.2 Latches
Latch is normally design to avoid glitches or having some delay for certain condition of
achieving a good functionality. But for DFT purpose, latch would not be included in scan chain
and tools would define it as non scan flip flop. As for this purpose if the designer could avoid the
latch, it will better to get the high coverage of the design. But if there is no ways to avoid latches
to meet the functionality performance, before scan stitching all the latches must be define to be
excluded from scan chain.
SNUG Singapore 2008 8 Strategy to Achieve High Test Coverage for SOC
2.3.1.5 Bus Contention
Bus contention could happen if the same bus is having a conflict data float in same bus between
two different flops. This is always happened if the code of the register is using multi dimensional
array method.
1) Multi-dimensional array
RTL example:
This option in DC, will ensure that the bus structures of multi-dimensional array will follow the
correct matrix as is has been coded.
When scan input port is a bidirectional pad, to avoid the conflict of tester and design driving at
same time, the tristate buffer at this pad is always driven as an input pad during test mode. In test
mode, input enable (IE) is always to be set 1’b1 and output enable (OE) is always to be set to
0’b0.
3) Tristate driver
It is well known that the bus contention could be avoided also by not putting tristate driver in
your design module.
SNUG Singapore 2008 9 Strategy to Achieve High Test Coverage for SOC
in shifting and capturing mode. If there is any blocked path or the ATPG tools cannot search for
the new set of loading value to break the loop, the code must be changed as well.
Some coding could be generated many violations based on the poor style coding. Example shown
in box below is the RTL that coded to generate the counter to count error bit. In the point of DFT
view, the first line of the RTL box code will generate the violation as the asynchronous reset
signal is having a computation with other data. Figure 4 is presenting all DFT violation that had
been reported by ATPG tool .All the other register that inputted by the violated asynchronous
signal (reset as data) or violated clock (clock as data) is violated.
D Q
clk
X1 violation
A0
A1
Y
ber [1]
B0
SNUG Singapore 2008 10 Strategy to Achieve High Test Coverage for SOC
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
rdat_tx <= 0;
buff_tx_rdy <= 0;
cnt <= 0;
ber <= 0;
ctrl_bep <= 0;
state <=0;
err_burst <= 0;
rdy <= 0; // 001-b1,010-b2,011-b3,100-b4, 111-
block
ber_done <= 0;
end
else
begin
if(rdy_tx) // grab tx data
begin
cnt <= cnt + 1;
rdat_tx[cnt] <= dat_tx;
if(cnt == 455)
buff_tx_rdy <= 1'b1; // all data are ready in buffer
end
else if(rdy==3'd7)
begin
buff_tx_rdy <= 0;
rdy <= 0;
ber <= 0;
err_burst <= 0;
ctrl_bep <= 0;
ber_done <= 0;
end
else if(cnt>9'd455)
cnt <= 0;
else if(buff_tx_rdy)
begin
if(rdy != 0)
begin
ber <= ctrl_bep + ber;
SNUG Singapore 2008 11 Strategy to Achieve High Test Coverage for SOC
during scan-stitching is disabled as timing optimization will be primarily handled by synthesis
team.
SNUG Singapore 2008 12 Strategy to Achieve High Test Coverage for SOC
IO Pads
BSR cells BSR cells IO Pads
Pad 1 sub_top_gprs (core design)
0
EM_D[0] 1 Pad 129
EM_A[0]
test_si1
test_mode
test_so1
Pad 130
0
Scan input port sharing Scan Chain 1 io_em_a_pad_0 1
EM_A[1]
io_em_a_pad_1
Example of clock
sub_clkin
bypassing
Clock distributions
CLKIN
Module from PLL
PLL
0
1
io_bb_txst
test mode
test_si64 0
test_so64
1
io_i2c_sda
sub_clkin Scan Chain n
In this project, hookup test port at the top level will be done manually on RTL as the limited
option in DFT tool which only allow Scan Enable(SE) signal to control the IO pads instead of
using test mode pin. While BSR cell is been inserted at top level RTL, all this port must be set as
a linkage port:
SNUG Singapore 2008 13 Strategy to Achieve High Test Coverage for SOC
set_bsd_linkage_port -port_list {MODE[2] MODE[1] MODE[0] CLKIN SE RFMD_CLKR
EM_DCLK_IN TESTCLK0 TESTCLK1}
SE pin is having maximum fanout from the top level to the all connection of the scan flops, the
timing constraint for SE pin is a most critical part to STA team to ensure the timing performance
is meet between the tester and the chip. Therefore to avoid possibility of the timing issue between
the ATE and SE signal of the chip, it was decided to choose the test mode pin to control IO pads
for scan testing. After the hookup test port is done, the scan stitching netlist of core design will
be compiled together in DC, to have a complete full scan netlist and SPF generated file.
In synthesis works, the synthesis guy is also optimizing the power performance of the chip itself.
In improving the power performance in term of saving power for the remaining inactive
switching work of the circuit, the clock gating cell should be inserted while running synthesis.
Latch is a non scan flop and it will disturbed the controllable and observable of the test pattern
propagating between the scan flops, there is a way to handle the violation to improve the test
coverage. The few options are already served mainly for DFT purpose by Power Compiler tool.
The option we used is to put the control signal before Scan Enable pin to get higher test
coverage. The details explanation can be referred to the reference [11]. It was stated that the fault
coverage using Scan Enable signal before the latch is given higher fault coverage.
insert_clock_gating
propagate_constraints -gate_clock
hookup_testports -verbose
SNUG Singapore 2008 14 Strategy to Achieve High Test Coverage for SOC
2.5 Handling Hard Macro: ARM7TDMI and Memories
For the memories, the testing for manufacturing defect is used built in self test (BIST) method
where the test mechanism and test algorithm is separate mode with testing mode. As the
memories is a hard macro all the memories will isolated from the testing. This bypassing work is
done manually coded at RTL coding stage.
As ARM7TDMI is a hard macro and do not have a scan chain stitched in its core, in scan testing
mode this ARM macro had been bypassed. Some of the combinational logic surround the ARM
will not be tested but it is not effected the fault coverage for the whole design as the nodes point
is too little compared to overall total fault.
Analysis of violations is effectively done using the advanced features of ATPG tools. Using GUI
schematic and also extensive reports, we can get the information of all criteria of fault
propagating in the design. All ATPG untestable paths for STA1 or STA0 can be used as a
reference to investigate the root cause of low test coverage for overall design.
The graph is obtained by choosing the module that presented the fault number bigger than 20k
faults in design. From this result, the module that has a significant low fault coverage and bigger
fault number is USB module. In the graph, turquoise colored bar shows that fault coverage for
SNUG Singapore 2008 15 Strategy to Achieve High Test Coverage for SOC
USB block is only achieved 49.3% fault coverage. But compared to the result from USB module
itself it has test coverage of 98.99%, after the scan path integrated to the top level test coverage
drops by more than 50%. Due to increase the fault coverage for overall design, the analysis on
the uncontrollable and unobservable point must be done.
SNUG Singapore 2008 16 Strategy to Achieve High Test Coverage for SOC
3.2 Blockage Tracking and Debugging
Figure 11: Blocking Path between USB and Synchronous Reset Synchronizer Module
As the violation is not occurs from the module itself, the integration path for each clocks,
asynchronous reset and synchronous reset reviewed from path to path. From the Figure 11, it s
traced that blockage is happen between reset synchronize block to reset synchronous signal from
external patterns. Blockage means the pattern that enable to detect Stuck-AT-1 and Stuck-AT-0
for the USB logics cannot be controlled where the combinational APTG cannot propagate from
the primary input to check the defect point.
To fix the issue, the synchronous reset itself need to be connected from any nearer input pin
while scan testing. Therefore all the test patterns that to detect fault can be controlled easily and
the fault can be observed savely. As the RTL is been freeze this time, the new connection is done
into the verilog netlist shown in the box bellow.
SNUG Singapore 2008 17 Strategy to Achieve High Test Coverage for SOC
Figure 12: Blockage path before fixed
SNUG Singapore 2008 18 Strategy to Achieve High Test Coverage for SOC
Figure 15: Test Coverage vs Module Name
The test coverage for the whole core design is finally achieved up to 97.19%. This result is
achieved for the basic ATPG run as shown in the Figure 14 and Figure 15.
After fixed all violation at basic scan atpg, scan simulation need to be done for chain simulation.
After it passed, the simulation will be run at parallel simulation and random pattern on serial
simulation.The flow of the fault simulation and ATPG test generation is shown from the Figure
16. After doing test case simulations and debugging the final settings for the ATPG to is as
below:
set_atpg -capture_cycles 4
set_atpg -abort_limit 100
set_atpg -resim_basic_scan_pattern mask
SNUG Singapore 2008 19 Strategy to Achieve High Test Coverage for SOC
run_atpg fast_sequential_only -auto
analyze_faults -class au
analyze_faults -class ud
report summaries sequential_depths
set_atpg -capture_cycles 6
set_atpg -abort_limit 100
set_atpg -resim_basic_scan_pattern mask
run_atpg fast_sequential_only -auto
report summaries sequential_depths
analyze_faults -class au
analyze_faults -class ud
set_atpg -capture_cycles 8
set_atpg -abort_limit 100
set_atpg -resim_basic_scan_pattern mask
run_atpg fast_sequential_only -auto
report summaries sequential_depths
Final Result:
No DFT Performance DFT Synopsys Tool
CPU Time (s) 21932.89
Test Coverage 98.22%
Fault Number 2865620
SNUG Singapore 2008 20 Strategy to Achieve High Test Coverage for SOC
Basic ATPG Run for
Chain Test Pattern
Chain SImulation
Fail
Result
Pass
Parallel SImulation
Fail
Result
Pass
Fail
Result
Pass
Fail
Result
Pass
End
SNUG Singapore 2008 21 Strategy to Achieve High Test Coverage for SOC
3.4 Failure Simulation and Debugging
The parallel simulation result had shown below indicated that the chain-9, chain-25 and chain-35
is having a failure while capturing the data at the scan output port.
// *** ERROR during scan pattern 3364 (detected during final pattern unload), T= 1693300.00 ns
3364 chain9 1017 (exp=0, got=x) // pin EM_A[8], scan cell 1017
3364 chain9 1035 (exp=0, got=x) // pin EM_A[8], scan cell 1035
3364 chain9 1053 (exp=0, got=x) // pin EM_A[8], scan cell 1053
// *** ERROR during scan pattern 3364 (detected during final pattern unload), T= 1693300.00 ns
3364 chain25 82 (exp=0, got=x) // pin EM_WP[0], scan cell 82
// *** ERROR during scan pattern 3364 (detected during final pattern unload), T= 1693300.00 ns
3364 chain35 953 (exp=1, got=x) // pin EM_WE[1], scan cell 953
3364 chain35 954 (exp=1, got=x) // pin EM_WE[1], scan cell 954
// 1693400.00 ns : Simulation of 3365 patterns completed with 6 errors
Waveform shows the failure detected at EM_A[7], scan output port as it was expected to get 1,
but got 0. The assumption can be make is the failure could be timing problem. As per assumption
there was few test cases had been done, chain simulation, parallel simulation and serial
simulations. But after run serial simulation on respected chain, the simulation is passed.
SNUG Singapore 2008 22 Strategy to Achieve High Test Coverage for SOC
But one of the test case that detected on the simulation is fail with timing is running simulation
for both test pattern 257 and test pattern 258. The failure is because the hold timing between the
few register while shifting mode happen. It can be look at waveform below.
STA reports are rechecked and it was detected that the path is unconstraint and it had been traced
that the constraint for one of distribution clock had not been defined.
Startpoint: u_Apiu_baseband/u_apiu_l1c/l1c_top/sltrate/cdis_trig1/wr_iq_reg
(rising edge-triggered flip-flop)
Endpoint: u_Apiu_baseband/u_apiu_l1c/l1c_top/sltrate/main1/adjust_tb_reg_0_
(rising edge-triggered flip-flop clocked by clkin)
Path Group: (none)
Path Type: min
Incorrect setting
set_case_analysis 1 u_sub_top_Wireless_IC_Design/u_comb_logic/clkmux2/S0
set_case_analysis 0 u_sub_top_Wireless_IC_Design/u_comb_logic/clkmux1/S0
Correct Setting:
set_case_analysis 0 u_sub_top_Wireless_IC_Design/u_comb_logic/clkmux2/S0
set_case_analysis 1 u_sub_top_Wireless_IC_Design/u_comb_logic/clkmux1/S0
SNUG Singapore 2008 23 Strategy to Achieve High Test Coverage for SOC
After the STA team put the correct DFT constraints and closed timing, the simulation with
timing fixed netlist is passing simulations. After fixing timing for the test mode, the simulation is
passing. Scan simulation for all test vectors have been done using two different format of test
program, verilog format and STIL format. The results are tabled as below:
Scenario 1: Timing in test mode is clean but timing in functional mode not clean
Scenario 2: Both timing performance of the functional mode and test mode is clean
After the STA team closed the timing clean for both of functional mode and testing mode, the
scan simulation passed for all type of scan simulation using STIL test program but using verilog
simulation there is still 1 failure. From the scenarios, STIL simulation is performed better
compared to verilog simulation.
SNUG Singapore 2008 24 Strategy to Achieve High Test Coverage for SOC
o From the Table 1 and Table 2, it is also recommended to do the scan simulation based on
the STIL protocol is using STIL test pattern. it is also directly supported by the fab ATE
where the same STIL database could be simulated and run in the ATE. This saves disk
space, and validates the actual pattern set and not a "branch" in the flow of data to a
Verilog pattern database that only had value for simulation [5].
o It is undeniable that the scan testing is only use low-speed test (10 MHz) rather than high-
speed functional clock (WIRELESS_IC_DESIGN 52 MHz). Transition faults may not be
covered but it is more applicable for deep submicron technology. For the target 0.18u
technology, stuck-at fault model coverage suffices the required fault coverage
requirements.
Further Discussion:
The quality of the overall performance of the test coverage based on the cost of the
manufacturing defect and other issues faced during post-silicon test pattern debugging are not
covered in this paper. It will be discussed further in the future paper.
4.2 Conclusion
This paper had discussed the flow and the methodology work to get high test coverage and how it
is implemented in Wireless IC Labs project. The high test coverage is finally obtained for this
design is 98% test coverage. Some issues had also had been shown and the solution to solve the
problem had also been discussed.
5.0 Acknowledgement
The appreciation goes to those involved in this project and gave full cooperation in achieving
good result. Acknowledgements to Suhaimi Bahisham, Muhammad Khairol, Roslee, Mohamed
Farid, Noraini, Zubir, Sridar, Sivaprasad Embanath, Norliza Jalani and Nazaliza Othman.
6.0 References
1. Tracy Larrabee, Member, IEEE, Test Pattern Generation Using Boolean
Satisfiability, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. 11,
NO. 1, JANUARY 1992
2. DFT Compiler DFT Architecture User Guide (DB Mode) ,Version X-2005.09, September
2005
3. DFT Compiler User Guide Vol. 1: Scan (XG Mode) Version Y-2006.06, June 2006
4. TetraMAX® ATPG User Guide Version Y-2006.06, June 2006
5. Test Pattern Validation User Guide Version Y-2006.06, June 2006
6. Kyeongsoon Cho, Randal E. Bryant, Carnegie Mellon University
Test Pattern Generation For Sequential MOS Circuit by Symbolic Simulation
7. Sukalyan Mukherjee, Design for Testability to Achieve High Test Coverage- A
Case Study, Wipro Ltd.
SNUG Singapore 2008 25 Strategy to Achieve High Test Coverage for SOC
8. Yinghua Min and Zhongcheng Li, Evaluation of Test Generation Algorithms
Center for Fault-Tolerant Computing, CAD Lab. Institute of Computing
Technology, Academia Sinica Beij ing, China
9. Wang Wu Wen,2006 VLSI Test Principle and Architecture, Elsevier Inc
10. J. Bhasker , Verilog HDL Synthesis
11. Power Compiler" User Guide Version Y-2006.06, June 2006, Chapter 12
SNUG Singapore 2008 26 Strategy to Achieve High Test Coverage for SOC