Handout #5

EE 214
Winter 2009

MOS Transistor Modeling for Analog Design

Part II

B. Murmann and B. A. Wooley

Stanford University

Corrections:
1/23/09: Fixed ωp2 expression on slide 32; see also text p. 641

Re-cap

Subthreshold
Operation

Transition to
Strong Inversion

ƒ What causes the discrepancy between 2/VOV and 0.18μm NMOS in

strong inversion?

B. A. Wooley, B. Murmann EE214 Winter 2008-09 2

 Short Channel Effects

ƒ Velocity saturation due to high lateral field

ƒ Mobilityy degradation
g due to high
g vertical field
ƒ Vt dependence on channel length and width
ƒ Vt = f(VDS)
ƒ ro = f(VDS)
ƒ …

ƒ We will limit the discussion in EE214 to the first two aspects of the above
list, with a focus on qualitative understanding

B. A. Wooley, B. Murmann EE214 Winter 2008-09 3

Velocity Saturation (1)

ƒ IIn the
th derivation
d i ti off th the square llaw model,
d l it iis assumed
d th
thatt th
the carrier
i
velocity is proportional to the lateral E-field, v=μE
ƒ Unfortunately, the speed of carriers in silicon is limited
– At very high fields (high voltage drop across the conductive channel),
the carrier velocity saturates

Approximation:
μE
νd (E) = ≅ μEc = vscl for E >> Ec
E
1+
Ec
1
v d (Ec ) = v scl
2

B. A. Wooley, B. Murmann EE214 Winter 2008-09 4

 Velocity Saturation (2)

ƒ It is
i important
i t t to
t distinguish
di ti i h various
i regions
i iin th
the above
b plot
l t
– Low field, the long channel equations still hold
– Moderate field, the long channel equations become somewhat
inaccurate
– Very high field across the conducting channel – the velocity saturates
completely and becomes essentially constant (vscl)
ƒ T
To gett some feel
f l for
f latter
l tt two
t cases, let's
l t' first
fi t estimate
ti t the
th E field
fi ld using
i
simple long channel physics
ƒ In saturation, the lateral field across the channel is

VOV 200mV V
E = e.g. = 1.11⋅ 106
L 0.18μm m

B. A. Wooley, B. Murmann EE214 Winter 2008-09 5

Field Estimates

ƒ In 0.18μm technology, we have for an NMOS device

m
1.73 ⋅ 105
v s = 11.5 ⋅ 106 V
Ec = scl ≅
μ cm 2 m
150
Vs
Therefore
V
1.11⋅ 106
E m ≅ 0 .1
=
Ec 11.5 ⋅ 10 6 V

ƒ This means that for VOV on the order of 0.2V, the carrier velocity is
somewhat reduced,, but the impairment
p is relatively
y small
ƒ The situation changes when much larger VOV are applied, e.g. as the
case in digital circuits

B. A. Wooley, B. Murmann EE214 Winter 2008-09 6

 Short Channel ID Equation

ƒ A simple equation that captures the moderate deviation from the long
channel drain current can be written as (see text)

1 W 2 1
ID ≅ μCox VOV ⋅
2 L ⎛ VOV ⎞
⎜1 + ⎟
⎝ Ec L ⎠
1 W E L ⋅ VOV
≅ μCox VOV ⋅ c
2 L ( Ec L + VOV )

Think of this as a “parallel combination"

V
Minimum-length
Minimum length NMOS: EcL = 11.5 ⋅ 106 ⋅ 0.18μm = 2.1V
m
V
Minimum-length PMOS: EcL = 28.75 ⋅ 106 ⋅ 0.18μm = 5.25V
m

B. A. Wooley, B. Murmann EE214 Winter 2008-09 7

Modified gm/ID Expression

ƒ Assuming VOV << EcL, we can show that (see text, pp. 63-64)

gm 2 1
≅ ⋅
ID VOV ⎛ VOV ⎞
⎜1 + ⎟
⎝ Ec L ⎠

ƒ E.g.
E ffor an NMOS d
device
i with
ith VOV=200mV
200 V

gm 2 1 2
≅ ⋅ = ⋅ 0 .9
ID VOV ⎛ 0 . 2 ⎞ VOV
⎜1+ ⎟
⎝ 2 .1 ⎠

ƒ Means that the square

q g inversion ((at VOV≅200mV))
law model in strong
should be off by about 10%
ƒ This prediction agrees well with the simulation data on slide 2

B. A. Wooley, B. Murmann EE214 Winter 2008-09 8

 Mobility Degradation due to Vertical Field

ƒ In MOS technology, the oxide thickness has been continuously scaled

down with feature size
– ~6.5nm in 0.35μm, ~4nm in 0.18μm, ~1.8nm in 90nm CMOS
ƒ As a result, the vertical electric field in the device increases and tries to
pull the carriers closer to the "dirty" silicon surface
– Imperfections impede movement and thus mobility
ƒ This effect can be included by replacing the mobility term with an
"effective mobility"
μ 1
μeff ≅ θ = 0.1...0.4
(1 + θVOV ) V

ƒ Yet another "fudge factor"

– Possible to lump with EcL parameter, if desired

B. A. Wooley, B. Murmann EE214 Winter 2008-09 9

Transit Frequency Plot

1 gm
fT =
2π Cgg

B. A. Wooley, B. Murmann EE214 Winter 2008-09 10

 Observations - fT

ƒ Again the square-law model doesn't do a very good job

– Large fT discrepancy in subthreshold operation and in strong
inversion (large VOV)
ƒ The reasons for these discrepancies are exactly the same as the ones
we came across when looking at gm/ID
– Bipolar action in subthreshold operation and moderate inversion
– Short channel effects at large VOV
• Less gm, hence lower gm/Cgg
ƒ Same conclusion: we won't be able to make good predictions with a
simple square law relationship

B. A. Wooley, B. Murmann EE214 Winter 2008-09 11

gm/ID· fT Plot

gm 1 3μ
Square Law: ⋅ fT ≅
ID 2π L2

Sweet spot (?)

Short channel
Square law predicts effects
too much gm/ID

B. A. Wooley, B. Murmann EE214 Winter 2008-09 12

 Intrinsic Gain Plot

ƒ Impossible to approximate with “λ” model equation!

B. A. Wooley, B. Murmann EE214 Winter 2008-09 13

Gradual Onset of 1/gds

VDS = VOV

B. A. Wooley, B. Murmann EE214 Winter 2008-09 14

 Gradual Onset of 1/gds (Zoom)

VDS = VOV VDS = 2/(gm/ID)

B. A. Wooley, B. Murmann EE214 Winter 2008-09 15

“VDSsat” Estimate Based on gm/ID

“VDSsat” defined
(arbitrarily) as VDS at
which 1/g gds is equal
q
to ½ of the value at
VDS = VDD/2 = 0.9V

≅4kT/q

ƒ 2/(gm/ID) is a reasonable estimate of “V

VDSsat”

B. A. Wooley, B. Murmann EE214 Winter 2008-09 16

 Observations – Intrinsic Gain

ƒ Device shows a rather gradual transition from triode to saturation

– Square law predicts an abrupt change from small to large intrinsic
gain at VDS = VOV
– 2/(gm/ID) provides a reasonable estimator for the minimum VDS that is
needed to extract gain from a device
• Typically
T i ll wantt tto stay
t att lleastt 100
100mV
V above
b thi
this value
l ini practical
ti l
designs
ƒ The physics that govern the behavior of ro=1/gds are complex
– Channel length modulation
– Drain induced barrier lowering (DIBL)
– Substrate current induced body effect (SCBE)
• Not present in all technologies and/or PMOS devices
ƒ If you are interested in more details, please refer to EE316 or similar

B. A. Wooley, B. Murmann EE214 Winter 2008-09 17

The Challenge

ƒ Square-law model is inadequate for design in fine-line CMOS

– But simulation models (BSIM, PSP, …) are too complex for hand-
calculations
ƒ This issue tends to drive many designers toward a “spice monkey”
design methodology
– No hand calculations, iterate in spice until the circuit “somehow”
meetst the
th specifications
ifi ti
– Typically results in sub-optimal designs
ƒ Our goal
– Maintain a systematic design
methodology in absence of a set of
compact MOSFET equations
ƒ Strategy
– Design using look-up tables or charts
[[Courtesyy Isaac Martinez]]

B. A. Wooley, B. Murmann EE214 Winter 2008-09 18

 The Problem

B. A. Wooley, B. Murmann EE214 Winter 2008-09 19

The Solution

ƒ Use pre-computed spice data in hand calculations

B. A. Wooley, B. Murmann EE214 Winter 2008-09 20

 Technology Characterization for Design

ƒ Pl
Plott the
th following
f ll i parameters
t for
f a reasonable
bl range off gm/ID and
d
channel lengths
– Transit frequency (fT)
– Intrinsic gain (gm/gds)
– Current density (ID/W)
ƒ In addition, may want to tabulate relative estimates of extrinsic
capacitances
it
– Cgd/Cgg and Cdd/Cgg
ƒ Parameters are (to first order) independent of device width
– Enables "normalized design" and re-use of charts
– Somewhat similar to filter design procedure using normalized
coefficient tables
ƒ Do hand calculations using the generated technology data
– Can use Matlab functions to do table-look-up on pre-computed data

B. A. Wooley, B. Murmann EE214 Winter 2008-09 21

Transit Frequency Chart

L=0.18um

L=0.5um

B. A. Wooley, B. Murmann EE214 Winter 2008-09 22

 Intrinsic Gain Chart

L=0.5um

L 0 18
L=0.18um

B. A. Wooley, B. Murmann EE214 Winter 2008-09 23

Current Density Chart

L=0.18um

L 05
L=0.5um

B. A. Wooley, B. Murmann EE214 Winter 2008-09 24

 VDS Dependence

ƒ VDS dependence
is relatively weak
ƒ Typically
yp y OK to
work with plots
generated for
VDD/2

B. A. Wooley, B. Murmann EE214 Winter 2008-09 25

Extrinsic Capacitances (1)

0.70 ƒ Again, usually OK

to work with
estimates taken at
VDD/2

0.24

B. A. Wooley, B. Murmann EE214 Winter 2008-09 26

 Extrinsic Capacitances (2)

B. A. Wooley, B. Murmann EE214 Winter 2008-09 27

Generic Design Flow

1) Determine gm (from design objectives)

2) Pick L
ƒ Short channel Æ high fT (high speed)
ƒ Long channel Æ high intrinsic gain
3) Pick gm/ID (or fT)
ƒ Large gm/ID Æ low power, large signal swing (low VDSsat)
ƒ Small gm/ID Æ high fT (high speed)
4) Determine ID (from gm and gm/ID)
5) Determine W (from ID/W, current density chart)

Many other possibilities exist (depending on circuit specifics, design

constraints and objectives)

B. A. Wooley, B. Murmann EE214 Winter 2008-09 28

 Basic Design Example

Given specifications and objectives

– 0.18 μm technology
0 18-μm
– DC gain = -4
– RL=1k, CL=50fF, Ri=10k
– Maximize bandwidth while
keeping IB ≤ 300uA
• Implies L=Lmin=0.18um
– Determine device width
– Estimate dominant and non-
dominant pole

B. A. Wooley, B. Murmann EE214 Winter 2008-09 29

Small-Signal Model

Calculate gm and gm/ID

4 gm 4mS S
Av ( 0 ) ≅ g mRL = 4 ⇒ gm = = 4mS = = 13.3
1k Ω ID 300μA A

B. A. Wooley, B. Murmann EE214 Winter 2008-09 30

 Why can we Neglect ro?

Av ( 0 ) = g m ( RL || ro )
−1
⎛ 1 1⎞
= gm ⎜ + ⎟
⎝ RL ro ⎠
1 1 1
= +
Av ( 0 ) g mRL g m ro

1 1 1
= +
4 g mRL g m ro

ƒ Even at L=Lmin= 0.18μm, we have gmro > 30 (see slide 23)

ƒ ro will be negligible in this design problem

B. A. Wooley, B. Murmann EE214 Winter 2008-09 31

Zero and Pole Expressions

gm
High frequency zero ωz ≅ >> ωT
(negligible) Cgd

1
Dominant pole ωp1 ≅
Ri ⎡⎣Cgs + Cgb + (1 + g m RL ) ⋅ Cgd ⎦⎤
(Miller approximation)
1
≅
Ri ⎡⎣Cgg + g m RL ⋅ Cgd ⎦⎤

1
Nondominant pole ωp 2 ≅
⎛ Cgg 1 ⎞ ⎛ 2
Cgd ⎞
⎜ L
R ⎟ ⎜⎜ L
C + C − ⎟
⎜ Cgd g m ⎟⎠ ⎝ Cgg ⎟⎠
dd
⎝

B. A. Wooley, B. Murmann EE214 Winter 2008-09 32

 Determine Cgg via fT Look-up

L=0 18um
L=0.18um
16.15 GHz

B. A. Wooley, B. Murmann EE214 Winter 2008-09 33

Find Capacitances and Plug in

1 gm 1 4mS
Cgg = = = 39.4fF
2π fT 2π 16.15GHz

Cgd
Cgd = Cgg = 0.24 ⋅ 39.4fF = 9.46fF
Cgg

Cdd
Cdd = Cgg = 0.70 ⋅ 39.4fF = 27.6fF
Cgg

∴ fp1 ≅ 206MHz ∴ fp 2 ≅ 4.2GHz

B. A. Wooley, B. Murmann EE214 Winter 2008-09 34

 Device Sizing

15.5 A/m L=0.18um

B. A. Wooley, B. Murmann EE214 Winter 2008-09 35

Circuit For Spice Verification

ID 300μA
Device width W = = = 19.4μm
ID 15.5 A / m
W

Simulation circuit

B o

1F

B. A. Wooley, B. Murmann EE214 Winter 2008-09 36

 Simulated DC Operating Point

element 0:mn1 Calculation

region Saturati
id 327.6259u 300 uA
vgs 622.0847m
vds 872.3741m
vdsat 112.5042m
vod 135
135.7267m
7267m
gm 4.1837m 4 mS Good agreement!
gds 110.6098u
...
cdtot 27.0360f 27.6 fF
cgtot 39.5020f 39.4 fF
cgd 9.3506f 9.46 fF
...
gm/ID 12.8 13.3 S/A

B. A. Wooley, B. Murmann EE214 Winter 2008-09 37

HSpice .OP Capacitance Output Variables

HSpice (.OP) Corresponding Small Signal

Model Elements

cdtot 43.2542f cdtot ≡ Cgd + Cdb

cgtot 56.5745f cgtot ≡ Cgs + Cgd + Cgb
cstot ≡ Cgs + Csb
cstot 108.8336f
cbtot 113.0007f
cgs 39.3691f bt t ≡ Cgb + Csb+ Cdb
cbtot
cgd 7.2416f cgs ≡ Cgs
cgd ≡ Cgd

B. A. Wooley, B. Murmann EE214 Winter 2008-09 38

 Simulated AC Response

203 MHz
11.5 dB (3.8)

4.7 GHz

ƒ Calculated values: |Av(0)|=12 dB (4.0), fp1=206 MHz, fp2=4.2 GHz

B. A. Wooley, B. Murmann EE214 Winter 2008-09 39

Observations

ƒ The design is essentially right on target!

– Typical discrepancies are on the order of 10-20%, mostly due to VDS
dependencies, finite output resistance, etc.
ƒ We accomplished this by using pre-computed spice data in the design
process
ƒ Even if discrepancies are more significant, there’s always the possibility
to track down the root causes
– Hand calculations are based on parameters that also exist in Spice,
e.g. gm/ID, fT, etc.
– Different from square law calculations using μCox, VOV, etc.
• Based on artificial parameters that do not exist or have no
significance
i ifi iin th
the spice
i model
d l

B. A. Wooley, B. Murmann EE214 Winter 2008-09 40

 References

ƒ F. Silveira et al. "A gm/ID based methodology for the design of CMOS
analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA,"
OTA, IEEE Journal of Solid State Circuits, Sept.
Solid-State
1996, pp. 1314-1319.
ƒ D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via
the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on
El t i
Electronics, Circuits
Ci it and dS Systems
t , pp. 1179-1182,
1179 1182 SSept.t 2002
2002.
ƒ B. E. Boser, "Analog Circuit Design with Submicron Transistors," IEEE
SSCS Meeting, Santa Clara Valley, May 19, 2005,
http://www ewh ieee org/r6/scv/ssc/May1905 htm
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
ƒ P. Jespers, The gm/ID Design Methodology for CMOS Analog Low Power
Integrated Circuits, Springer, 2009

B. A. Wooley, B. Murmann EE214 Winter 2008-09 41