FPGA based Architecture for Radar’s STC, FTC and

Gain modules

Joaquín García, Gilberto Viveros, René Cumplido

Computer Science Department, INAOE, Apdo. Postal 51 & 216

Tonantzintla, Puebla, México
Email: joaquingr@ccc.inaoep.mx, {gviveros, rcumplido}@inaoep.mx

Abstract. Recent innovations like reconfigurable computing have allowed to

easy experiment new architectures that support a wide range of applications for
Digital Signal Processing (DSP). Field Programmable Gate Array (FPGA)
provides a cheap platform for research and development. Radar signal
processing is widely used for civil and military proposes. Radar’s systems
operate on Real-Time basis. This paper presents an architecture that has been
design to parallel and digital implement Sensitivity Time Control (STC), Fast
Time Constant (FTC) and Gain modules commonly used to correct some
clutters.

1 Introduction

Radar signal processing is a well known technology and widely studied, it is an

excellent tool for weather prediction, civil aviation and many other applications
including its military uses. However this is not an accessible technology for many
who could take advantage from the recent enhancements in digital technology and
reconfigurable computing. Target recovering from the echo signal is not a trivial
task since rain, snow, hail or dust clutter affects radar’s readings, resulting in poor or
false target detection or even worst to lose a target, some other problems are related to
the degradation of the signal during time and space. STC, FTC and Gain modules are
basic modules for radar signal processing that pretend to filter the echo’s signal to
reduce the effect of the mentioned clutters. This work proposes, and validates by
simulation and test bench methods, an architecture that implements the three modules
listed above.
STC, FTC and Gain are enough studied techniques, also mentioned at books, but
there are not references of digital hardware implementations.
The rest of the paper is structured as follows: Section 2 provides a technical
overview of STC, FTC and Gain. Section 3 presents the general and particular
architectures. Section 4 presents the simulation performed in order to validate the
implementation. Section 5 shows the FPGA implementation and experimental
results. In section 6, the results are discussed. Finally at section 7, conclusions are
presented.
2 Modules

2.1 STC

The first moments of a reading echo, it has high power due to the nearby and the last
readings usually have a significant power decreasing. The module responsible for
correcting this is Sensitivity Time Control (STC) also called swept gain, anti-clutter
control, suppressor or sea clutter control [1] since it is commonly used to decrease the
amplitude of nearby target that could be a false target caused by sea clutter. In calm
seas this control is set to its minimum value. STC’s main task is to detect close
targets that might be obscured by sea clutter, but if it is set to its high value trying to
remove sea-clutter, STC could remove small close targets too. The figure 1 shows
the kind of function used by the STC to correct sea clutter.

Figure 1. Echo and STC voltage Vs time (or distance).

2.2 FTC

Rain, insects, and some weather conditions like dust could be considered as noise for
the radar signal, for these situations the Fast Time Constant (FTC) module is used to
remove undesired readings, basically based on a derivative filter and some times
associated with CFAR, used to set a constant probability of false echo.
FTC some times called Rain Clutter Control, which is a variable FTC, is a
differentiator that detects abrupt changes or fluctuations in echo’s signal in order to
discriminate constant or almost-constant echo’s signal, frequently caused by rain,
dust, snow or other unwanted echoes. It is also known as differential or anti-rain
clutter control.
FTC is in fact a high pass filter whose cost is the reduction of the maximum
detection range, to avoid this problem log-FTC could be used for large distances.
When it is used to reduce rain clutter is also called weather-fix. The present work
applies the simple FTC.

2.3 Gain

Techniques for correcting attenuation are well known by DSP, for instance a Gain
module tries to reduce attenuation caused by many factors like signal degradation in
the channel or range scale being used. Gain is used to amplify the signal in order to
detect weak echoes but also can be used to decrease the signal, so strong echoes could
be distinguished from weaker ones.

3 Architecture

Each module works independently from the other two, then we propose a parallel
architecture based on stream data processing with one linear mixer that joins the three
outputs. The architecture elements are a control unit (CU), FTC module, STC
module, Gain module, mixer, a stream data bus, a clock signal and an output data bus.
CU receives the control values for each of the three modules, synchronizes the
system, configures the operation according to the range used and specifies inputs to
each module; for instance a fixed function is used to process the SCT, those values
are stored in a Look Up Table (LUT), but the address increment to read this LUT
could not be lineal due to different resolutions and ranges used at radar’s systems.

Figure 2. Architecture proposed.

Figure 3 shows the STC module which consists of a LUT, ALU, a counter and a
register to store the output data. LUT is used as STC’s curve storage, the counter is
designed to configure its increment as function of resolution, and counter’s function is
to provide the LUT’s address. FTC is shown at figure 4 and basically is a deriver
which is built with an adder and two registers, one to store the previous value and
other to store the output.

Figure 3. STC architecture. Figure 4. FTC basic architecture.

4 Simulation

In order to validate HW implementation, a simulation using MatLab was performed

using a synthetic echo, 12 bits integers and 2048 samples. The intention of
simulating was to validate the results obtained by hardware once it is implemented
and also to use the same synthetic echo to test the implementation. Figure 5 shows
the output of the simulation of a synthetic echo through the three mixed modules, the
signal with highest and lowest values is the synthetic echo and the other is the filtered
echo (darker and marked one).

Figure 5. Simulation performed with MatLab.

5 FPGA Implementation and Results

The implementation was performed in a XSA-50 board from XESS with a Xilinx
Spartan II FPGA. The system was developed with VHDL using Active-HDL from
Aldec as simulating tool, in the first stages of design and to generate some of the basic
elements; at figure 6 it is shown the block design at Active-HDL. VHDL model was
synthesized with Xilinx ISE and targeted for a XC2S50TQ144-5 (Spartan II). ISE
core generator was used for the STC LUT creation. Finally MatLab was used for
simulation, generating STC values and its S-Record and plotting the results stored at
the board SDRAM.
In order to validate the hardware implementation a test bench was implemented.
It is basically a SDRAM driver to read the synthetic echo, stored via S-record, and
also used for storing the output stream.
Table 1 summarizes resource statistics while table 2 summarizes timing statistics
after synthesis, it must be mentioned that these tables include the elements added by
the SDRAM driver.

Figure 6. Block design in Active-HDL.

The filtered signal by the proposed architecture is shown in figure 7. The filtered
signal, resulted of the hardware implementation is like the one simulated with
MatLab. Some minor differences result from the limited memory for the LUT that
stores STC values allocated at the BRAMs of the FPGA. The system throughput is
one sample per clock cycle. According with minimum period of 9.787 ns, the
maximum frequency is 102.176 MHz.
 Element Available Used Percent
Slices 768 101 13
Slice Flip Flops 1536 88 5
4 input LUTs 1536 161 10
IOBs 96 51 53
BRAMs 4 3 75
GCLKs 4 1 25

Table 1. Device utilization.

Metric Time (ns)

Minimum period 9.787
Minimum input arrival time before clock 10.363
Maximum output requires time after clock 11.852
Maximum combinational path delay 11.814

Table 2. Timing summary.

Figure 7. Results obtained.

6 Discussion

The proposed parallel architecture implements STC, FTC and Gain modules with
few and specialized dedicated hardware. This architecture performs the arithmetic
operations needed to process STC, FTC and Gain simultaneously, has latency of one
cycle and produces an output result on each clock cycle. The proposed architecture
process data on stream basis and the number of samples does not modify the latency.
Since its maximum frequency is around 100 MHz and one sample is processed by
cycle, processing 100 MSPS (Millions of Samples Per Second) could be reached, and
it is as good as commercial radars that process between 50 and 100 MSPS.
Commercial radar processes 4096x4096 samples in 2.5 seconds which means
6710886.4 samples per second. These premises give us a subjective idea of the
performance since there are not similar architectures reported.

7 Conclusions

This work presents an efficient architecture that computes STC, FTC and Gain in real
time. The designed architecture for those controls is based on parallel processing
under dedicated and specialized hardware that was reached due to flexible and cheap
platform provided by FPGA. The presented architecture is able to process 100 MPSP
which is a good metric according with commercial radars.

Acknowledgments

This work has been partially supported by the National Council for Science and Technology of
Mexico (CONACyT) under grant number 181689.

References

1. Merrill Ivan Skolnik, Introduction to Radar Systems, Editorial McGraw-Hill, 2000

2. Ray Andraka, “FPGAs Make a Radar Signal Processor on a Chip a Reality”, IEEE
Proceedings of the Asilomar Conference on Signals, Systems and Computers, October
1999.
3. Radar Navigation and Maneuvering Board Manual, 2001.
4. Stefan Sjoholm, and Lennart Lindh, VHDL for Designer, Prentice Hall, First Edition,
1997.
5. Andre DeHon, “The Density Advantage of Reconfigurable Computing”, IEEE Computer,
Vol. 33, No. 4, April 2000, pp. 41-49.