• Attributes can be applied to arrays, types, and signals.

• Broad classification of attributes is

1) Array attributes

2) Type attributes

3) Signal attributes

Examples:

Type ROM is array (0 to 15, 7 downto 0) of bit;

Signal ROM1: ROM;

Attribute Returns Examples

A’LEFT(N) Left bound of Nth ROM1’ LEFT(1)=0

index range ROM1’ LEFT(2)=7

A’RIGHT(N) RIGHT bound of Nth ROM1’RIGHT(1)=15

index range ROM1’RIGHT(2)=0

Attribute Returns Examples

A’RANGE(N) Nth index range ROM1’ RANGE(1)= 0 to 15

reversed ROM1’ RANGE(2)=7
downto 0

A’REVERSE_RANGE(N) Nth index range ROM1’ REVERSE_RANGE(1)

= 15 downto 0
ROM1’ REVERSE_RANGE(2)
= 0 to 7

Attribute Returns Examples

A’LENGTH(N) Size of Nth index ROM1’ LENGTH(1)=16

range ROM1’ LENGTH(2)=8

A’ ASCENDING True if ascending ROM1’ ASENDING(1) =

True
 ROM1’ ASENDING(2) =
false

Examples:

• Type ncolor is (red, yellow, blue, white, black, green, brown);

• Signal color: ncolor

Attributes Description Example Result

‘LEFT Left bound OF type Color’LEFT Returns red

‘RIGHT RIGHT bound of type Color‘RIGHT Returns brown

‘HIGH Largest bound type Color‘HIGH Returns brown

Description Example Result

Attributes
‘LOW Smallest bound type Color‘LOW Returns red

‘POS(V) Position of value V Color‘POS(blue) Returns 2

in type

‘VAL(P) Value at Position Color‘VAL(4) Returns black

of V in type

Attributes Description Example Result

‘SUCC(V) Value after V in Color‘SUCC(blue) Returns white

type
‘PRED(V) Value before V Color‘PRED(green) Returns black
in type
‘LEFTOF Value left to Color‘LEFTOF(green) Returns black
(before) V in
type
Attributes Description Example Result

‘IMAGE(V) Converts value V Color‘IMAGE(red) Returns “red”

of type to string

‘VALUE(S) Converts string S Color‘VALUE(“red”) Returns red

of type to value

Attribute T/E Example Kind Type

‘EVENT EV S1’EVENT VALUE BOOLEAN

In current simulation cycle, if s1 changes, this attribute becomes TRUE.
‘LAST_EVEN EV s1’LAST_VALUE VALUE TIME
T
The amount of time since the last value change on s1. If s1’EVENT is TRUE, the value of
s1’LAST_VALUE is 0.
‘LAST_VALUE EV s1’LAST_VALUE VALUE As s1
The value of s1 before the most recent event occurred on this signal.

Attribute T/E Example Kind Type

‘ACTIVE TR s1’ACTIVE VALUE BOOLEAN

If s1 has had a transaction in the current simulation cycle, s1’ACTIVE will be TRUE for this
simulation cycle.
‘LAST_ACTIVE TR s1’LAST_ACTIVE VALUE TIME

The amount of time since the last transaction occurred on s1.

‘DRIVING - s1’DRIVING VALUE BOOLEAN

If s1 is being driven in a process, s1’DRIVING is TRUE in the same process.

Attribute T/E Example Kind Type

‘DELAYED - s1’DELAYED (5 NS) SIGNAL As s1

A copy of s1, but delayed by 5 NS. If no parameter or 0, delayed by delta. Equivalent to TRANSPORT
delay of s1.
‘STABLE EV s1’STABLE (5 NS) SIGNAL BOOLEAN

A signal that is TRUE if s1 has not changed in the last 5 NS. If no parameter or 0, the resulting signal is
TRUE if s1 has not changed in the current simulation time.

Attribute T/E Example Kind Type

‘QUIET TR s1’QUIET (5 NS) SIGNAL BOOLEAN

A signal that is TRUE if no transaction has been placed on s1 in the last 5 NS. If no parameter or 0, the
current simulation cycle is assumed.

‘TRANSACTION TR s1’TRANSACTION SIGNAL BIT

A signal that toggles each time a transaction occurs on s1. Initial value of this attribute is not defined.

Entity attr_ex is

Port (B, C: in bit);

End attr_ex;

Architecture test of attr_ex is

Signal A, C_delayed5, A_trans:bit;

Signal A_stable5, A_quiet5: Boolean;

Begin

A <= B and C;

C_delayed5 <= C’delayed(5 ns);

A_trans <= A’transaction;

A_stable5 <= A’stable(5 ns);

A_quiet5 <= A’quiet (5 ns);

End test;

Waveforms for attribute test

Attributes in assert statements

Check: process

Begin

Wait until (Clk=’1’ AND Clk’EVENT);

Assert (D’stable(setup_time))

Report (“Setup time violation”)

Severity error;

Wait for hold_time;

Assert (D’stable(hold_time))

Report (“Hold time violation”)

Severity error;

End process check;

Example for Array Attributes

Procedure for Adding Bit-Vectors

procedure Addvec2

(Add1,Add2: in bit_vector;

Cin: in bit;

signal Sum: out bit_vector;

signal Cout: out bit) is

variable C: bit := Cin;

alias n1 : bit_vector(Add1'length-1 downto 0) is Add1;

alias n2 : bit_vector(Add2'length-1 downto 0) is Add2;

alias S : bit_vector(Sum'length-1 downto 0) is Sum;

begin

assert ((n1'length = n2'length) and (n1'length = S'length))

report "Vector lengths must be equal!"

severity error;

for i in s'reverse_range loop

S(i) <= n1(i) xor n2(i) xor C;

C := (n1(i) and n2(i)) or (n1(i) and C) or (n2(i) and C);

end loop;

Cout <= C;

end Addvec2;

Transport and Inertial Delays

Transport delay: is used to model the delay introduced by wiring

Example: Z1 <= transport X after 10 ns;

Inertial delay: is the default delay type for VHDL and is used to model propagation
delay of gates and other devices.

Example: Z2 <= X after 10 ns;

Waveforms for Delay Model

Z3 <= reject 4 ns X after 10 ns;
10ns 3ns 5ns
10ns
x
2ns

Z1

Z2

Z3

0 10 20 30 40 50

Exercise Problems from Roth

1. Write a VHDL function that will take two integer vectors, A and B, and find the
dot product C=å ai * bi. The function call should be of the form DOT (A, B),
where A and B are integer vector signals. Use attributes inside the function to
determine the length and ranges of the vectors. Make no assumptions about
the high and low values of the ranges. For example:

A(3 downto 1) = (1,2,3), B (3 downto 1)=(4,5,6),

C = 3 * 6 + 2 * 5 + 1 * 4 = 32

Output a warning if the ranges are not the same.

Type intarray is array (natural range <>) of integer;

Function DOT (A, B: intarray) return integer is

Alias A1: intarray (A’length-1 downto 0) is A;

Alias B1: intarray (B’length-1 downto 0) is B;

Variable Sum: integer:=0;

Begin
 Assert (A’Range = B’Range)

Report “Vector ranges are not the same!”

Severity warning;

If (A’length /= B’length) then

Report “Vector length must be equal!”

Severity error;

Return 0; End if;

For I in A1’range loop

Sum := Sum + (A1(i) * B1(i));

End loop;

Return sum;

End DOT;

2.AVHDL entity has inputs A and B, and outputs C and D. A and B are initially high.
Whenever A goes low, C will go high 5 ns later, and if A changes again, C will
change 5 ns later. D will change if A has not had any transactions for 5 ns.

Write the VHDL architecture with a process that determines the outputs C and D.

Entity dm is

Port (A, B: in bit:=’1’;

C, D: inout bit);

End dm;

Architecture dm of dm is

Begin

Process (A, A’quiet (5ns))

Begin

If (A’event) then C<= transport not A after 5ns; end if;

If (A’quiet (5ns)’event) then D <= not D; end if; End

process;End dm;