COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTOR

WITH SHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECT

PHILIP TAN BEOW YEW

UNIVERSITI SAINS MALAYSIA

2008
COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTOR WITH
SHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECT

by

PHILIP TAN BEOW YEW

Thesis submitted in fulfilment of the

requirements for the degree
of Doctor of Philosophy

August 2008
 ACKNOWLEDGEMENTS

I would like to express my gratitude to my Ph.D. project supervisor, Dr. Othman Sidek

for his guidance and encouragement throughout the duration of this project. His

support in determining the project that benefit to both my work and study is highly

appreciated.

Special thanks go to my Silterra supervisor, Al Kordesch for his unconditional

guidance and constructive suggestions, which enable me to overcome the obstacles in

my Ph.D. project. I am also grateful to Silterra management team for the

encouragement for further study and technical publications. Not forgetting to all my

supportive colleagues in Technology Development and Device Modeling team, thanks

for everything.

Finally, I would like to express my sincere thanks and utmost appreciation to my

beloved family, especially to my wife, Christine. For their undying love, support and

patient that enable me to complete my Ph.D. degree successfully.

ii
 TABLE OF CONTENTS

Page

ACKNOWLEDGEMENTS ii
TABLE OF CONTENTS iii
LIST OF TABLES vii
LIST OF FIGURES viii
LIST OF SYMBOL xiv
LIST OF ABBREVIATION xx
ABSTRAK xxii
ABSTRACT xxiv

CHAPTER 1 : INTRODUCTION

1.0 Chapter Overview 1

1.1 Introduction to Compact Modeling 1
1.2 History of Compact Modeling 2
1.3 Compact Modeling of CMOS Transistor Deep Submicron 4
Effects
1.3.1 Body effect and Bulk Charge Effect 6
1.3.2 Short Channel Effect (SCE) 8
1.3.3 Reverse Short Channel Effect (RSCE) 9
1.3.4 Narrow Width Effect (NWE) 11
1.3.5 Inverse Narrow Width Effect (INWE) 12
1.3.6 Small Size Effect on Threshold Voltage 13
1.3.7 Drain Induced Barrier Lowering (DIBL) 13
1.3.8 Channel Length Modulation (CLM) 16
1.3.9 Velocity Saturation 19
1.3.10 Subthreshold Conduction 20
1.3.11 Field Dependent Mobility 22
1.3.12 Substrate Current induced Body Effect 24
(SCBE)
1.3.13 Gate Induced Drain Leakage (GIDL) 27
1.3.14 Polysilicon Gate Depletion 28
1.3.15 Velocity Overshoot 29
1.3.16 Source and Drain Resistance Effect 29

iii
 1.3.17 Effective Width and Effective Length 30
1.4 Why Focus on STI Mechanical Stress Effect Modeling? 30
1.5 Background and Objective 31
1.6 Contributions of the Proposed Compact Models 32
1.7 Chapter Summary 33

CHAPTER 2 : LITERATURE REVIEW

2.0 Chapter Overview 34

2.1 Background and Literature Review of STI Mechanical Stress 34
Effect
2.2 Literature Review of Modeling of STI Mechanical Stress Effect 42
2.3 Chapter Summary 50

CHAPTER 3 : MODELING OF STI MECHANICAL X-STRESS

EFFECT

3.0 Chapter Overview 51

3.1 STI Mechanical x-Stress Effect 52
3.1.1 STI Mechanical x-Stress Effect on 0.18 μm CMOS 52
Technology
3.1.2 STI Mechanical x-Stress Effect on 0.13 μm CMOS 59
Technology
3.2 Modeling of STI Mechanical x-Stress Effect 63
3.3 Modeling of Width Dependence of STI Mechanical x-Stress 67
Effect
3.4 STI x-Stress Effect on CMOS Mismatch Characteristics 69
3.5 Modeling of STI x-Stress Effect on CMOS Mismatch 73
Characteristics
3.6 Chapter Summary 76

iv
CHAPTER 4 : MODELING OF STI MECHANICAL Y-STRESS
EFFECT

4.0 Chapter Overview 77

4.1 STI Mechanical y-Stress Effect 78
4.1.1 Verification of Hook Shaped Drain Current Behavior 81
4.2 Modeling of STI Mechanical y-Stress Effect 84
4.2.1 Empirical-Based STI Mechanical y-Stress Model 84
4.2.2 Physical-Based STI Mechanical y-Stress Model 86
4.2.3 STI y-stress Model versus Standard SPICE Model 90
4.2.4 Extraction Methodology of STI y-Stress Model 93
4.2.5 Application of STI y-Stress Model 96
4.3 Chapter Summary 102

CHAPTER 5 : PHYSICAL EXPLANATIONS OF STI MECHANICAL

STRESS EFFECT

5.0 Chapter Overview 103

5.1 STI Induced Compressive Stress 104
5.2 STI Stress Effect on Electron Mobility and Hole Mobility 105
5.3 Interaction of x-Stress Effect and y-Stress Effect 110
5.4 Chapter Summary 113

CHAPTER 6 : CONCLUSION AND FURTHER DEVELOPMENT

6.0 Conclusion 114

6.1 Further Development 115

REFERENCES 117

PUBLICATIONS 123

v
APPENDICES
A Compact STI x-Stress HSPICE Model 126
for 0.13 μm Technology 1.2 V CMOS Transistor
B Empirical-Based STI x-Stress Width Dependence HSPICE 129
Model for 0.13 μm Technology 1.2 V CMOS Transistor
C Empirical-Based STI x-Stress Mismatch HSPICE Model 132
for 0.18 μm Technology 1.8 V CMOS Transistor
D Physical-Based STI y-Stress HSPICE Model 135
for 0.13 μm Technology 1.2 V High-Vt CMOS Transistor
E Physical-Based STI y-Stress HSPICE Model 138
for 0.13 μm Technology 2.5 V CMOS Transistor

BIODATA OF AUTHOR 141

vi
 LIST OF TABLES

Page

Table 2.1 External applied mechanical tensile stress effect on Id as 38

reported in (Kumagai et al., 2002).

Table 2.2 Internal process-induced mechanical tensile stress on Idsat 39

as reported in (Ge et al., 2003).

Table 2.3 Piezoresistance coefficient of the compressive STI x- 41

stress and y-stress on NMOS and PMOS as reported in
(Gallon et al., 2004).

Table 3.1 Summary of short channel Vtlin change due to STI x-stress 53
for 0.18 μm CMOS technology. Published in (Tan et al.,
2004a and Tan et al., 2004b).

Table 3.2 Summary of short channel Idsat change due to STI x-stress 55
for 0.18 μm CMOS technology. Published in (Tan et al.,
2004a and Tan et al., 2004b).

Table 3.3 Summary of short and long channels Idsat change in 58

percentage due to STI x-stress for 0.18 μm CMOS
technology. Published in (Tan et al., 2004a).

Table 3.4 Summary of short channel Vtlin change due to STI x-stress 61
for 0.13 μm CMOS technology.

Table 3.5 Summary of short channel Idsat change due to STI x-stress 63
for 0.13 μm CMOS technology.

Table 3.6 Summary of STI x-stress effect on CMOS transistor Vt 72

mismatch and Id mismatch. Published in (Tan et al.,
2004c).

Table 4.1 Transistor sizes of 1.2 V High-Vt transistors and 2.5 V 96

transistors for STI y-stress model verification.

Table 5.1 Process-induced mechanical compressive stress on Idsat 105

as interpreted from paper (Ge et al., 2003).

Table 5.2 Actual silicon results of W dependence on x-stress effect 110

and L dependence on y-stress effect for NMOS and
PMOS transistors.

vii
 LIST OF FIGURES

Page

Figure 1.1 Non-uniform depletion width when Vd > 0 V (Cheng and 7

Hu, 1999).

Figure 1.2 Charge regions: (a) in long channel; (b) in short channel 8
(Liu, 2001).

Figure 1.3 Lateral doping profile with pocket implantation (Cheng 10

and Hu, 1999).

Figure 1.4 Vt versus L characteristics of a transistor with RSCE 10

(Cheng and Hu, 1999).

Figure 1.5 CMOS transistor with LOCOS isolation technology (Liu, 11

2001).

Figure 1.6 CMOS transistor with STI isolation technology. 12

Figure 1.7 Surface potential versus L for (a) long channel transistor 14
(b) short channel transistor, and (c) short channel
transistor at high Vd (Taur and Ning, 1998).

Figure 1.8 Conduction band profile showing DIBL effect in short 15

channel transistor (Yeo, 2005).

Figure 1.9 CMOS transistor operates in; (a) linear region, (b) onset 17
of saturation, (c) beyond saturation where CLM occurs
(Taur and Ning, 1998).

Figure 1.10 Id-Vd curves with Vg,2 > Vg,1, showing the relationship 18
between Va and the slope of Id in saturation (Liu, 2001).

Figure 1.11 Id-Vd characteristics with velocity saturation, solid lines 20

and as if there were no velocity saturation, dashed lines
(Taur and Ning, 1998).

Figure 1.12 Subthreshold characteristics of short and long channel 21

transistors at low and high Vd (Taur and Ning, 1998).

Figure 1.13 Mobility versus Vertical Effective Field to illustrate how 23

the mobility behavior is dominated by different
scattering mechanisms (Cheng and Hu, 1999).

Figure 1.14 Id-Vd characteristics due to SCBE (Cheng and Hu, 24

1999).

Figure 1.15 SCBE effect that increases Isub and Id due to impact 25
ionization (Cheng and Hu, 1999).

viii
Figure 1.16 Id-Vd and Rout characteristics to illustrate how their 26
behaviors are dominated by CLM, DIBL and SCBE
(Cheng and Hu, 1999).

Figure 1.17 NMOS drain region when the channel is (a) inverted, (b) 27
accumulated and (c) when n+ region surface is
depleted or inverted (Taur and Ning, 1998).

Figure 1.18 Poly gate depletion region (Cheng and Hu, 1999). 28

Figure 2.1 Layout styles of the W/L = 20 μm/0.2 μm transistor 35

(Scott et al., 1999).

Figure 2.2 NMOS Idsat versus layout types. Idsat decrease in small 35
type L = 0.2 μm is equivalent to 30 nm increase in L for
medium type L = 0.2 μm (Scott et al., 1999).

Figure 2.3 (100) silicon wafer coordinates. 36

Figure 2.4 Id change due to external x-stress (Kumagai et al., 37

2002).

Figure 2.5 Id change due to external y-stress (Kumagai et al., 37

2002).

Figure 2.6 Id change due to external z-stress (Kumagai et al., 37

2002).

Figure 2.7 Idsat change due to external applied stress for (a) PMOS 38
and (b) NMOS with 500 μm gate length (Chen and
Huang, 2002).

Figure 2.8 3D process-induced strain components (Ge et al., 39

2003).

Figure 2.9 STI mechanical x-stress effect on Id at different W 40

(Chan et al., 2003).

Figure 2.10 STI mechanical x-stress effect on Id at different L (Chan 40

et al., 2003).

Figure 2.11 Distance between STI edge and gate edge, “a” (Bianchi 43
et al., 2002).

Figure 2.12 Mobility change referenced to mobility at “a_min”, plotted 43

versus "a" (Bianchi et al., 2002).

Figure 2.13 Mobility change reference to mobility at “a_min”, plotted 44

versus “(a – a_min)/a” (Bianchi et al., 2002).

Figure 2.14 2D simulation results and transistor layout (Su et al., 46

2003).

ix
Figure 3.1 Compressive STI mechanical stress on a CMOS 51
transistor.

Figure 3.2 Short channel Vtlin versus sa characteristics for 0.18 μm 53

CMOS technology. N = 32 dice. Published in (Tan et al.,
2004a and Tan et al., 2004b).

Figure 3.3 Short channel Idsat versus sa characteristics for 0.18 μm 55

CMOS technology. N = 32 dice. Published in (Tan et al.,
2004a and Tan et al., 2004b).

Figure 3.4 Effect of STI y-stress on wide width and narrow width 56
transistors.

Figure 3.5 Long channel Vtlin versus sa characteristics for 0.18 μm 57

CMOS technology. N = 32 dice. Published in (Tan et al.,
2004a).

Figure 3.6 Long channel Idsat versus sa characteristics for 0.18 μm 58

CMOS technology. N = 32 dice. Published in (Tan et al.,
2004a).

Figure 3.7 Short channel Vtlin versus sa characteristics for 0.13 μm 60

CMOS technology. N = 27 dice.

Figure 3.8 Short channel Vtlin and Idsat versus sa characteristics for 62
0.13 μm CMOS technology. N = 27 dice. Published in
(Tan et al., 2005a and Tan et al., 2006a).

Figure 3.9 Accuracy of the proposed x-stress model on NMOS Vtlin 65

versus sa characteristics. N = 27 dice.

Figure 3.10 Accuracy of the proposed x-stress model on NMOS Idsat 65

versus sa characteristics. N = 27 dice.

Figure 3.11 Accuracy of the proposed x-stress model on PMOS Vtlin 66

versus sa characteristics. N = 27 dice.

Figure 3.12 Accuracy of the proposed x-stress model on PMOS Idsat 66

versus sa characteristics. N = 27 dice.

Figure 3.13 Fitting of the proposed W dependence model (Equation 68

37) on NMOS Vtlin and Idsat versus sa characteristics. N =
27 dice.

Figure 3.14 Fitting of the proposed W dependence model (Equation 69

38) on PMOS Vtlin and Idsat versus sa characteristics. N =
27 dice.

Figure 3.15 Standard deviation of delta Idsat versus 1/sqrt(W x L) 72

mismatch characteristics. N = 32 dice. Published in
(Tan et al., 2003 and Tan et al., 2004c).

x
Figure 3.16 Possible mechanism of STI x-stress effect on CMOS 73
transistors mismatch.

Figure 3.17 Fitting of the proposed mismatch model on NMOS Idsat 75

mismatch characteristics. N = 32 dice.

Figure 3.18 Fitting of the proposed mismatch model on PMOS Idsat 75

mismatch characteristics. N = 32 dice.

Figure 4.1 Actual silicon data showing a hook shaped Idsat curve. 78

Figure 4.2 Percentage of Idsat change referenced to W = 20 μm, for 80

1.2 V NMOS transistors. N = 171 dice. Published in
(Tan et al., 2005d).

Figure 4.3 Percentage of Idsat change referenced to W = 20 μm, for 80

1.2 V PMOS transistors. N = 171 dice. Published in
(Tan et al., 2005d).

Figure 4.4 Transistor layout with artificial width defined by using 82

Select layer.

Figure 4.5 PMOS Idsat versus width curve with and without STI y- 83
stress. N = 6 dice.

Figure 4.6 NMOS Idsat versus width curve with and without STI y- 83
stress. N = 6 dice.

Figure 4.7 Standard versus the proposed empirical-based y-stress 85

model on PMOS normal width and artificial width Idsat
data. N = 1 die. Published in (Tan et al., 2006b).

Figure 4.8 Artificial width method to characterize the STI y-stress 86

effect.

Figure 4.9 Inverse exponential function fitting to Idsat degradation 87

due to STI y-stress.

Figure 4.10 Fitting of 1/x and 1/(exp x) functions to the TCAD 2D 87

simulation data of compressive STI stress intensity on
silicon.

Figure 4.11 TCAD 2D simulation of the compressive STI stress 88

intensity in transistor active area.

Figure 4.12 Comparison of standard model versus STI y-stress 91

model fitting for 1.2 V NMOS transistors. N = 171 dice.

Figure 4.13 Comparison of standard model versus STI y-stress 92

model fitting for 1.2 V PMOS. N = 171 dice.

Figure 4.14 Effect of the STI y-stress parameters in fitting the hook 93
shaped Idsat curve.

xi
Figure 4.15 Parameters that control different regions of the hook 94
shaped Idsat curve. Symbol is data and line is model.

Figure 4.16 Effect of DW parameter, Pwint to the hook shaped Idsat 95

curve. Symbol is data, solid and dotted lines are before
and after the parameter value change.

Figure 4.17 Effect of first y-stress parameter, Pstyu01 to the hook 95

shaped Idsat curve. Symbol is data, solid and dotted lines
are before and after the parameter value change.

Figure 4.18 Effect of second y-stress parameter, Pstyu02 to the hook 95

shaped Idsat curve. Symbol is data, solid and dotted lines
are before and after the parameter value change.

Figure 4.19 Fitting of the proposed STI y-stress model on 1.2 V 98

High-Vt NMOS Vtlin and Idsat. N = 1 dice.

Figure 4.20 Fitting of the proposed STI y-stress model on 1.2 V 99

High-Vt PMOS Vtlin and Idsat. N = 1 dice.

Figure 4.21 Fitting of the proposed STI y-stress model on 2.5 V 100
NMOS Vtlin and Idsat. N = 1 dice.

Figure 4.22 Fitting of the proposed STI y-stress model on 2.5 V 101
PMOS Vtlin and Idsat. N = 1 dice.

Figure 5.1 3D compressive stress directions in a CMOS transistor. 103

Figure 5.2 Compressive stress induced by STI fabrication process. 104

Figure 5.3 Current flow of conventional CMOS transistor in the 105

[110] direction.

Figure 5.4 Silicon lattice with outer electron orbit. 106

Figure 5.5 Constant energy surface of conduction band. 106

Figure 5.6 Constant energy surface of valence band (Thompson et 107

al., 2004).

Figure 5.7 Constant energy valleys of conduction band under 107

compressive x-stressed.

Figure 5.8 Electrons effective mass in current flow direction. 108

Figure 5.9 Conduction band splitting due to compressive x-, y- and 108
z-stress.

Figure 5.10 Constant energy valleys of valence band under 109

compressive x-stressed.

Figure 5.11 Holes effective mass in current flow direction. 109

xii
Figure 5.12 Holes redistribution in the constant energy valleys of 110
valence band due to compressive x-, y- and z-stress.

Figure 5.13 Constant energy valleys of conduction band for narrow 111
width transistor under STI compressive x-stress.

Figure 5.14 Constant energy valleys of valence band for narrow 112
width transistor under STI compressive x-stress.

xiii
 LIST OF SYMBOLS

% Percent

≥ Greater or equal

Δ Delta

α Power term for L dependence STI stress effect

π pi (3.142)

μ Carrier mobility

η Ideality factor

μ0(a) Active space carrier mobility

μ0(a_min) Minimum active space carrier mobility

μA micro-Ampere

μeff Effective carrier mobility

φf Difference of Fermi potential and substrate intrinsic potential

μm micrometer

δNP Positive sign for NMOS and negative sign for PMOS

εox Oxide permittivity (12 x 8.85 x 10-12 F/m)

εs Silicon permittivity (3.9 x 8.85 x 10-12 F/m)

< Smaller

a Active space

a_min Minimum active space

Abulk Bulk charge effect

Agu0 Gaussian distribution term for STI x-stress mismatch

C Capacitance

Cdep Depletion capacitance per unit area in the bulk

Cox Gate oxide capacitance

d Distance

xiv
E Electric Field

f0, f1, f2 Representation of complicated functions

h Planck's constant (6.6262 x 10-34 Js)

I Current

Id Drain current

Id,0 Ideal long channel Id

Idlin Linear drain current

Idsat Saturation drain current

Ioff Leakage current (off current)

Isub Substrate current

J Current density

k p x (h/2π)

L Channel length

Ldrawn Drawn channel length

Leff Effective channel length

Lod Length of transistor active area (length of oxide definition)

Lod Active length

m meter

m* Effective mass

mA milli-Ampere

meV milli-electron-Volt

mV milli-Volt

N Number of samples

nc Carrier concentration

nm nanometer

p Momentum

Pa0 L dependence bulk charge parameter

xv
Pags Gate bias dependence bulk charge parameter

Paid STI x-stress mismatch magnitude parameter

Palpha0 First SCBE effect on Isub parameter

Palpha1 L dependence SCBE effect on Isub parameter

Pb0 Channel width bulk charge parameter

Pb1 Channel width offset bulk charge parameter

Pbeta0 Second SCBE effect on Isub parameter

Pcdsc Drain and source to channel coupling capacitance parameter

Pcdscb Body bias sensitivity of Pcdsc parameter

Pcdscd Drain bias sensitivity of Pcdsc parameter

Pcit Interface trap capacitance parameter

Pdsub Vt L dependence exponent DIBL parameter

Pdvt0 First SCE parameter

Pdvt0w First SS parameter

Pdvt1 L dependence exponent SCE parameter

Pdvt1w L dependence exponent SS parameter

Pdvt2 Body bias SCE parameter

Pdvt2w Body bias SS parameter

Pdwb Body bias channel width offset parameter

Pdwg Gate bias channel width offset parameter

Peta0 Vt DIBL parameter

Peta0_original Peta0 without STI stress effect

Petab Vt body bias DIBL parameter

Pk1 First-order body effect parameter

Pk2 Second-order body effect parameter

Pk3 NWE parameter

Pk3b Body effect NWE parameter

xvi
Pketa Body bias dependence bulk charge parameter

Pku0 STI stress effect on Pu0 parameter

Plint Channel length offset parameter

Plku0, Pwku0, Ppku0 STI stress effect of Pu0 binning parameters

Plku1 L fitting parameters for STI stress effect

Pll, Plw, Plwl, Plln, Plwn Channel length geometry scaling parameters

Pmobmod Mobility mode parameter

Pmp STI x-stress mismatch sensitivity parameter

Pnfactor Subthreshold turn-on swing parameter

Pngate Polysilicon gate doping concentration parameter

Pnlx RSCE parameter

Pnrd Number of drain square parameter

Pnrs Number of source square parameter

Ppclm Channel length modulation parameter

Ppdiblc1 First DIBL correction on Va parameter

Ppdiblc2 Second DIBL correction on Va parameter

Ppdiblcb Body bias DIBL correction on Va parameter

Pprwb Body bias dependence of Prdsw parameter

Pprwg Gate bias dependence of Prdsw parameter

Ppscbe1 First high Vd drain conductance modification parameter

Ppscbe2 Second high Vd drain conductance modification parameter

Ppvag Gate bias dependence Va parameter

Prdsw Drain and source resistance per μm of gate width parameter

Prsh Sheet resistance parameter

Psaref sa reference parameter

Psbref sb reference parameter

Pstxu01 STI x-stress mobility parameter

xvii
Pstxvth01 STI x-stress Vt parameter

Pstxwe STI x-stress width dependence parameter

Pstxwep STI x-stress width dependence exponential parameter

Pstyu01 First STI y-stress parameter

Pstyu02 Second STI y-stress parameter

Ptox Oxide thickness parameter

Pu0 Zero field universal mobility parameter

Pu0_original Pu0 without STI stress effect or mismatch effect

Pua First order mobility degradation parameter

Pub Parabolic mobility degradation parameter

Puc Body bias mobility degradation parameter

Pvoff Subthreshold offset voltage parameter

Pvsat Carrier saturation velocity parameter

Pvsat_original Pvsat without STI stress effect

Pvth0 Zero back bias threshold voltage parameter

Pvth0_original Pvth0 without STI stress effect

Pw0 Channel width offset NWE parameter

Pwint Channel width offset parameter

Pwl, Pww, Pwwl, Pwln, Pwwn Channel width geometry scaling parameters

Pwr Exponent effective channel width of Prdsw parameter

Pwvth0 Width binning parameter of Pvth0

Pww Channel width offset parameter

Pxj Source/drain junction depth parameter

Pxl Delta width

Pxw Delta length

q Electron charge (1.6e-19 Coulombs)

Rd Drain resistance

xviii
Rds Drain and source resistance

Rout Output resistance

Rs Source resistance

S0l, S1l L fitting parameters for STI stress effect

sa, sb Distance between STI edge and gate edge (active space)

T Temperature

Tnom Nominal temperature

V Voltage

Va Early voltage

Vb Bulk voltage

Vbi Built-in voltage

Vd Drain voltage

Vd,eff Effective drain voltage of linear to saturation smoothing function

Vdd Operating voltage

Vdsat Saturation drain voltage

Vg Gate voltage

Vmμ0 Maximum μ0(a) variation with respect to μ0(a_min)

Vs Source voltage

Vt Threshold voltage

Vtlin Linear threshold voltage

W Channel width

Wdrawn Drawn channel width

Weff Effective channel width

x Distance from the center of the channel

Xdep Channel depletion thickness in the substrate

Xdep,0 Channel depletion thickness in the substrate at zero back bias

Xpoly Poly depletion thickness

xix
 LIST OF ABBREVIATION

2D Two-dimensional

3D Three-dimensional

AA Active Area

BSIM3v3 Berkeley Short-Channel IGFET Model – Version 3.3

BSIM3v3.24 Berkeley Short-Channel IGFET Model – Version 3.3.24

BSIM3v3.3 Berkeley Short-Channel IGFET Model – Version 3.3.3

BSIM4 Berkeley Short-Channel IGFET Model – Version 4

BSIM4.3.0 Berkeley Short-Channel IGFET Model – Version 4.3.0

BSIM4.6.1 Berkeley Short-Channel IGFET Model – Version 4.6.1

BTBT Band-To-Band Tunneling

CD Critical Dimension

CLM Channel Length Modulation

CMC Compact Modeling Council

CMOS Complementary Metal Oxide Semiconductor

CTE Coefficient of Thermal Expansion

DC Direct Current

DIBL Drain Induced Barrier Lowering

DW Delta Width

EKV Bulk-referencing SPICE model

exp Exponential

GCA Gradual Channel Approximation

GIDL Gate Induced Drain Leakage

HCE Hot Carrier Effect

HISIM Hiroshima University SPICE model

HSPICE Circuit simulation engine created by Meta-Software

xx
IC Integrated Circuit

IEDM International Electron Devices Meeting

IGFET Insulated Gate Field Effect Transistor

INWE Inverse Narrow Width Effect

LDD Lightly Doped Drain

LOCOS Localized-Oxidation-of-Silicon isolation

MOS Metal Oxide Semiconductor

NMOS N-type Metal Oxide Semiconductor

NWE Narrow Width Effect

PMOS P-type Metal Oxide Semiconductor

PSP Penn State Philips SPICE model

PSS Process-strained Silicon

RSCE Reverse Short Channel Effect

SCBE Substrate Current induced Body Effect

SCE Short Channel Effect

SD Source/drain

Si Silicon

SiO2 Silicon dioxide

SPICE Simulation Program with Integrated Circuit Emphasis

sqrt Square Root

SS Small Size

stdev Standard Deviation

STI Shallow Trench Isolation

TCAD Technology Computer Aided Design

TSMC Taiwan Semiconductor Manufacturing Company

XSIM National Technology University SPICE model

xxi
 PEMODELAN PADAT UNTUK TRANSISTOR CMOS DI BAWAH
SUBMIKRON DENGAN KESAN TEKANAN MEKANIKAL PENGASINGAN
PEPARIT CETEK

ABSTRAK

Thesis ini memperkenalkan satu model padat, dua model berasaskan empirikal

dan satu model berasaskan fizikal untuk kesan tekanan mekanikal Pengasingan

Peparit Cetek (STI) ke atas transistor CMOS di bawah submikron. Model tekanan-x

STI padat digunakan untuk menangkap tekanan dalam arah laluan transistor panjang.

Model ini adalah lebih ringkas berbanding dengan model tekanan STI BSIM4, tetapi

dapat mencapai ketepatan yang serupa. Dua ciri-ciri baru tekanan-x STI telah

dikenalpastikan. Ciri yang pertama adalah fakta bahawa kesan tekanan-x STI bagi

transistor CMOS berubah untuk transistor lebar yang berlainan. Kesan ini telah dikesan

dalam teknologi-teknologi 0.18 μm dan 0.13 μm. Satu model kesan tekanan-x STI

bergantung kepada lebar yang empirikal telah dicadangkan untuk menangkap kesan

ini. Ciri baru yang kedua adalah fakta bahawa kesan tekanan-x STI mengubah ciri-ciri

ketidaksamaan transistor CMOS. Satu model Monte Carlo yang empirikal telah

dicadangkan untuk menangkap kesan ini. Satu lengkuk arus parit tepu (Idsat)

berupabentuk cangkul berlawan dengan transistor lebar yang baru telah dikenalpasti.

Lengkuk ini tidak dapat dimodelkan dengan mengunakan model tekanan STI BSIM4.

Dengan mengunakan satu kaedah bentangan yang baru, ciri-ciri fizikal lengkuk ini

telah dikenalpasti. Lengkuk Idsat berupabentuk cangkul ini disebabkan oleh gabungan

kesan-kesan daripada tekanan-y STI (tekanan STI dalam arah laluan transistor lebar)

yang menurunkan Idsat dan kesan Perubahan Lebar (DW) yang meningkatkan Idsat.

Berdasarkan ciri-ciri fizikal ini, satu model tekanan-y STI yang fizikal diperkenalkan

untuk menangkap kelakuan Idsat berupabentuk cangkul ini. Ketepatan model-model

yang dicadangkan di dalam thesis ini dipastikan dengan mengunakan silikon data

benar yang difabrikasikan dengan mengunakan teknologi-teknologi CMOS Silterra 0.18

μm dan 0.13 μm yang berpiawaian industri. Model-model baru ini dibina dalam model

xxii
BSIM3v3 dengan mengunakan kaedah model makro (juga dikenali sebagai kaedah

sublitar). Dua parameter SPICE, parameter voltan ambang tiada pincang belakang,

Pvth0 dan parameter kelincahan pembawa, Pu0, telah digunakan untuk membina model-

model ini. Perbezaan masa simulasi antara model makro dan model konventional

adalah tidak ketara (< 5 %).

xxiii
 COMPACT MODELING OF DEEP SUBMICRON CMOS TRANSISTOR
WITH SHALLOW TRENCH ISOLATION MECHANICAL STRESS EFFECT

ABSTRACT

This thesis introduces a compact model, two empirical-based models and a

physical-based model of Shallow Trench Isolation (STI) mechanical stress effect on

deep submicron CMOS transistor. The compact STI x-stress model is used to capture

the stress effect in the channel length direction. This model is simpler than the BSIM4

STI stress model, but able to achieve the similar accuracy. Two new characteristics of

STI x-stress have been identified. The first characteristic is the fact that the STI x-

stress effect on CMOS transistor varies for different transistor channel widths. An

empirical width dependence of STI x-stress effect model has been proposed to capture

this effect. The second new characteristic is the fact that STI x-stress effect changes

the CMOS transistor mismatch characteristics. An empirical Monte Carlo model is

proposed to capture this effect. A new hook shaped saturation drain current, Idsat curve

versus channel width has been identified. This curve cannot be modeled using the

BSIM4 STI stress model. By using a new layout method, the physical characteristics of

the curve are identified. The hook shaped Idsat curve is caused by the combined effects

of STI y-stress (stress in the channel width direction) that degrades the Idsat and the

Delta Width (DW) effect that increases the Idsat. Based on the physical characteristics, a

new physical-based STI y-stress model is proposed to capture the hook shaped Idsat

behavior. The accuracy of the models in this thesis is verified on actual silicon data

fabricated using Silterra’s industry-standard 0.18 μm and 0.13 μm CMOS technologies.

These new models are incorporated into the BSIM3v3 model by using macro model

method (also known as subcircuit method). The two SPICE parameters, the zero back

bias threshold voltage parameter, Pvth0 and the carrier mobility parameter, Pu0, are used

for developing these models. The difference in simulation time between the macro

model and the conventional model is insignificant (< 5 %).

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 CHAPTER 1
INTRODUCTION

1.0 Chapter Overview

This chapter introduces the compact modeling works in this thesis. First, the

basic concept of compact modeling is introduced. Then, the history of compact

modeling of CMOS transistor which started with the theory Gradual Channel

Approximation (GCA) is reviewed. How the important deep submicron effects of CMOS

transistor are captured in BSIM3v3 equations are then discussed.

After reviewing the theoretical concept of compact modeling, the reasons why

this research focuses on SPICE modeling of the STI stress effect on CMOS transistor

is discussed. The background and objective of this research are then given. Finally, the

contribution of the proposed STI mechanical stress models to compact modeling

research is discussed.

1.1 Introduction to Compact Modeling

Compact model is basically a set of simplified physics equations that describe

the behaviors of semiconductor devices and able to run with SPICE simulator at

minimum time. Compact modeling is finding the parameter values for the compact

model equations to achieve a good fit between the simulation data and the measured

data. The main objective of the compact modeling is to enable the accurate prediction

of circuit performance before actual fabrication.

When transistor scaling goes to deep submicron, more and more significant

physical phenomena need to be captured by compact model. The physical phenomena

that are negligible in the CMOS micron technology have dominated the behavior of the

CMOS deep submicron technology.

Many researchers have put in much effort in establishing the set of equations

(Compact Model) that can provide the most accurate circuit simulation at the minimum

1
time. Berkeley Short-Channel IGFET models (BSIM3v3 and BSIM4 models) are

currently widely used by wafer fabrication foundries and IC design houses. Other

SPICE models such as PSP model, EKV model, HISIM model and XSIM model are

also popular. The standardization of these models is performed by an independent

organization called Compact Model Council (CMC).

All the modeling works in this thesis is based on BSIM3v3.24, where the final

released version is BSIM3v3.3 model (Cheng et al., 2005). In short, these BSIM3v3

family models, which built on similar source code, are known as BSIM3v3 model in this

thesis. The discussion in this thesis also references to BSIM4.3.0 (Xi et al., 2003) and

BSIM4.6.1 (Dunga et al., 2007) models for STI stress model discussion. In short, all the

BSIM4 family models are known as BSIM4 models in this thesis. The BSIM4 model is

built on a different source code compared to the BSIM3v3. Hence, the BSIM4 model is

not backward compatible to the BSIM3v3 model. The technology nodes of the

experimental transistors that are used in this thesis are 0.18 μm and 0.13 μm.

1.2 History of Compact Modeling

Compact modeling is originally driven by the need to express the CMOS

transistor behavior in quantitative form. Specifically, to design circuits with CMOS

transistors, how much current is carried in the “on” state of a transistor and how much

leakage current flows in the “off” state must be calculated. In short, the current-voltage,

I-V and capacitance-voltage, C-V characteristics of the CMOS transistor are needed,

specifically the quantitative relationship between the drain current and terminal

voltages.

In the beginning of the compact modeling era, there were four long-channel

CMOS transistor models proposed for DC circuit simulation (or calculation) as

explained in the reference book (Wolf, 1995). All the four models are based on the

long-channel Gradual Channel Approximation (GCA), which assumes that the variation

of the electric field in the x-direction (channel length, L direction) is much less than the

2
corresponding variation in the z-direction (perpendicular to channel plane direction).

The four models are Bulk-Charge model, Square-Law model, Pao-Sah model and

Charge-Sheet model.

Bulk-Charge model (Ihantola and Moll, 1964) and Square-Law model (simplified

version of Bulk-Charge model) are only valid if the CMOS transistor is operated in

strong inversion. This has limited the usage of these models.

Pao-Sah model (Pao and Sah, 1966) is the first model that able to cover the

entire range of CMOS transistor operation. This model retains the GCA but the drain

current, Id equation requires numerical integration in two dimensions. Such numerical

complexity has limited the role of this model for theoretical analysis of the CMOS

transistor.

The limited practical usage of the Pao-Sah model motivated a search for an

approximate advanced analytical model that is still accurate over a wider range of

operating conditions. Charge-Sheet model (Brews, 1978) has become the most widely

adopted long-channel CMOS model that is accurate in the inversion range.

Although the Charge-Sheet model allows Id to be calculated with much less

computational effort than that of the Pao-Sah model, the computational effort for

determining Id is still too great for most circuit simulation applications, and thus the

Charge-Sheet model has not been incorporated into the popular circuit simulation

engine, which is known as the SPICE simulator.

Since the Charge-Sheet model is too complex to be used in most circuit

simulation applications, an alternate analytical expression (simplified from the Charge-

Sheet model) is implemented to be used in subthreshold region. For the inversion

region, the simpler Bulk-Charge and Square-Law models are used. The combination of

these models enables the SPICE simulator to cover the entire range of CMOS

transistor operation with a reasonable simulation time.

When comparing the usage of the Bulk-Charge and Square-Law models, the

primary advantage of the Square-Law model is its simplicity. Most hand calculations for

3
circuit design with CMOS transistors make use of the Square-Law model. It is also the

model used for the simplest (Level 1) analysis of circuits in SPICE simulator. While the

more-accurate Level 2 SPICE for CMOS transistor is based on the Bulk-Charge model.

1.3 Compact Modeling of CMOS Transistor Deep Submicron Effects

This section discusses how SPICE model equations able to capture the CMOS

transistors deep submicron effects. BSIM3v3 modeling equations are selected for the

discussion in this section because the modeling equations are less complicated

compared to BSIM4 but sufficient to describe most of the CMOS transistor deep

submicron effects. One can easily catch up with BSIM4 or others SPICE models with

the basic understanding of BSIM3v3.

The electrical characteristics of a CMOS transistor are threshold voltage, Vt,

drain current, Id, off current, Ioff and substrate current, Isub. How the deep submicron

effects change the transistor electrical characteristics and how these effects can be

captured in BSIM3v3 equations is discussed. The following discussions in this section

are based on three SPICE modeling reference books (Taur and Ning, 1998, Cheng and

Hu, 1999, and Liu, 2001), and two BSIM manuals; BSIM3v3 manual (Cheng et al.,

2005) and BSIM4 manual (Dunga et al., 2007).

The physical phenomena of CMOS transistors that are discussed in this

section, are (1) Body effect, (2) Short Channel Vt Effect, SCE due to charge sharing,

(3) Reverse Short Channel Effect, RSCE due to lateral non-uniform doping, (4) Narrow

Width Effect, NWE, due to LOCOS isolation, (5) Inverse Narrow Width Effect, INWE

due to STI isolation, (6) Small Size effect, SS, (7) Drain Induced Barrier Lowering,

DIBL, (8) Channel Length Modulation, CLM, (9) Velocity Saturation, (10) Subthreshold

conduction, (11) Field dependent mobility, (12) Substrate Current induced Body Effect,

SCBE, (13) Gate Induced Drain Leakage, GIDL, (14) Polysilicon gate depletion effect,

(15) Velocity overshoot, (16) Source and drain resistance effect and (17) Effective

length and effective width effect.

4
 In BSIM3v3, there are six effects that change the threshold voltage, Vt as

shown in Equation 1.

⎛ ΔVt , body _ effect − ΔVt , sce + ΔVt , rsce + ΔVt , nwe ⎞

Vt = Pvth0 + δnp⎜⎜ ⎟⎟ (1)
⎝ + ΔV t , ss − Δ V t , dibl ⎠

where Pvth0 is the BSIM3v3 threshold voltage parameter of a long channel transistor at

zero back bias, Vb = 0 V. δnp is positive sign for NMOS and negative sign for PMOS.

The four effects that increase Vt are body effect, RSCE, NWE and SS. The other two

effects that decrease Vt are SCE and DIBL. These six effects on Vt are discussed in

the following sections.

The simple Square-Law form of Id equations (Brews, 1978) in linear region and

saturation region are shown in Equation 2 and Equation 3 below:

W ⎡ 1 2⎤
Id = μCox ⎢⎣(Vg − Vt )Vd − Vd Vd < Vdsat
2 ⎥⎦
when (2)
L

W ⎡ (Vg − Vt ) 2 ⎤
Id = μCox ⎢ ⎥ when Vd ≥ Vdsat (3)
L ⎣ 2 ⎦

where Vdsat = (Vg − Vt ) , μ is the carrier mobility, Cox is the gate oxide capacitance, W is

the channel width and L is the channel length.

Id modeling in BSIM3v3 equations is discussed based on seven effects. They

are bulk charge effect (Abulk), CLM, DIBL, field dependent carrier’s mobility, µ, SCBE,

velocity saturation and source drain resistance effect.

Ioff is modeled using Pvoff, which is the subthreshold offset voltage parameter.

Subthreshold conduction is calculated based on ideality factor, η, where Id is calculated

when Vg is below Vt. These effects are further discussed in the following sections.

Isub, which is caused by SCBE is model in BSIM3v3. The parameters that used

to model the Isub are actually Palpha0, Palpha1 and Pbeta0, but not Ppscbe1 and Ppscbe2

5
(although these last two parameters’ names have the term SCBE). SCBE is actually

caused by impact ionization that produces extra electrons that sweep into the drain that

increases Id and also produces extra holes that sweep into the substrate that increases

Isub. The increase of Id is modeled using Ppscbe1 and Ppscbe2 and the increase of Isub is

modeled using Palpha0, Palpha1 and Pbeta0.

1.3.1 Body effect and Bulk Charge Effect

The body effect refers to the effect of Vb on Vt. The body effect increases the Vt

of a CMOS transistor, when a reverse bias Vb is applied. Larger reverse Vb increases

the threshold voltage because the channel depletion layer becomes wider and hence

higher gate voltage, Vg is needed to invert the channel.

Body effect on Vt is modeled in BSIM3v3 by using Equation 4,

ΔVt , body _ effect = Pk1 ( )

2φ f − Vb − 2φ f − Pk2Vb (4)

where Pk1 is the first-order body effect parameter and Pk2 is the second-order body

effect parameter. Default values of Pk1 = 0.53 V1/2 and Pk2 = -0.0186. From Equation 4,

the more positive value of Pk1 and Pk2, the more significant the body effect is. φ f is the

difference between Fermi potential and the intrinsic potential of the substrate. 2φ f of a

substrate doping of 1e17 cm-3 is approximately 0.81 V.

The bulk charge effect is closely related to the body bias effect and refers to the

changing Vt along the channel when Vd > 0 V. Vt is not constant along the channel

because the width of the depletion region along the channel is not uniform in the

presence of a nonzero Vd, as shown in Figure 1.1.

6
 Figure 1.1: Non-uniform depletion width when Vd > 0 V (Cheng and Hu, 1999).

Body effect on Id, is modeled in BSIM3v3 by using Abulk, as shown in Equation 5.

⎡ ⎡ Pa0 Leff ⎤⎤
⎢ ⎢ ⎥⎥
⎢ ⎢ Leff + 2 Pxj Xdep ⎥⎥
⎢ ⎢⎛ 2 ⎥⎥
⎢ ⎢⎜ ⎛ ⎞ ⎞⎟⎥ ⎥
Pk1 ⎜ ⎟ ⎥
⎢⎜1 − Pags (Vg − Vt )⎜
Leff 1
Abulk = ⎢1 + ⎟ ⎥ (5)
⎢ 2 2φ f − Vb ⎟ 1 + PketaVb
⎢⎜
⎝ ⎝ Leff + 2 Pxj Xdep ⎠ ⎟⎠⎥ ⎥
⎢ ⎢ ⎥⎥
⎢ ⎢ Pb0 ⎥⎥
⎢ ⎢+ Weff + P ⎥⎥
⎣⎢ ⎢⎣ b1
⎦⎥ ⎦⎥

where Pa0 is the L dependence bulk charge parameter, Pags is gate bias dependence

bulk charge parameter, Pketa is body bias dependence bulk charge parameter, Pb0 is

channel width bulk charge parameter, Pb1 is channel width offset bulk charge

parameter. The default values of Pa0 = 1, Pags = 0, Pketa = -0.047 V-1, Pb0 = 0 m, Pb1 = 0

m. Pxj is source/drain junction depth parameter and Xdep is the channel depletion

thickness in the substrate. Weff is the effective channel width. The Weff is further

discussed in Section 1.3.17.

Equation 6 and Equation 7 show the Id equation with the term Abulk.

W ⎡ 1 ⎤
Id = μCox ⎢⎣ (V g − Vt )Vd − Abulk ⋅ Vd 2 ⎥ when Vd < Vdsat (6)
L 2 ⎦

7
 W ⎡ (V g − V t ) 2 ⎤
I d = μ C ox ⎢ ⎥ when Vd ≥ Vdsat (7)
L ⎣ 2 A bulk ⎦

(Vg − Vt )
where Vdsat =
Abulk

1.3.2 Short Channel Effect (SCE)

SCE is the decrease of transistor Vt as L is reduced, due to charge sharing. The

SCE is especially pronounced when Vd = Vdd (or at high drain bias). Figure 1.2(a)

shows the long channel depletion region, where the effect from the source and drain

can be ignored.

When L is decreased, there is more overlapping of the source and drain

depletion region to the channel. This results in electric field pattern in two-dimensional,

as shown in Figure 1.2(b). In other words, the depletion charge under the gate is

actually induced by the gate together with the source and drain. The channel charge is

considered to be “shared” by the gate, source and drain (Charge Sharing Model).

Hence, less gate charge density (smaller gate voltage) is needed to induce inversion in

short channel transistors than in long channel transistors. This means the gate voltage,

Vg required to turn on the transistor become smaller as the L is reduced.

Figure 1.2: Charge regions: (a) in long channel; (b) in short channel (Liu, 2001).

8
 SCE effect on Vt is model in BSIM3v3 by using the Equation 8,

⎡ ⎛⎜⎜ − Pdvt1 Leff ⎞⎟⎟ ⎜⎜ − Pdvt1 eff ⎟⎟ ⎤

⎛ L ⎞

ΔVt , sce = Pdvt0 ⎢e⎝ + 2e⎝ ⎥(Vbi − 2φ f )

2 Lt ⎠ Lt ⎠

⎢ ⎥ (8)
⎣ ⎦

ε s Xdep
where Lt = (1 + Pdvt2Vb ) and
Cox
Pdvt0 is the first SCE parameter, Pdvt1 is the L dependence exponent SCE parameter

and Pdvt2 is the body bias SCE parameter. The default value of Pdvt0 = 2.2, Pdvt1 = 0.53

and Pdvt2 = -0.032 V-1. Leff is the effective channel length. The Leff is further discussed in

Section 1.3.17. Vbi is the built-in voltage of the source-bulk/drain-bulk junction and εs is

the silicon permittivity.

1.3.3 Reverse Short Channel Effect (RSCE)

RSCE causes the Vt to increase as L decreases. This is caused by the non-

uniform lateral doping effect, due to pocket implantation, as shown in Figure 1.3. The

channel doping concentration near the source and drain is higher than in the middle of

the channel. The increased doping concentration in the two ends of the channel can

result in an increase in Vt as the channel becomes shorter. The combined RSCE and

SCE effects result in a ‘hump’ in the characteristics of Vt versus L, as shown in Figure

1.4.

RSCE effect on Vt is modeled in BSIM3v3 by using the Equation 9.

⎛ P ⎞
ΔVt , rsce = Pk1 ⎜⎜ 1 + nlx − 1⎟⎟ 2φ f (9)
⎝ Leff ⎠

9
where Pnlx is the RSCE parameter and Leff is the effective channel length. The default

value of Pnlx = 1.74 x 10-7 m. RSCE increases the Vt of short channel transistors and

has negligible effect on Vt of long channel transistors.

Figure 1.3: Lateral doping profile with pocket implantation (Cheng and Hu, 1999).

Figure 1.4: Vt versus L characteristics of a transistor with RSCE (Cheng and Hu, 1999).

10
1.3.4 Narrow Width Effect (NWE)

NWE happens when the Localized-oxidation-of-silicon (LOCOS) isolation

technology is used. Figure 1.5 shows the transistor cross-section in the channel width,

W direction with LOCOS isolation. Both ends of the gate oxide (in W direction) are

known as “bird beak” due to their shape. The “bird beak” shape causes thicker gate

oxide at the edge and hence results in higher Vt. As W reduces the “bird beak” effect

becomes more severe. This increases the overall Vt.

Figure 1.5: CMOS transistor with LOCOS isolation technology (Liu, 2001).

Also the fringing field from the gate that terminates at bulk charges outside the

intrinsic portion of the transistor (as defined by Weff), as shown in Figure 1.5, also

causes higher Vt. This is because it takes a larger gate voltage to deplete the extra bulk

charges before an inversion layer can be formed.

NWE effect on Vt is modeled in BSIM3v3 by using Equation 10,

ΔVt , nwe = (Pk 3 + Pk 3bVb )

Ptox
2φ f (10)
Weff + Pw0

where Pk3 is the NWE parameter, Pk3b is the body effect NWE parameter, Ptox is the

oxide thickness parameter, Pw0 is the channel width offset NWE parameter and Weff is

11
the effective channel width. The default value of Pk3 = 80, Pk3b = 0 and Pw0 = 2.5 x 10-6

m.

NWE only happens when LOCOS isolation is used. From quarter micron

technology and below, the LOCOS isolation has been replaced by STI. STI process

causes the opposite effect on Vt, which is known as INWE. Hence, Pk3 should be set to

a smaller value, such as 0.001 to make this term negligible in the final Vt calculation.

Unfortunately, the INWE that decreases Vt for narrow width transistors is not captured

in either BSIM3v3 or BSIM4.

1.3.5 Inverse Narrow Width Effect (INWE)

INWE causes the Vt to decrease as W decreases. INWE happens when STI

technology is used. The STI profile causes thinner gate oxide at the edge of the

channel and hence smaller Vt, as shown in Figure 1.6. When W reduces, the thinner

gate oxide at the edge of the channel causes the entire channel to have lower Vt.

The field lines from the gate electrode that are focused by the sharp geometry

of the channel edge also lower the Vt. This is because at the edges of the channel, an

inversion layer is formed at a lower voltage than at the center. As a result, the average

Vt of the channel is lower in the transistors with smaller W. As mentioned in the

previous section, INWE is not modeled in both BSIM3v3 and BSIM4. Therefore,

binning or global binning approach must be used.

Figure 1.6: CMOS transistor with STI isolation technology.

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1.3.6 Small Size Effect (SS) on Threshold Voltage

SS in CMOS transistors is basically similar to the SCE. Instead of decrease in

the transistor Vt as L is reduced from SCE, the SS correct the short channel Vt for

narrow width transistor by increasing the Vt.

SS on Vt is modeled in BSIM3v3 by using Equation 11,

⎡ ⎛⎜⎜ − Pdvt1w Weff Leff ⎞⎟⎟ ⎜⎜ − Pdvt1w eff eff ⎟⎟ ⎤

⎛ W L ⎞

ΔVt , ss = Pdvt0w ⎢e⎝ + 2e⎝ ⎥ (Vbi − 2φ f )

2 Ltw ⎠ Ltw ⎠

⎢ ⎥ (11)
⎣ ⎦

ε s X dep
where Ltw = (1 + Pdvt2wVb ) and
Cox

Pdvt0w is the first SS parameter, Pdvt1w is the L dependence exponent SS parameter and

Pdvt2w is the body bias SS parameter. The default value of Pdvt0w = 0, Pdvt1w = 5.3e6 m-1

and Pdvt2w = -0.032 V-1.

1.3.7 Drain Induced Barrier Lowering (DIBL)

The potential barrier at the surface between the source and drain for NMOS

transistor is shown in Figure 1.7. Under off conditions, the potential barrier in the p-type

region prevents electron from flowing to the drain. The surface potential is mainly

controlled by the Vg.

When the Vg is below Vt, there are only a limited number of electrons injected

from the source over the barrier and flow into the drain. This is called subthreshold

current. In the long channel case, the potential barrier is flat over most of the transistor

because the source and drain fields only affect the very ends of the channel.

As L become shorter, the source and drain fields penetrate deeply into the

middle of the channel, which lowers the potential barrier between source and drain.

This causes a substantial increase of the subthreshold current. In other words, the Vt

13
becomes lower than that of the long channel value. The region of maximum potential

barrier also shrinks to a single point near the center of the transistor.

When a high Vd is applied to a short channel transistor, the barrier height is

lowered even more, resulting in further Vt decrease. The maximum point of the barrier

also shifts toward the source end as shown in Figure 1.7. This effect is referred to as

DIBL. It explains the experimentally observed increase of subthreshold current with Vd

in short channel transistors.

The conduction band profile of the DIBL effect on short channel transistor is

shown in Figure 1.8. The electrons in the source region, which is at lower potential flow

to the drain region (at higher potential) after overcoming the gate controlled barrier.

Large Vd lowers the barrier and thus less gate voltage is needed to provide the

electrons enough energy to overcome the barrier and flow to the drain region.

Figure 1.7: Surface potential versus L for (a) long channel transistor (b) short channel

transistor, and (c) short channel transistor at high Vd (Taur and Ning, 1998).

14
 Figure 1.8: Conduction band profile showing DIBL effect in short channel transistor

(Yeo, 2005).

DIBL effect on Vt is modeled in BSIM3v3 by using Equation 12,

⎡ ⎛⎜⎜ − Pdsub Leff ⎞⎟⎟ ⎜⎜ − Pdsub eff ⎟⎟ ⎤

⎛ L ⎞

ΔVt , dibl = ⎢e⎝

2 Lt0 ⎠
+ 2e⎝
Lt0 ⎠
⎥(Peta0 + PetabVb )Vd
⎢ ⎥ (12)
⎣ ⎦

ε s Xdep,0
where Lt0 = and
Cox
Pdsub is the Vt L dependence exponent DIBL parameter, Peta0 is the Vt DIBL parameter

and Petab is the Vt body bias DIBL parameter. The default value of Pdsub = 0.56, Peta0 =

0.08 and Petab = -0.07 V-1. Xdep,0 is the depletion thickness in the substrate at zero bulk

bias.

15
1.3.8 Channel Length Modulation (CLM)

The saturation of Id, Idsat can be understood from the inversion charge density.

When Vd is small (linear region), the inversion charge density at the drain end of the

channel is only slightly lower than the source end, as shown in Figure 1.9(a).

As the Vd increases (for a fixed Vg), the Id increases, but the inversion charge

density at the drain decreases until finally it goes to zero when Vd = Vdsat = Vg – Vt. At

this voltage, Id reaches its maximum value. In other words, the surface channel

vanishes at the drain end of the channel when saturation occurs. This is called pinch-

off (indicated by Y) and is illustrated in Figure 1.9(b). This is a simplified diagram.

When Vd increases beyond the saturation, the pinch-off point moves toward the

source, but the Id remains essentially the same. This is because for Vd > Vdsat, the

voltage at the pinch-off point remains at Vdsat and the current stays the same apart from

a slight decrease in L (to L’), as shown in Figure 1.9(c). This phenomenon is called

Channel Length Modulation (CLM) that makes the channel look as if it is shorter.

Since Id increases when L reduces, the CLM increases the Idsat. This effect can

be seen from the plots of Id-Vd curves. CLM and DIBL effect on Id is modeled in

BSIM3v3 by using Early Voltage, Va as shown in Equation 13,

⎛ Vd − Vdsat ⎞
Id = Id,0⎜1 + ⎟ (13)
⎝ Va ⎠

where Va = Va , sat + Va , clm _ dibl .

Id,0 is the ideal long channel Id as discussed in Equation 3. Early Voltage, Va is a

variable that adjusts the slope of the variation of Id with respect to Vd. Graphically, can

be taken to be value on the –x axis for which the current extrapolates to 0 A, as shown

in Figure 1.10.

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Figure 1.9: CMOS transistor operates in; (a) linear region, (b) onset of saturation,

(c) beyond saturation where CLM occurs (Taur and Ning, 1998).

17
 Figure 1.10: Id-Vd curves with Vg,2 > Vg,1, showing the relationship between Va and the

slope of Id in saturation (Liu, 2001).

Va,sat and Va,clm_dibl equations are shown in the following Equation 14 and

Equation 15:

Va , sat = f 0(Leff , Pvsat , Rds,...) (14)

μeff
1 + Ppvag (Vg − Vt )
2 Pvsat Leff
Va , clm _ dibl =
Ppclm f1 + θrout (1 + PpdiblcbVb ) f 2 (15)

⎡ ⎛⎜⎜ − Pdrout Leff ⎞⎟⎟ ⎜⎜ − Pdrout eff ⎟⎟ ⎤

⎛ L ⎞

θ rout = Ppdiblc1 ⎢e⎝ + 2e⎝ ⎥ + Ppdiblc2

2 Lt0 ⎠ Lt0 ⎠
where ⎢ ⎥
⎣ ⎦
ε s Xdep,0
and Lt0 =
Cox

f0, f1 and f2 represent complicated functions and other variables that are covered in this

discussion. Ppvag is gate bias dependence Va parameter, Pvsat is carrier saturation

velocity parameter. Ppclm is channel length modulation parameter, Ppdiblc1 is first DIBL

correction on Va parameter, Ppdiblc2 is the second DIBL correction on Va parameter,

Ppdiblcb is the body bias DIBL correction on Va parameter. The default value of Ppvag = 0,

Pvsat = 8 x104 ms-1, Ppclm = 1.3, Ppdiblc1 = 0.39, Ppdiblc2 = 0.0086 and Ppdiblcb = 0.39.

18
1.3.9 Velocity Saturation

Carrier velocity saturation is another important parameter that affects the

characteristics of short channel transistors. In long channel transistors, the Idsat is

explained by the concept of channel pinch-off. For short channel transistors, the Idsat is

explained by velocity saturation.

When the Vd increases in a long channel transistor, the Id first increases, and

then becomes saturated at a voltage with the onset of pinch-off at the drain. In a short

channel transistor, the Idsat occurs at a much lower voltage due to velocity saturation, as

shown in the Id-Vd curves in Figure 1.11. This is because at high (horizontal) field

strength, the velocity of the carriers tends to saturate due to scattering effects

(collisions suffered by the carriers). The transistor W/L is 9.5 μm/0.25 μm.

This velocity saturation effect is modeled in BSIM3v3 using Pvsat parameter.

This parameter when used in NMOS, denotes the electron saturation velocity and

when used in PMOS, denotes the hole saturation velocity. Therefore, Pvsat in NMOS

should be slightly larger than the Pvsat in PMOS. Pvsat is a critical parameter determining

the transistor current in short channel transistors, but has negligible impact on long

channel transistors.

This agrees with the physical effects that in long channel transistors, the electric

field parallel to the current conduction is small and the electron drift velocity is roughly

equal to the mobility times the field. The drift velocity never reaches a magnitude

comparable to Pvsat. In short channel transistors, in contrast, the field is large enough

such that the carriers travel at the saturation velocity in a sizable portion of the channel.

Pvsat also affects Va, as shown in Equation 15 (in the previous section).

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Figure 1.11: Id-Vd characteristics with velocity saturation, solid lines and as if there were

no velocity saturation, dashed lines (Taur and Ning, 1998).

1.3.10 Subthreshold Conduction

The subthreshold conduction in Figure 1.12 shows the transition of a CMOS

transistor state from “on” to “off”. In an ideal case, the subthreshold slope should be

infinity. Typical subthreshold slope is about 80 to 100 mV/dec.

When the subthreshold slope is degraded, this usually means that the transistor

is harder to turn “off” because the gate loses control over the channel surface potential.

The subthreshold slope degradation also reduces the Vt and causes higher Ioff.

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 Figure 1.12: Subthreshold characteristics of short and long channel transistors at low

and high Vd (Taur and Ning, 1998).

Subthreshold conduction effect on Id at off condition (Vg < Vt), Ioff is modeled in

BSIM3v3 by using Equation 16,

2 ⎛ qVt ⎞ ⎛ qPvoff ⎞
⎜− ⎟
W ⎛ kT ⎞ ⎜⎜ −
⎝ ηkT
⎟⎟ ⎜ ηkT ⎟
Ioff = μCox ⎜ ⎟ e ⎠
e ⎝ ⎠
L ⎜⎝ q ⎟⎠ (16)

where Pvoff is the subthreshold offset voltage parameter. The default value of Pvoff =

-0.08 V. q is the single electron charge (1.6e-19 C). From Equation 16, Ioff is

proportional to ideality factor, η (Equation 17),

⎛ qV g ⎞
⎜⎜ ⎟⎟
⎝ η kT
Ioff ∝ e ⎠
(17)

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The ideality factor, η is given in Equation 18,

⎛ Cdep ⎞ Pcit
η = 1 + ⎜ Pnfactor ⎟+ +
⎝ Cox ⎠ Cox
⎡ ⎛ ⎛ L ⎞
⎜⎜ − Pdvt1 eff ⎟⎟ ⎞ ⎤
⎛ L ⎞

⎢⎛⎜ Pcdsc + PcdscdVd + PcdscbVb ⎞⎟⎜ e⎝

⎜⎜ − Pdvt1 eff ⎟⎟
Lt ⎠ ⎟
2 Lt ⎠
+ 2e ⎝ ⎥ (18)
⎢⎝ Cox ⎠⎜ ⎟ ⎥
⎣ ⎝ ⎠ ⎦

ε s Xdep
where Lt = (1 + Pdvt2Vb ) and
Cox

Pnfactor is subthreshold turn-on swing parameter, Pcit is the interface trap capacitance

parameter (this parameter is purely a DC parameter which does not affect the C-V

characteristics of the transistor), Pcdsc is drain and source to channel coupling

capacitance parameter (a pure DC parameter), Pcdscd is drain bias sensitivity of Pcdsc

parameter (a pure DC parameter), Pcdscb is body bias sensitivity of Pcdsc parameter (a

pure DC parameter). The default value of Pnfactor = 1, Pcit = 0 Fm-2, Pcdsc = 2.4e-4 Fm-2,

Pcdscd = 0 FV-1m-2 and Pcdscb = 0 FV-1m-2. Cdep is the depletion capacitance per unit area

in the bulk.

The last term is similar to the one used in SCE for Vt calculation. It is meant for

the short channel transistors. Usually to model the subthreshold current, Pnfactor and

Pvoff are used. Other parameters can set to their default values, rule of thumb is the

ideality factor, η should be close to "1".

1.3.11 Field Dependent Mobility

Mobility is a key parameter in transistor modeling. It is a measure of the ease of

carrier motion in semiconductor materials. Carrier transport in a MOS transistor mainly

takes place along the interface between silicon, Si and silicon dioxide, SiO2. The carrier

mobility at the interface is lower than in the bulk and depends on both vertical and

horizontal electric field.

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 In the early years of CMOS, the gate oxide was thick, and the vertical electric

field induced by the gate bias was low and hence the influence of the vertical electric

field could be ignored. But in today’s short channel transistors, oxide thicknesses are

very thin, for example in 0.13 μm technology the oxide thickness is about 2 nm. Thus,

the influence of the vertical electric field is strong and the carrier mobility is not constant

as the gate bias changes.

Three scattering mechanisms have been proposed to account for the

dependence of mobility on the vertical component of the electric field. They are phonon

scattering, coulomb scattering and surface roughness scattering. Each scattering

mechanism is dominant under some specific conditions of the doping concentration,

temperature and bias. For good quality interfaces, phonon scattering is generally the

dominant scattering mechanism at room temperature, as shown in Figure 1.13.

Figure 1.13: Mobility versus Vertical Effective Field to illustrate how the mobility

behavior is dominated by different scattering mechanisms (Cheng and Hu, 1999).

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 In BSIM3v3, the effective carrier mobility, μeff, of mobility mode parameter,

Pmobmod = 1, is given in Equation 19,

Pu0
μeff = 2 (19)
⎛ Vg + Vt ⎞ ⎛ Vg + Vt ⎞
1 + (Pua + PucVb )⎜⎜ ⎟⎟ + Pub ⎜⎜ ⎟⎟
⎝ tox ⎠
P ⎝ tox ⎠
P

where Pu0 is the zero field universal mobility parameter, Pua is the first order mobility

degradation parameter, Pub is the parabolic mobility degradation parameter and Puc is

the body bias mobility degradation parameter. The default value of Pu0 = 0.067 m2V-1s-1

(NMOS) and 0.025 m2V-1s-1 (PMOS), Pua = 2.25 x 10-9 mV-1, Pub = 5.87 x 10-19 m2V-2

and Puc = -4.65 x 10-11 mV-2.

1.3.12 Substrate Current induced Body Effect (SCBE)

At saturation mode, the high electric field near the drain region causes impact

ionization of carriers. For NMOS transistor, the generated electrons are swept into the

drain whereas the holes flow into the substrate. This phenomenon is known as SCBE.

SCBE results in Id increase that is many times larger than Isub, as shown in Figure 1.14.

Figure 1.14: Id-Vd characteristics due to SCBE (Cheng and Hu, 1999).

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