TM

R E A L W O R L D S I G N A L P R O C E S S I N G

Clocks and Timing Selection Guide

4Q 2003
Table of Contents
Overview
Clock Distribution Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Signal-Level Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Clock Selection by Speed and Signaling Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Clock Selection by Number of Outputs and Signaling Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Clock Buffers/Drivers (Non-PLL)

Featured Product
CDCM1804—Differential and Single-Ended Output in One Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

PLL Clock Buffers (Zero-Delay)

Featured Products
CDCFR83/CDCR61A — 533-MHz Direct RambusTM Clock Generator with Phase Aligner and
400-MHz without Phase Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
CDCVF857/CDCV857B — 2.5-V Phase Lock Loop Clock Drivers for Speeds up to DDR400 . . . . . . . . .8
CDCU877 — 1.8-V Phase Lock Loop Clock Driver for DDR II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Advanced PLL-Based Synthesizers

Featured Products
CDC7005 — Low Phase Noise Clock Synthesizer with Multiplying, Dividing and Jitter Cleaning . . . .10
CDCF5801 — Low-Jitter Clock Multiplier/Divider with Programmable Delay and Phase Alignment . .12
CDCVF25084 — 3.3-V 1:8 Zero Delay (PLL) x4 Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Real-Time Clocks (RTCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Resources
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
For More Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Introduction Applications Support

Texas Instruments (TI) offers a wide selection of
timing support devices, from non-PLL-based buffers
to high-performance PLL clock synchronizers.
Included in the TI clock family are zero-delay PLL
clock drivers and a series of PLL-based multipliers
and dividers designed to help manage clock jitter and
skew for a variety of standard signal levels. In addi-
tion, many of the PLL devices are spread spectrum
clock (SSC) compatible. There is also a selection of
clock drivers for memory applications.
Do you need help selecting the timing devices for
your board designs? Are you concerned about jitter,
skew, zero-delay and other parameters affecting your
timing budget? The TI technical application support
team will work with you on TI’s clock and timer
products and provide solution options for your board-
level concerns. To get answers to your technical
questions, contact your nearest TI Product Information
Center listed at the end of this guide or select from
the TI Worldwide options at: www.ti.com/clocks

2 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Overview

Clock Distribution Circuits

Clock Buffers PLL Clock Buffers Advanced PLL-Based

(Non-PLL) (Zero-Delay) Synthesizers
Pages 6-7 Pages 8-9 Pages 10-12

Differential x1 PLL-Based Multipliers/

LVPECL/LVDS/ Buffers Dividers
MLVDS

Single-Ended Double Data Jitter

LVTTL/CMOS Rate (DDR) Cleaners

Crosspoint Direct PC
Switches RambusTM Synthesizers

Mixed-Signal Buffers
LVTTL + LVPECL

Real-Time Clocks (RTCs)

Modules
Integrated
(Includes Battery
Circuits
and Crystal)
Pages 13-14
Pages 13-14

For more information, visit:

www.ti.com/clocks

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 3

Overview (Continued)

Clock Distribution Circuits
Clock Buffers/Drivers (Non-PLL) — TI
offers both single-ended and differential
clock buffers that perform from below
200 MHz up to 3.5 GHz in a variety of
fan-out options. In addition to simple
buffering, TI also offers a mixed-signal
option for customers needing differential
signals (LVPECL) and single-ended signals
(LVTTL/LVCMOS) from the same device.
Zero-Delay PLL Clock Buffers — TI
offers zero-delay buffers that target the
latest memory standards (DDR400,
DDR-2 for example) as well as buffers
that provide single-ended PLL functions
for general-purpose applications.
Advanced PLL-Based Synthesizers —
The advanced PLL family consists of
devices that assist with high-performance
requirements such as cleaning the jitter
from a noisy clock source (CDC7005) or
providing phase adjustment (CDC5801).
TI also offers low-jitter (<1-ps phase
noise) multiplying and dividing functions
in this category.

Signal-Level Comparisons

2.5-V CMOS Traditional CMOS LVTTL/LVCMOS 5-V TTL

3.3 V

VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V

2.0 V
VOH = 1.8 V VIH = VIH = 2.0 V VIH = 2.0 V
VIH = 0.7 × VDD
0.7 × VDD VIL = VIL = 0.8 V VIL = 0.8 V
1.0 V VIL = 0.2 × VDD
0.2 × VDD VOL = 0.6 V
VOL = 0.5 V/ VOL = 0.5 V/
VOL = 0.4 V 0.55 V
0.55 V
0V

1.5-V HSTL 2.5-V SSTL-2 2.5-V/3.3-V LVDS 3.3-V LVPECL

3.3 V

VOH =
VIH = 2.275 V
VREF = VOH = 2.135 V
1.25 V 1.82 V VX = VOH =
2.0 V VREF = VIH = 1.475 V 310 mV 600 mV
VOH = 1.2 V
0.75 V VREF + 0.35 V
VIH = 1.10 V 2.4 V VIL = VOL =
VREF – 0.20 V 1100 mV 250 to 1.825 V 1.68 V
1.25 V 700 mV VCM =
200 mV 450 mV
0.75 V 700 mV 2.0 V
400 mV VIL = 0V
VREF – 0.35 V VOL = VOL =
VIL = 0.68 V
0V 0.925 V
VREF – 0.20 V VOL =
0.4 V

Signal-Level Definitions
VREF = Input Reference Voltage
VOH = High Output Voltage
VIH = High Input Voltage
VID = Differential VOD = Differential
Input Voltage Output Voltage
VIL = Low Input Voltage
VOL = Low Output Voltage

4 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Overview (Continued)

Clock Selection by Speed and Signaling Type

Signal Type

CDCU877
SSTL-2/RSL CDCV857B
CDCV850 CDCV855 CDCR61A CDCFR83
(DDR/Rambus®) CDCVF857
CDCR83

CDCLVD110
SN65LVDS116
SN65LVDS117 CDCM1804
LVPECL/LVDS CDCP1803
SN65LVDS104
MLVDS/CML SN65MLVD201 SN65LVDS100
SN65LVDS105
SN65CML100 SN65LVDS101
SN65LVDS108
SN65LVDS109 CDCVF111 CDC7005 CDCLVP110
CDC5801
CDC2536
CDC2582 CDC509
CDC2586 CDC516 CDCVF2509 CDCVF2505
CDCVF2510 CDCVF25081
CDC536 CDC2509
CDC582 CDC2510
LVTTL/HCMOS CDC586 CDC2516
CDCV304 CDCVF25084 CDCVF2310
CDC351
CDC2351 CDC950
CDC960
CDC318A
Clock Buffers/Drivers (Non-PLL)—Pages 6-7
CDC319
PLL Clock Buffers (Zero-Delay)—Pages 8-9
CDC329A Advanced PLL-Based Synthesizers—Pages 10-12
CDC337
CMOS/TTL CDC339 CDC328A
CDC340 CDC391
CDC341

80 100 125 140 175 200 300 400 500 533 750 800 900 1 – 3.5 GHz
Maximum Speed (MHz)

Clock Selection by Number of Outputs and Signaling Type

Signal Type

CDCV850
CDCR61A CDCV857B
SSTL-2/RSL CDCR83 CDCV855
(DDR/Rambus®) CDCVF857B
CDCFR83 CDCU877

CDC5801 SN65LVDS104 SN65LVDS108

SN65LVDS109 CDCLVD110
SN65LVDS100 CDC7005 SN65LVDS116
SN65LVDS101 CDCVF111 SN65LVDS117
LVPECL/LVDS SN65CML100 SN65LVDS105
MLVDS/CML SN65MLVD201 CDCLVP110
CDCP1803
3-LVPECL
CDCM1804
3-LVPECL
1-LVTTL CDC2510C
CDCVF25081 CDCVF2510
CDC582 CDC516 CDC318A
CDC536 CDC509 CDC2582 CDC2516
LVTTL/HCMOS CDCV304 CDCVF2505 CDC2351
CDC2536 CDC2509C CDC586
CDCVF2509 CDC351 CDC2586
CDCVF2310
CDCVF25084 CDC319

CDC208 Clock Buffers/Drivers (Non-PLL)—Pages 6-7

CDC328A CDC337 PLL Clock Buffers (Zero-Delay)—Pages 8-9
CMOS/TTL CDC208 CDC329A CDC339
CDC391 CDC340 Advanced PLL-Based Synthesizers—Pages 10-12
CDC341

1 4 5 6 8 9 10 12 16 18
Number of Outputs

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 5

Clock Buffers/Drivers (Non-PLL)
• VCC range 3.0 to 3.6 V • Receiver input threshold ±75 mV
Non-PLL-based buffers will add a delay
• Signaling rate up to 800 MHz for • 24-pin MLF package (4 mm x 4 mm)
(skew) from the input to the output.
LVPECL and 200 MHz for LVCMOS
An advantage for buffers is they add a Get samples, datasheets and app.
• Differential input stage for very wide
very low amount of jitter, very often reports at:
common-mode range also provides VBB
less than 1 ps (rms). www.ti.com/sc/device/CDCM1804
bias-voltage output for single-ended
input signals
Featured Product
CDCM1804 — Differential and CDCM1804 Functional Diagram
Single-Ended Output in One Buffer
The CDCM1804 clock driver distributes
one pair of differential clock inputs to three IN Y0
pairs of LVPECL differential clock outputs
LVPECL
Y[2:0] and /Y[2:0] with minimum skew for
IN Y0
clock distribution. It is specifically designed
for driving 50-Ω transmission lines.
Additionally, the CDCM1804 offers a
single-ended LVCMOS output Y3. This
output is delayed by 1 ns over the three
PECL output stages to minimize noise CMOS Y3
Div 1
impact during signal transitions.
Div 2
Key Features Div 4
• Distributes one differential clock input Div 8
Div 16 Y1
to three LVPECL differential clock out-
puts and one LVCMOS single-ended LVPECL
output Y1
• Programmable output divider for two
LVPECL outputs and one LVCMOS
output Y2
Bias
• Low-output 20-ps (typical) skew for clock Generator LVPECL
distribution applications for LVEPCL VBB VDD – 1.3 V Y2
outputs; 1-ns output skew between (IMAX < 1.5 mA)
LVCMOS and LVPECL transitions,
minimizing noise
S1
Control EN
S0

For more information, visit:

www.ti.com/clocks

6 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Clock Buffers/Drivers (Non-PLL) Selection Guide
Char.
Input Output VCC Propagation Output Temp.
Device Description Level Level Frequency (V) Delay Skew (°C) # Pins/Pkg Price1
Differential Clocking
CDCP18032 1:3 buffer with dividers LVPECL LVPECL 0 to 800 MHz 3.3 TBA TBA –40 to 85 24/MLF See
Web
CDCLVP110 1:10 LVPECL/HSTL with selectable LVPECL/ LVPECL 0 to 3.5 GHz 2.5/3.3 230 to 370 ps 30 ps –40 to 85 32/LQFP 5.25
input clock HSTL 5.60
CDCLVD110 1:10 programmable LVDS clock LVDS LVDS 0 to 900 MHz 2.5 3 ns (max) 30 ps (typ) –40 to 85 32/TQFP 7.00
CDCVF111 1:9 diff LVPECL clock LVPECL LVPECL 0 to 650 MHz 3.3 450 to 600 ps 50 ps 0 to 70 28/PLCC 7.70
SN65LVDS100 1:1 buffer LVDS LVDS 1 GHz 3.3 200 to 800 ps — –40 to 85 8/SOIC/MSOP 2.52
SN65LVDS101 1:1 buffer LVDS LVPECL 1 GHz 3.3 400 to 900 ps — –40 to 85 8/SOIC/MSOP 2.52
SN65LVDS104 1:4 buffer LVDS LVDS 315 MHz 3.3 2.2 to 4.2 ns 100 ps –40 to 85 16/SOIC 2.22
SN65LVDS105 1:4 buffer LVTTL LVDS 315 MHz 3.3 1.4 to 3.5 ns 100 ps –40 to 85 16/SOIC 2.22
SN65LVDS108 1:8 buffer LVDS LVDS 311 MHz 3.3 1.6 to 4.5 ns 300 ps –40 to 85 38/TSSOP 4.00
SN65LVDS109 Dual 1:4 buffer LVDS LVDS 311 MHz 3.3 1.6 to 4.5 ns 550 ps –40 to 85 38/TSSOP 4.00
SN65LVDS116 1:16 buffer LVDS LVDS 311 MHz 3.3 2.2 to 4.7 ns 300 ps –40 to 85 64/TSSOP 5.97
SN65LVDS117 Dual 1:8 buffer LVDS LVDS 311 MHz 3.3 1.6 to 4.5 ns 550 ps –40 to 85 64/TSSOP 5.97
SN65CML100 1:1 buffer LVDS CML 750 MHz 3.3 250 to 800 ps — –40 to 85 8/SOIC/MSOP 2.52
SN65MLVD201 1:1 driver and receiver LVTTL/ MLVDS/ 100 MHz 3.3 1 to 2.4 ns — –40 to 85 8/SOIC 2.10
MLVDS LVTTL
Single-Ended
CDC208 Dual 1:4 fanout, 3-state outputs TTL CMOS 0 to 60 MHz 5 6.6 to 10.2 ns 1 ns –40 to 85 20/SOIC 3.89
CDC318A 1:18 clock with I2C control interface LVTTL LVTTL 0 to 100 MHz 3.3 1.2 to 4.5 ns 250 ps 0 to 70 48/SSOP 1.38
CDC319 1:10 clock with I2C control interface LVTTL LVTTL 0 to 140 MHz 3.3 1.2 to 3.6 ns 250 ps 0 to 70 28/SSOP 1.41
CDC328A 1:6 fanout with selectable polarity TTL TTL 0 to 100 MHz 5 1.5 to 5.0 ns 500 ps –40 to 85 16/SOIC/SSOP 3.36
CDC329A 1:6 fanout with selectable polarity TTL CMOS 0 to 80 MHz 5 1.7 to 5.9 ns 600 ps –40 to 85 16/SOIC 2.80
CDC337 1:8 clock with four 1x outputs, TTL CMOS 0 to 80 MHz 5 4 to 9 ns 900 ps –40 to 85 20/SOIC 3.96
four 1/2x outputs, 3-state outputs
CDC339 1:8 clock with four 1x outputs, TTL CMOS 0 to 80 MHz 5 3 to 9 ns 900 ps –40 to 85 20/SOIC/SSOP 3.30
four 1/2x outputs, 3-state outputs
CDC340 1:8 with fast tpd fanout TTL TTL/CMOS 0 to 80 MHz 5 2.8 to 4.8 ns 600 ps 0 to 70 20/SOIC 3.96
CDC341 1:8 with fast tpd fanout TTL TTL/CMOS 0 to 80 MHz 5 3.1 to 4.9 ns 600 ps 0 to 70 20/SOIC 4.05
CDC351 1:10 with fast tpd fanout, LVTTL LVTTL/ 0 to 100 MHz 3.3 3 to 4 ns 500 ps 0 to 70 24/SOIC/SSOP 5.36
3-state outputs LVCMOS
CDC391 1:6 clock with selectable polarity TTL TTL 0 to 100 MHz 5 1.5 to 5.0 ns 500 ps –40 to 85 16/SOIC 3.24
and 3-state outputs
CDCV304 1:4 fanout for PCI-X and LVTTL LVCMOS 0 to 140 MHz 3.3 1.8 to 3.0 ns 100 ps –40 to 85 8/TSSOP 1.05
general apps
CDCVF23103 1:10 clock with 2 banks for LVTTL/ LVTTL/ 0 to 170 MHz 2.5/3.3 1.3 to 2.8 ns 100 ps @ 3.3 V –40 to 85 24/TSSOP 1.94
general-purpose apps LVCMOS LVCMOS (VDD = 2.5 V) (VDD = 2.5 V) 170 ps @ 2.5 V
0 to 200 MHz 1.5 to 3.5 ns
(VDD = 3.3 V) (VDD = 3.3 V)
CDC23513 1:10 with fast tpd fanout, LVTTL LVTTL/ 0 to 100 MHz 3.3 3.6 to 4.8 ns 500 ps 0 to 70 24/SOIC/SSOP 4.97
3-state outputs LVCMOS
CDC2351Q 1:10 with fast tpd fanout, LVTTL LVTTL/ 0 to 100 MHz 3.3 3.6 to 4.8 ns 500 ps –40 to 125 24/SOIC/SSOP 6.42
3-state outputs LVCMOS
Crosspoint Switch
SN65LVDS122 2x2 crosspoint switch LVDS LVDS 750 MHz 3.3 400 to 900 ps 40 ps –40 to 85 16/SOIC/TSSOP 4.75
SN65LVDT122 2x2 crosspoint switch LVDS LVDS 750 MHz 3.3 400 to 900 ps 40 ps –40 to 85 16/SOIC/TSSOP 4.75
w/terminators
SN65LVCP22 2x2 crosspoint switch LVDS LVDS 500 MHz 3.3 550 to 800 ps 20 ps –40 to 85 16/SOIC/TSSOP 3.89
DS90CP22 footprint
SN65LVCP23 2x2 crosspoint LVPECL LVPECL 1 GHz 3.3 700 to 1000 ps 20 ps –40 to 85 16/SOIC/TSSOP 4.95
SN65LVDS1252 4x4 crosspoint LVDS LVDS 750 MHz 3.3 250 to 1000 ps 50 ps –40 to 85 38/TSSOP See
Web
Mixed-Signal Buffers
CDCM18042 1:3 LVPECL + 1 LVTTL w/dividers LVPECL LVPECL+ 800 MHz 3.3 TBA TBA TBA 24/MLF See
LVTTL Web
For more information regarding test conditions used to obtain measurements, see datasheets at: www.ti.com/clocks Preview devices appear in BOLD BLUE
1Suggested resale price in U.S. dollars in quantities of 1,000
2Expected release 4Q 2003. See Web for details.
3With series output resistors

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 7

PLL Clock Buffers (Zero-Delay)
Zero-delay PLL-based buffers lock onto CDCR61A Functional Diagram
the incoming clock signal and provide PWRDWNB S0 S1 S2 STOPB
an output synchronous to the input.
This is best suited for applications that Test MUX
Bypass MUX
need to be synchronous.
ByPCLK
PLLCLK
Featured Products
CLK
CDCFR83/CDCR61A — 533-MHz REFCLK B
Phase
Aligner PACLK
CLKB

Direct RambusTM Clock Generator PLL

with Phase Aligner and 400-MHz A

without Phase Aligner D

The CDCR61A is an independent clock

2
generator that provides one differential, MULT0 PCLKM SYNCLKN
MULT1
high-speed Rambus® channel-compatible
output pair and one single-ended output
meet or exceed JEDEC spec for DDRI Applications
at half the crystal frequency. The
and DDRII, respectively. • CDCV857B can be used in all applica-
CDCR83 and CDCFR83 provide clock
tions requiring distribution of SSTL2-
multiplication and phase alignment for Key Features
level clock signals
Direct RambusTM memory systems to • External feedback pins (FBIN, FBINB) to
• CDCV857B is the clocking solution for
enable synchronous communication synchronize outputs to the input clock
DDR200/266/333 memory modules
between the Rambus channel and the • SSC-compatible
• CDCV857B is particularly well-suited
ASIC clock domains. • CDCV857B enters low-power mode
for applications requiring clock distribu-
when no CLK input signal is applied or
Key Features tion to onboard DDR DRAMs
PWRDWN is low
• CDCR61A requires an external • CDCU877 is designed for the clocking
• CDCVF857 is compatible with JEDEC
18.75-MHz crystal oscillator DDRII memory module
DDR400 spec
• CDCFR83 has a wide input-frequency
• CDCU877 can be used in single-ended Get samples, datasheets and app.
range from 33 to 100 MHz
input and output modes reports at:
• CDCFR83 has SSC tracking capability
www.ti.com/sc/device/CDCV857B
to reduce EMI
www.ti.com/sc/device/CDCU877
Applications
• CDCR61A is a 400-MHz differential
CDCU877 Functional Diagram
clock source for the 800-MHz Direct
OE LD* or OE Y0
Rambus clock system Power Down
Y0
OS Control and
• CDCR83 and CDCFR83 provide clock Test Logic
LD*, OS or OE Y1
AVDD
multiplication and phase alignment for Y1
Direct Rambus memory systems PLL bypass
Y2

LD* Y2
Get samples, datasheets and app.
Y3
reports at:
Y3
www.ti.com/sc/device/CDCR61A
Y4
www.ti.com/sc/device/CDCFR83 Y4

Y5
CDCVF857/CDCV857B/CDCU877 — CLK
Y5
CLK
Phase Lock Loop Drivers for DDR 10 kΩ to
PLL
Y6

and DDR-II Memory 100 kΩ

Y6

CDCV857B and CDCU877 are high- Y7

FBIN
Y7
performance, low-crossover-voltage, low-
FBIN
power, low-skew and low-jitter zero-delay Y8
Y8
clock buffers that distribute a differential
*The logic detect (LD) powers down the device when a
clock input pair to 10 differential pairs of logic low is applied to both CK and CK. Y9

Note. Input clock resistors, OE and OS inputs are for Y9

clock outputs and one differential pair of DDRII only. DDRI PLL has power-down input.
feedback clock outputs. These devices FBOUT
FBOUT

8 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 PLL Clock Buffers (Zero-Delay) Selection Guide
Output
Jitter Skew Char.
Input Output Frequency VCC (Peak-to-Peak [P-P] or Phase (max) Temp. # Pins/
Device Description Level Level (MHz) (V) Cycle-to-Cycle [C-C]) Error1 (ps) (°C) Pkg Price2
x1 PLL-Based Buffers
CDC509 1:9 PLL clock LVTTL LVTTL 25 to 125 3.3 P-P: ±100 ps (>66 MHz) 100/+480 ps 200 0 to 70 24/TSSOP 2.27
CDC516 1:16 PLL clock LVTTL LVTTL 25 to 125 3.3 P-P: ±100 ps (>66 MHz) –80/+400 ps 200 0 to 70 48/TSSOP 2.78
CDC2509 1:9 PLL w/narrow loop BW LVTTL LVTTL 25 to 125 3.3 P-P: ±100 ps (>66 MHz) –500 to –50 ps 200 0 to 70 24/TSSOP 2.07
CDC2509B3 1:9 PLL clock with SSC LVTTL LVTTL 25 to 125 3.3 P-P: ±80 ps (66 to 100 MHz) ±200 ps 200 0 to 70 24/TSSOP 2.07
CDC2509C3 1:9 PLL clock with SSC LVTTL LVTTL 25 to 125 3.3 C-C: max |100| ps ±150 ps 200 0 to 85 24/TSSOP 2.05
(66 to 100 MHz)
CDC2510 1:10 PLL w/narrow loop BW LVTTL LVTTL 25 to 125 3.3 P-P: ±100 ps (>66 MHz) –500 to –50 ps 200 0 to 70 24/TSSOP 5.82
CDC2510B3 1:10 PLL clock with SSC LVTTL LVTTL 25 to 125 3.3 P-P: ±80 ps (66 to 100 MHz) ±200 ps 200 0 to 70 24/TSSOP 5.82
CDC2510C3 1:10 PLL clock with SSC LVTTL LVTTL 25 to 125 3.3 C-C: max |100| ps ±150 ps 200 0 to 85 24/TSSOP 2.05
(66 to 100 MHz)
CDC25163 1:16 PLL clock LVTTL LVTTL 25 to 125 3.3 P-P: ±100 ps (>66 MHz) –700/+180 ps 200 0 to 70 48/TSSOP 2.77
(typ)
CDCVF25053 1:5 PLL clock driver for LVTTL LVTTL 24 to 200 3.3 C-C: 70 ps (typ) — 150 –40 to 85 8/TSSOP/ 0.70
general-purpose, SSC (66 to 200 MHz) SOIC
CDCVF250813 1:8 low-power PLL clock LVTTL LVTTL 10 to 200 3.3 C-C: ±100 ps ±150 ps (66 150 –40 to 85 16/TSSOP/ 1.16
with two banks, SSC (66 to 200 MHz) to 200 MHz) SOIC
CDCVF25093 1:9 low-power PLL clock for LVTTL LVTTL 50 to 175 3.3 C-C: |65| ps (typ) ±125 ps (66 100 0 to 85 24/TSSOP 2.11
PC 133 and beyond apps, SSC (100 to 166 MHz) to 166 MHz)
CDCVF25103 1:10 low-power PLL clock driver LVTTL LVTTL 50 to 175 3.3 C-C: |65| ps (typ) ±125 ps (66 100 0 to 85 24/TSSOP 2.11
for PC 133 and beyond apps, SSC (100 to 166 MHz) to 166 MHz)
CDC582/ 1:12 for SDRAM with 1/2x or 2x LVPECL LVTTL 25 to 50/ 3.3 P-P: 200 ps ±500 ps 0.5 ns 0 to 70 52/QFP 4.52
CDC25823 50 to 100
Double Data Rate (DDR)
CDCV850 1:10 PLL clock for DDR apps, SSTL-2/ SSTL-2 60 to 140 2.5 C-C: ±30 ps –50/+180 ps 75 –40 to 85 48/TSSOP 1.46
SSC compatible with two-line universal (100 to 133 MHz) (133 MHz)
serial interface
CDCV855 1:4 (plus feedback pair) PLL SSTL-2/ SSTL-2 60 to 180 2.5 C-C: ±50 ps ±100 ps 50 –40 to 85 28/TSSOP 1.06
differential clock for DDR LVTTL (100 to 180 MHz) (100 to
apps, SSC 180 MHz)
CDCV857 1:10 PLL differential clock for SSTL-2/ SSTL-2 60 to 200 2.5 C-C: ±75 ps ±100 ps (66 75 0 to 85 48/TSSOP 3.50
DDR 200/266, SSC LVTTL (100 to 200 MHz) to 167 MHz)
CDCV857A 1:10 PLL differential clock for SSTL-2/ SSTL-2 60 to 180 2.5 C-C: ±50 ps ±100 ps (100 75 0 to 85 48/TSSOP 2.50
DDR 200/266, SSC LVTTL (100 to 180 MHz) to 180 MHz) 56/µBGA4
CDCV857B 1:10 PLL differential clock driver SSTL-2/ SSTL-2 60 to 200 2.5 C-C: ±50 ps ±50 ps (min/ 70 (typ) –40 to 85 48/TSSOP 3.15
for DDR 200/266/333, SSC LVTTL (100 to 200 MHz) max) (100 56/µBGA4
to 200 MHz)
CDCVF857 1:10 PLL differential clock driver SSTL-2/ SSTL-2 60 to 220 2.5/ C-C: ±50 ps ±50 ps (min/ 40 (typ) –40 to 85 48/TSSOP 3.15
for DDR 200/266/333 and LVTTL 2.6 (100 to 200 MHz) max) (100 40/MLF
DDR 400, SSC to 200 MHz)
CDCU877 5 PLL for DDR-II SSTL-2/ SSTL-2 200 to 333 1.8 C-C: ±40 ps ±50 ps (min/ 40 (typ) –40 to 85 52/µBGA4 3.40
LVTTL (200 to 333 MHz) max) (200 40/MLF
to 333 MHz)
Direct RambusTM
CDCR61A 400-MHz Direct Rambus clock CMOS RSL6 300/400 1.8/ C-C: 100 ps (400 MHz) — — 0 to 85 16/TSSOP 1.59
generator-lite, SSC 3.3
CDCR83 400-MHz Direct Rambus clock CMOS RSL6 267 to 400 3.3 C-C: 50 ps (400 MHz) ±100 ps — –40 to 85 24/SSOP 1.64
generator, SSC
CDCFR83 533-MHz Direct Rambus clock CMOS RSL6 267 to 533 3.3 C-C: 40 ps (533 MHz) ±100 ps — –40 to 85 24/SSOP 1.89
generator, SSC
1Formore information regarding test conditions used to obtain measurements, see datasheets at: www.ti.com/clocks New products appear in BOLD RED
2Suggested resale price in U.S. dollars in quantities of 1,000 Preview devices appear in BOLD BLUE
3With series output resistors
4µBGA = MicroStar BGATM
5Expected release 4Q 2003
6Rambus signaling levels

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 9

Advanced PLL-Based Synthesizers
Featured Products • Supports five differential LVPECL outputs
System Clock Synchronizers — A
• Efficient jitter cleaning from low PLL
synchronizing clock can be used to CDC7005 — Low Phase Noise Clock loop bandwidth
take a system clock signal (from a Synthesizer with Multiplying, • Low-phase noise characteristic
backplane, for example) and provide
Dividing and Jitter Cleaning • Programmable delay for phase
outputs to a subsystem at the same
Key Features adjustments
frequency or an even multiple/divisor
• High-performance 1:5 PLL clock • Packaged in a 64-pin BGA (0.8-mm
of that frequency. In addition to syn-
synchronizer and jitter cleaner pitch — ZVA)
chronizing the system clock, synchro-
• Programmable multiplier and divider • Industrial temperature range –40°C to
nizers can also remove jitter from the
• Two clock inputs: VCXO_IN clock is 85°C
clock source.
synchronized to REF_IN clock Get samples, datasheets and app.
Clock Multipliers — Clock circuits can
• VCXO is external to allow for flexible reports at:
multiply a frequency either by having
application frequencies www.ti.com/sc/device/CDC7005
an internal PLL or by synchronizing the
input frequency to a faster voltage-
controlled crystal oscillator (VCXO). CDC7005 Functional Diagram
The key difference is the level of jitter
the application can tolerate. Internal OPA_IN
PLL-based devices in general will add OPA OPA_OUT
OPA_IP
more jitter than devices that synchro-
STATUS_REF
nize to an external VCXO; however,
STATUS_VCXO
the performance of the latter is
Hold
dependent on the VCXO chosen and
LVCMOS Program Program
design of the feedback path. REF_IN STATUS_LOCK
Input Divider M Delay M

Clock Dividers — Unlike multipliers, Program Program Charge

CP_OUT
PFD
Divider N Delay N Pump
clock division can be accomplished
CTRL_LE
through internal logic dividers in either
CTRL_DATA PECL VI I_REF
non-PLL buffers or PLL-based buffers. 2 LVTTL Reference
CTRL_CLK
The jitter on non-PLL-based buffers
NPD SPI
will be very close to the jitter of the MUX_SEL
NRESET LOGIC
source clock. The jitter added for PLL-
based devices will vary.

Phase Adjustment — Some applica- 5

PECL PECL Y0
tions require phase alignment to adjust PECL
P MUX0 Latch Out Y0B
for delays within a system (varying Divider

lengths on a backplane can sometimes

require phase adjustment). 5 Y1
/1 PECL PECL PECL
MUX1 Latch Out Y1B
Synthesizers — Synthesizers typically
/2
take an oscillator as a direct input and VCXO_IN
then generate several frequencies 5 Y2
PECL PECL PECL PECL
Input /4 Latch Out Y2B
through internal PLLs. Clock synthesiz- MUX2
VCXO_INB
ers are very common in the PC space. /8
5 Y3
PECL PECL PECL
/16 MUX3 Latch Out Y3B

5 Y4
PECL PECL PECL
MUX4 Latch Out Y4B
For more information, visit:
www.ti.com/clocks

10 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Advanced PLL-Based Synthesizers (Continued)

Featured Products (Continued) CDC7005 as a Clock Synchronizer/Jitter Cleaner

Applications
CDC7005
Need to Jitter Clean and/or Synchronize a OPA
REF_IN Loop
Clock Signal? M 0 ps Filter
(30.72 MHz)
Jittery PFD CP
Clock N 0 ps
REF_IN
Y Clean
YB Clock Example
Values SPI MUX
Very often a system clock will develop jitter after
traveling over a backplane. However, very often
245.76 MHz
subsystems (especially those with SerDes or data P MUX
/1 122.88 MHz
converters) will require a very low-jitter clock MUX
VCXO /2 61.44 MHz LVPECL
source. In addition to synchronizing the system (245.76 MHz)
MUX Outputs
/4 30.72 MHz
clock, the CDC7005 can also clean the jitter from MUX (<1 ps
/8 RMS jitter
that system clock source. 15.36 MHz
/16 MUX possible)

Multiply or Divide with Low Jitter CDC7005 as a Multiplier/Divider

60 MHz
REF_IN CDC7005
Y
180 MHz OPA
YB Low BW
REF_IN Loop
250 0 ps
The VCXO selected can be at a higher frequency (60 MHz) Filter
PFD CP
than the input clock, which results in the input 750 0 ps
clock being multiplied to the outputs. Each output
can then be divided by 1, 2, 4, 8 or 16 from the Example
VCXO frequency. Whether multiplying or dividing, Values SPI MUX

the CDC7005 will maintain a very low-jitter output.

180 MHz
P MUX
/1 90 MHz
MUX
VCXO /2 45 MHz LVPECL
(180 MHz) MUX Outputs
Low Noise /4 22.5 MHz
/8 MUX
11.25 MHz
/16 MUX

Need Overall Phase Adjustment to Keep a CDC7005 for Phase Adjustment

System in Sync?
CDC7005
OPA
REF_IN Loop
Y Phase REF_IN
M 2.75 ns Filter
YB Delayed (120 MHz)
PFD CP
Y Phase
YB Advanced N 0 ps

Sometimes the phase of a clock needs to be Example

Values SPI MUX
adjusted to account for delays in a system (some-
times due to trace length over a backplane). The
120 MHz
CDC7005 can provide up to 2.75 ns of phase P MUX
adjustment. /1 120 MHz
MUX
VCXO /2 60 MHz LVPECL
MUX Outputs
(120 MHz) /4 30 MHz
/8 MUX
15 MHz
/16 MUX

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 11

Advanced PLL-Based Synthesizers (Continued)

Featured Products (Continued) CDCF5801 Functional Diagram

CDCF5801 — Low-Jitter Clock PWRDNB P0 StopB
Multiplier/Divider with
CDCF5801
Programmable Delay and VDDPA
Phase Alignment Control 00
The CDCF5801 provides clock multiplica- VDDP
GNDP GNDPA Div2 11 CLKOUT
REFCLK Phase (25...280) MHz
tion and division from a reference clock Aligner Div4 10
(12.5...240) CLKOUTB
(REFCLK) signal. It also allows delay or PLL Delay
MHz Div8 01
(Step Size =
advance of the CLKOUT/CLKOUTB with 1/(384 x f))
steps of 2.6 mUI through a unique GNDO
01 Div2

VDDREF/2
CLK
phase aligner. VDDO

00 Div4
Key Features DLY+ DLY–
11 Div8
• Low-jitter clock multiplier x1, x2, x4
or x8: 10 Div16
– Input frequency: 12.5 to 240 MHz
– Output frequency: 25 to 280 MHz 2 VDDPD/2 2
• 2.6-mUI programmable bidirectional
delay steps MULT[0:1] DLYCTRL LEADLAG P[1:2]
• One single-ended input and one (0...240) (0...280)
MHz MHz
differential output pair (input tolerates
LVPECL and LVTTL)
• Output can drive LVPECL, LVDS and • Auto frequency detection to disable • Spread spectrum clock compatible
LVTTL device (power-down mode) (SSC)
• Spread spectrum clock tracking ability • Operates from single 3.3-V supply • Available in 16-pin TSSOP package
to reduce EMI • Industrial temperature range –40°C to
Get samples, datasheets and app.
• Industrial temperature range: 85°C
reports at:
–40°C to 85°C • 25 on-chip series damping resistors
www.ti.com/sc/device/CDCVF25084
• No external RC network required
Applications
• Phase adjustment
• Low-jitter multiplier
• Low-jitter divider
CDCVF25084 Functional Diagram
Get samples, datasheets and app.
reports at: FBIN
16 Divide
by 4 MUX 2 1Y0
www.ti.com/sc/device/CDCF5801 1 PLL 25Ω
CLKIN
3 1Y1
CDCVF25084 — 3.3-V 1:8 Zero 25Ω

Delay (PLL) x4 Clock Multiplier 14 1Y2

25Ω
Key Features
15
• Phase-locked loop-based multiplier 25Ω
1Y3
by four 8 Input
S2 Select
• Input frequency range: 2.5 MHz to 9
S1 Decoding
45 MHz
• Output frequency range: 10 MHz to 6
2Y0
25Ω
180 MHz
• LVCMOS/LVTT I/O compatible 7
25Ω
2Y1
• Low jitter (cycle-cycle): ±120 ps over
the range 75 MHz to 180 MHz 10
25Ω
2Y2
• Distributes one clock input to two
banks of four outputs 11
25Ω
2Y3

12 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Advanced PLL-Based Synthesizers Selection Guide
Output
Jitter Skew Char.
Input Output Frequency VCC (Peak-to-Peak [P-P] or Phase (max) Temp. # Pins/
Device Description Level Level (MHz) (V) Cycle-to-Cycle [C-C]) Error1 (ps) (°C) Pkg Price2
Jitter Cleaners
CDC7005 Jitter cleaner, 5 LVPECL LVCMOS LVPECL 10 to 800 3.3 — — 200 –40 to 85 64/BGA 10.00
Phase Aligners
CDC5801 Multiplier/divider with LVCMOS LVPECL/ 150 to 500/ 3.3 P-P: PA bypassed = 40 ps, — — –40 to 85 24/SSOP 2.80
programmable delay and LVDS/ 12.5 to 62.5 PA active = 70 ps,
phase alignment LVTTL Division mode = 75 ps
CDCF5801 Multiplier/divider with LVCMOS LVPECL/ 25 to 280 3.3 P-P: PA bypassed = 40 ps, — — –40 to 85 24/SSOP 2.80
programmable delay and LVDS/ PA active = 70 ps,
phase alignment LVTTL Division mode = 75 ps
Multipliers/Dividers
CDC536 1:6 PLL clock with 1/2x or TTL LVTTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 28/SSOP 1.89
2x output, 3-state outputs
CDC582 1:12 PLL with 1/2x or LVPECL LVTTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 52/TQFP 4.52
2x output
CDC586 1:12 clock with 1/2x or LVTTL LVTTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 52/TQFP 5.05
2x output, 3-state outputs
CDC25363 1:6 PLL clock with 1/2x or TTL LVTTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 28/SSOP 5.05
2x output, 3-state outputs
CDC25823 1:12 PLL clock with 1/2x LVPECL LVTTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 52/TQFP 4.52
or 2x output
CDC25863 1:12 PLL clock with 1/2x or TTL TTL 25 to 100 3.3 P-P: 200 ps ±500 ps 500 0 to 70 52/TQFP 5.05
2x output, 3-state outputs
CDCVF25084 1:8 low-power 4x multiplier LVTTL LVTTL 10 to 180 3.3 C-C: ±100 ps — 150 –40 to 85 16/TSSOP 2.30
with two banks, SSC (66 to 180 MHz)
1Formore information regarding test conditions used to obtain measurements, see datasheets at: www.ti.com/clocks New products appear in BOLD RED
2Suggested resale price in U.S. dollars in quantities of 1,000 Preview devices appear in BOLD BLUE
3With series output resistors

Real-Time Clocks (RTCs)

Data Bus Type — There are two bus
types available: (1) address/data multi-
plexed and (2) parallel. With (1), the
memory address lines and data lines
share the same pins. With (2), the
address lines and data lines are separate
and the interface is the same as a static
RAM. The address/data multiplexed
devices have fewer pins but may require
more logic to interface.
3- or 5-V Operation — The RTCs can
run from a 5-V or 3-V rail.
CPU Supervisor — Some parts include Features
a full CPU supervisor that provides: • Real-time clock counts seconds
• CPU reset (power-on and push-button) through centuries in BCD format
• Power-fail interrupt • Complete surface-mount solution with
• Watchdog timer SNAPHAT TM package
• Non-volatile control for additional • Less than 500 nA of current consump-
NVSRAM tion in battery backup mode
• Clock accuracy (modules) better than
The integration of the supervisor on the
1 minute per month
RTC can reduce the component count in
• Up to 512K x 8 of onboard NVSRAM
a design.
• Onboard NVSRAM • 3- or 5-V operation
• VCC tolerance • Fully integrated CPU supervisor
• Package type

For more information, visit:

www.ti.com/clocks

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 13

 Real-Time Clocks (RTCs) Family of Products

Integrated Circuits

Address/Data Parallel
Multiplexed

On-Chip NVSRAM On-Chip & External External

RAM Control RAM Control

3V 5V 5V 3V 5V

— bq3285LD — bq3285 — bq4285 — bq4802LY — bq4845

— bq3285LF — bq3285E — bq4845Y
— bq4802Y

Modules
(Includes Battery and Crystal)

Address/Data Parallel
Multiplexed

On-Chip NVSRAM On-Chip & External On-Chip NVSRAM On-Chip & External
RAM Control RAM Control

114 Bytes 242 Bytes 114 Bytes No CPU CPU 5V

Supervisor Supervisor 3V

— bq3287 — bq3287E — bq4287 — bq4830Y — bq4822Y — bq4802LY — bq4847

— bq3287A — bq3287EA — bq4287E — bq4850Y — bq4832Y — bq4847Y
— bq4842Y — bq4802Y
— bq4852Y

Real-Time Clocks (RTCs) Selection Guide

VCC VCC External
Level Tolerance CPU Onboard NVSRAM
Device (V) (%) Supervisor NVSRAM Control Package Price1
Parallel Interface
bq4802Y 5 10 Yes No Yes 28-pin SOIC, TSSOP or SNAPHAT 2.35
bq4802LY 3 10 Yes No Yes 28-pin SOIC or TSSOP 2.35
bq4845 5 5 Yes No Yes 28-pin SOIC 2.35
bq4845Y 5 10 Yes No Yes 28-pin SOIC 2.35
bq4830Y 5 10 No 32K x 8 No 28-pin DIP Module 10.50
bq4822Y 5 10 No 8K x 8 No 28-pin DIP Module 9.50
bq4832Y 5 10 No 32K x 8 No 32-pin DIP Module 12.50
bq4842Y 5 10 No 128K x 8 No 32-pin DIP Module 14.50
bq4852Y 5 10 No 512K x 8 No 36-pin DIP Module 29.00
bq4847 5 5 Yes No Yes 28-pin DIP Module 4.95
bq4847Y 5 10 Yes No Yes 28-pin DIP Module 4.95
bq4850Y 5 10 No 512K x 8 No 32-pin DIP Module 25.00
Address/Data Multiplexed
bq3285 5 10 No 114 bytes No 24-pin SOIC 2.00
bq3285E 5 10 No 242 bytes No 24-pin SOIC or SSOP 2.00
bq3285LD 3 10 No 242 bytes No 24-pin SSOP 2.00
bq3285LF 3 10 No 240 bytes No 24-pin SSOP 2.00
bq3287 5 10 No 114 bytes No 24-pin DIP Module 3.79
bq3287A2 5 10 No 114 bytes No 24-pin DIP Module 3.79
bq3287E 5 10 No 242 bytes No 24-pin DIP Module 3.79
bq3287EA2 5 10 No 242 bytes No 24-pin DIP Module 3.79
bq4285 5 10 No 114 bytes Yes 24-pin SOIC 2.20
bq4285E 5 10 No 114 bytes Yes 24-pin SOIC 2.20
bq4287 5 10 No 114 bytes Yes 24-pin DIP Module 4.30
1Suggested resale price in U.S. dollars in quantities of 1,000
2The "A" versions have a RAM clear input pin

14 Clocks and Timing Selection Guide Texas Instruments 4Q 2003

 Resources
Literature For More Information
The literature below is available to download as Acrobat Reader For more information, please visit www.ti.com/clocks or
files at www-s.ti.com/sc/techlit/litnumber by replacing contact your nearest TI Product Information Center listed below.
litnumber with the Literature Number shown below. Other
literature is available at www.ti.com/clocks by selecting an
icon for Application Notes.

Description Lit. No. Description Lit. No.

Defining Skew, Propagation-Delay, Phase Offset (Phase Error) scaa055 Using TI’s CDC111/CDCVF111 with TLK3104SA Serial Transceiver
Design and Layout Guidelines for the CDCVF2505 Clock Driver scaa045 for Gigabit Ethernet and Backplane Applications scaa049
Design Considerations for TI’s CDCV857/CDCV857A DDR PLL scaa054 Using TI’s CDCV304 with Backplane Transceiver
Filtering Techniques: Isolating Analog and Digital Power Supplies (TLK1201/1501/2201/2501/2701/2711/3101) scaa052
in TI’s PLL-Based CDC Devices scaa048 AC-Coupling Between Differential LVPECL, LVDS, HSTL and CML scaa059
HSTL Clock Buffer Using the CDCV850 scaa058 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML scaa062
Interfacing Between LVPECL, LVDS, and CML scaa056 Real-Time Clock Notes
Jitter Performance of TI’s CDC111/CDCVF111 scaa047 U-500 Using the bq4845 for a Low-Cost RTC/NVSRAM Subsystem slua031
Output Jitter of CDC111/CDCVF111 in an ASIC U-502 Time-Base Oscillator for RTC IC slua051
Networking Application scaa051 U-503 Using the bq3285/7E in a Green or Portable Environment slua094
Using the CDC857 and CDCV850 to Transform a Single-Ended Clock Using RAM Clear Function with bq3285/bq3287A RTCs slua052
Signal Into Differential Outputs scaa043
Using TI’s CDCVF111 with SLK2501 Serial Gigabit Transceiver for
SONET and Gigabit Ethernet Applications scaa050

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Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale.
Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance,
customer’s applications or product designs, software performance, or infringement of patents. The publication of information regarding any other company’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Real World Signal Processing, the black/red banner and MicroStar BGA are trademarks of Texas Instruments. Direct Rambus is a trademark B010203
and Rambus is a registered trademark of Rambus Incorporated. All other trademarks are the property of their respective owners.

© 2003 Texas Instruments Incorporated

Printed in the U.S.A. by ____________________, Dallas, TX
Printed on recycled paper.

4Q 2003 Texas Instruments Clocks and Timing Selection Guide 15

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