Circuit Design Tutorial

Introduction to the cadence tutorial for analog ic design

In this tutorial you will be working with TSMC 0.18um CR018/CM018 mixed-mode
process design kit, available through MOSIS. The information contained in the design kit
is extremely confidential and you are recommended to consult your course instructor
before disclosing any results obtained in your class project/assignments. This is a short
tutorial meant to give a heads-up to those who are new to Cadence Design Environment.
In order to use Cadence software, you will need an account in CAD and Visualization
Lab (CVL) or IMPACT cluster.

Impact cluster is available only to the members of CESCA group

• Environment Setup

• Creating a Library and plotting MOS I-V characteristics

• Layout Tutorial
 Environment Setup

Please note that the steps given in this section are specific to the Cadence installation
environment in CVL and IMPACT.

1. Create a directory ECE4220 and change your working directory to ECE4220.

> mkdir ECE4220

> cd ECE4220

2. Use a text editor of your liking and create a file named cds.lib and copy/paste the
following text into the file:

INCLUDE /software/Cadence/IC5141/share/cdssetup/cds.lib
DEFINE tsmc18rf /software/Cadence/TSMC018/tsmc18rf
DEFINE avTech /software/Cadence/ASSURA315/tools/assura/etc/avtech/avTech

3. Copy /software/Cadence/TSMC018/display.drf file into ECE4220.

4. Then type the following sequence of commands to open a Command Interpreter

Window (CIW), shown in figure 1:

> Cadence [It is a script which configures various environment variables required to
properly run Cadence]
> icfb& [It stands for Integrated Circuit Front-to-Back and is a Cadence program, which
integrates all the design tools required for IC front and back-end design]

Figure 1. Cadence Command Interpreter Window

5. Go to Tools->Library Manager to open Library Manager as shown in figure 2:

 Figure 2. Library Manager

6. In Library Manager, the library column shows a list of libraries

available/configured. Cell column shows the cells available in the selected library.
Once you select a cell, you will see a list of corresponding cell views available in
View column. A cell may have multiple views corresponding to different Cadence
tools.

7. In Library Manager, you may enable check �Show Category?checkbox to

categorize the available cells in a library into categories according to their type, as
shown in figure 3:
 Figure 3. Library Manager with Category View Enable

If you are able to work through till this point without troubles, then your environment
setup for working with Cadence is complete.
 Creating a Library and plotting MOS I-V characteristics

In this section you will learn how to create your library and create a simple schematic/cell
view to simulate NMOS I-V characteristics and plot various MOS parameters thereof.

1. From File Menu click on File->New->Library, a new library dialog-box appears.

Enter a library name, eg tutorial and hit OK. See figure 4 below:

Figure 4. New Library Dialog-box

2. As you hit OK, a new dialog-box appears. Check the box corresponding to
"Attach to an existing techfile" and hit OK, as shown in figure 5:

Figure 5. Technology File for New Library File Dialog-box

3. In the new dialog-box which appears choose "tsmc18rf" and hit OK.

Figure 6. Attach Design Library Dialog-box

4. You would see "tutorial" in the list of libraries in Library Manager. Next select
"tutorial" library in Library Manager and click on File->New->Cell View. A new
cell view dialog-box appears as shown in figure 7. Type in "mosiv" in Cell Name
and make sure that View Name is "schematic" and Tool is selected as "Composer-
Schematic" and Library Name is "tutorial". Hit OK and a Virtuoso Schematic
Editing window will open up.

Figure 7. New Cell View Dialog-box

5. With Virtuoso Schematic Window selected hit 'i' key, an Add Instance dialog-box
will show up. Click "Browse" button, a Library Browser window will open up.
Select tsmc18rf Library, Mosfets from Category, nmos2v from Cell and symbol
from View column. Go back to the Add Instance dialog-box and change l (M)
property to 'l' and w (M) property to 'w' as shown in figure 8. At this point you
have configured NMOS properties and are ready to place an instance in your
schematic. So, go back to Schematic Editing Window and you would see a ghost
of the NMOS device symbol, place it anywhere in the dotted black area and hit
escape key.
 Figure 8. Add Instance Dialog-box for NMOS

6. Following the same procedure, add a voltage source and a ground into your
schematic. The voltage source can be found in analogLib->Sources:Independent-
 >vdc->symbol. The voltage source configuration in shown in figure 9. Ground
component is available in analogLib->Sources:Globals->gnd->symbol.

Figure 9. Add Instance Dialog-box for DC Voltage Source

7. In order to wire the placed component. Hit 'w' to enable wiring tool. Click on
NMOS gate terminal and layout the wire to connect to positive terminal of DC
voltage source, finally clicking on the positive terminal of the voltage source to
end the wire. Similarly connect NMOS drain and body terminals and negative
terminal of voltage source to the gnd component. Finally hit escape key to end
wiring. The schematic now looks as shown in figure 10. Save the schematic by
clicking the save button (highlighted in figure 10).
 Figure 10. Intermediate State of the Schematic

8. Now hit 'c' key and click on gate DC voltage source to make a copy of it. You
would see a ghost voltage source symbol. Place the copied voltage source close to
NMOS drain. Hit escape key to end copy. Now select the copied source and hit 'q'
key. An object property editor window will open up; change the DC voltage
property to "vds". You will observe that the object highlight box color changes to
pink in the schematic. Make sure that in the property editor window "Apply to" is
selected as "only current instance" and hit ok. Wire the copied voltage source as
shown in figure 11. Hit check and save button and make sure that CIW window
does not show any errors.
 Figure 11. Final Schematic

9. From Tools menu select Tools->Analog Environment. A Virtuoso Analog Design

Environment (ADE) Window will open up. Click on Setup-
>Simulation/Directory/Host. In the setup window, make sure Simulator is
selected as "spectre".

10. Select Variable->Copy from Cellview, you will see all the variables defined in
schematic show up in "Design Variables" section. Double click on 'w' and change
its value to 1u. Similarly, set vgs = 1, vds=1.4 and l=180n.

11. Next select Analysis->Choose... . In Choosing Analysis dialog-box select analysis

as "dc" and choose other settings as shown in figure 12 and hit ok.
 Figure 12. Analysis Setup

12. Next you need to select the variables to be plotted. Select Outputs->To Be Plotted
and then click on the drain terminal of NMOS in the schematic. The current
through the drain terminal is added to "Outputs" section of ADE. Double click on
the output and check the "saved" checkbox and hit "change". Quit the "Setting
Outputs" dialog-box by hitting OK. The current state of ADE window looks as
shown in figure 13:
 Figure 13: Virtuoso Analog Design Environment Window

13. Click on Simulation->Netlist and Run. When the simulation completes, you will
observe a plot similar the one shown in figure 14. The axis labels have been
intentionally removed because of confidentiality of the values.
 Figure 14: NMOS Ids vs Vds

14. Output resistance (ro) of a NMOS is the inverse of the slope of the above plot.
This mathematical operation can be performed by using calculator tool. Click on
Tools->Calculator... . In the calculator window select "dc" tab and check "wave"
checkbox. Now go the plotted waveform and click at any point on the waveform.
The waveform expression is copied into the calculator. Next select "deriv"
operation from listed operations in calculator, followed by "1/x" operation.
Change plot option to "New Win" and click on "Eval" button. A new plot of ro is
generated as shown in figure 15b. The calculator window settings are shown in
figure 15a. You may want to play around with the calculator utility and try
plotting mobility, gm etc of NMOS.
Figure 15a. Calculator Window

Figure 15b. Plot of ro vs Vds

15. Next select Tools->Parametric Analysis. Configure the parametric analysis setup
window as shown in figure 16 below with vgs as the parameter.

Figure 16: Parametric Analysis Setup

16. Then click on Analysis->Start. At the completion of the analysis you will observe
a plot similar to the one shown in figure 17 below:

Figure 17. Plot from Parametric Sweep

 Layout with Virtuoso
Authors: Jeannette Djigbenou, Meenatchi Jagasivaman, and Jia Fei
After developing a schematic of your design, the next step in the design flow is
creating a layout of your design using Cadence Virtuoso. A layout describes the
masks from which your design will be fabricated. The layers in a layout describe
the physical characteristics of the device and have more details than a
schematic. Therefore, layout verification of your design is critical.

There are two types of layout design: Full-Custom and Automated. Full-custom
layout is when the user physically draws all of the layers for the individual
transistor. This is a very tedious process, but usually enables results in a
compacter design than the automated process. The automated process, on the
other hand, is done by instantiating standard cells (reusing basic blocks) and
usually takes more area, but it is much faster.

To get you acquainted with the layout process, a tutorial has been developed that
describes the procedure to custom layout an inverter. Please go through it.

This following is the usual steps followed for the layout:

1. Layout Transistors and Routing...

2. Creating I/O Pins
3. Design Rule Check (DRC)

Layout Transistors and Routing...

The first step in layout design is to layout the transistors in your circuit. Where the
transistors are placed can be critical in getting the most compact design. Also, it
is important to make sure that all important nodes are accessible for routing.
After the transistors have been implemented, the next step is to make the
necessary routing connections. Usually, for large circuits, routing can take up as
much as 50% of the total area. Hence, it is a good idea to think about the
floorplanning of your design before you start the layout.
You can look at the Inverter Tutorial to get a basic introduction to what the
necessary components are.
Back To Top

Creating I/O Pins

Once you have finished creating the layout, the next step is to add the I/O pins of
your circuit. It is necessary to add the vdd! and vss! connections to your circuit for
the purpose of DRC. The following is a procedure to add I/O pins to your circuit:
Before you start, you have to have a layout (view name: layout) in your library.
 o From your Layout window:
1. Choose Create->Pin... from the menu.The Create Pin form
will appear.
2. If the form is titled "Create Shape Pin", choose "sym pin"
under the Mode option.
3. Enter a TerminalName(the name of your pin).
 NOTE: For HSPICE, there is a node name limit
of 16 characters.
4. Make sure that the "Display Pin Name" option is selected.
5. Specify the "I/O Type" as either input, output, or inputoutput.
6. Specify the Pin Type as either Metal1_T, Metal2_T,...
depending on which is the top layer at the place that the pin
is to be inserted.
7. Specify the Pin Width to the desired pin width (the pin is
square).
8. Move the mouse to specify where the pin and the label
should be placed.
9. Repeat the above process (1-7) for all the pins in your
circuit.

Back To Top

Design Rule Check (DRC)

Go to the DRC Section of the Cadence Tutorial, to get the DRC procedures.

Inverter Tutorial with Virtuoso

Authors: Jeannette Djigbenou, Meenatchi Jagasivamani, Jos Sulistyo
This tutorial shows layout of a CMOS inverter. At this point, you should have set
up the environment. Otherwise, refer to Setting UP Your Unix Environment. You
are assumed to know how to use layout editor, Virtuoso. If you don't know the
layout editor, follow the on-line tutorial in the cdsdoc. To start up open book, type
cdsdoc & from a terminal. The tutorial for Virtuoso can be found in cdsdoc at:
Custom IC Layout -> Layout -> Cell Design Tutorial -> Chapter 2.

The tutorial given below is for the NCSU design kits:

• TSMC 0.25um (MOSIS deep submicron rule) of NCSU kit

(NCSU_TechLib_TSMC03d)

TSMC 0.25um (MOSIS deep-submicron rule) of NCSU Kit

• Creating a New Cellview:

o Create a new cellview under an existing library. See Schematic
Entry with Composer to find out how to create a new library.

In the Command Interface Window (CIW):

a) Select File -> New -> Cellview.
b) Choose the library under which you would like to create
the new cell view.
c) Enter Cell Name: My_Inv (for the tutorial)
d) Choose Virtuoso as the Tool. View name should be
layout.
e) Click OK.
A blank virtuoso window should open.

• Setting Display Parameters:

a) Options -> Display.

b) Set the following options:

1. Pin names: On
2. Minor Spacing : 1.08
3. Major Spacing : 4.32
4. X Snap Spacing: 0.06
5. Y Snap Spacing: 0.06
6. Display levels:
7. From: 0
8. To: 30
• Click "Save To" to set them permanently.
• Layout an Inverter:
 o You should follow MOSIS SCN5M_DEEP design rule for TSMC
0.25 um five-metal, 2.5V processing (lambda = 0.12 um & min.
length = 0.24 um).
o The inverter consists of three parts -- p-transistor, n-transistor, and
connections.
o This inverter is probably almost minimum size; therefore, the n- and
p-transistors have the same W/L.

Use this figure as a guideline as you go through the procedure.

o Layout of P-transistor with L=0.24 um and W=0.48 um.

In this tutorial, we are using the Nwell process. Thus, the

substrate will be p-substrate. We will create a pmos transistor first.
To do that we need an Nwell in which the pmos transistor will be
formed.

 Draw the well

a) Select the n-well layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the n-well on the cellview
to be 2.94 wide by 2.52 tall .

 Draw the p- and n-select regions for the p transistor

a) Select the pselect layer from the LSW window; we

will draw the pselect enclosing the transistor
b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the pselect on the
cellview; 1.98 wide and 0.96 tall; its left- and right-
edges should be 0.48 away from well edges.
The pselect should be placed within the n-well, even if
the size should vary. (you can use the Edit->move
command to move the layer)

 Draw Diffusions

a) Select the pactive layer from the LSW window; we

will draw the active region of the p-device
b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
 c) Using your mouse, draw the pactive on the cellview
to be 1.5 wide by 0.48 tall - it should be enclosed by
the pselect by 0.24 and by the nwell by at least 0.72

 Draw Poly

a) Select the poly layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the poly on the cellview to
be 0.24 long by 1.32 wide.
The poly should be placed at the center of the p-
island. The poly should extend over the p-island by
0.30 um.

 Place Contacts

a) Select the contact layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the contact on the cellview
to be 0.24 long by 0.24 wide.
The contact should be placed at both sides of the
pactive. Repeat the above process for the second
contact.

o Layout of N-transistor with L=0.24 um and W=0.48 um.

 Draw the nselect

a) Select the nselect layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the nselect on the cellview
to be 1.98 wide by 0.92 tall

 Draw the N active region

a) Select the nactive layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the nactive on the cellview
to be 1.50 wide by 0.48 tall; it should be enclosed by
the nselect by 0.24 around its edges. Also, it needs to
be at least 0.72 away from the n-well (= 6 x lambda;
MOSIS rule 2.3 for DEEP).
  Extend Poly

a) Extend the poly layer created for the p-transistor

over the n-island, making sure that the poly extension
over n-island is 0.30. (you can use the Edit->Stretch
command to stretch the poly)
The poly should be placed at the center of the n-
island.

 Place Contacts

a) Select the contact layer from the LSW window

b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using your mouse, draw the contact on the cellview
to be 0.24 long by 0.24 wide.
The contact should be placed at both sides of the p-
island. Repeat the above process for the second
contact.

o Layout necessary connections

 Draw the well-contact

a) Select the nselect layer from the LSW window; we

will draw the nselect enclosing the substrate (vdd)
contact for the P transistor.
b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using the mouse, draw the nselect on the cellview;
at least 0.96 tall and wide, as it will have to enclose
the contact n-active by at least 0.24, which in turn
enclose the contact by at least 0.12.
The nselect abuts directly to the pselect of the P
transistor, but they should not overlap. Also, both
selects should be placed within the n-well.
d) Select the nactive layer from the LSW window; we
will draw the body contact region of the p device.
e) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
f) Using your mouse, draw the nactive on the cellview
to be at least 0.48 wide by 0.48 tall
g) Add a contact in the center of the well-contact
island.

 Draw the Substrate-contact

 a) Select the pselect layer from the LSW window; we
will draw the nselect enclosing the substrate (vss =
ground) contact for the N transistor
b) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
c) Using the mouse, draw the pselect on the cellview;
at least 0.96 tall and wide, as it will have to enclose
the contact p-active by at least 0.24, which in turn
enclose the contact by at least 0.12.
The nselect abuts directly to the nselect of the N
transistor, but they should not overlap.
d) Select the pactive layer from the LSW window
e) Select the Create->Rectangle (or choose the
Rectangle icon from the side toolbar).
f) Using your mouse, draw the n-island on the cellview
to be 0.48 wide by 0.48 tall; it must be enclosed by
the pselect by 0.24.
The p-island should be placed at least 0.48 um (= 4 x
lambda, MOSIS rule 2.5 DEEP) below the n-
transistor.
g) Add contacts in the center of the substrate-contact
island.

 Metal Connections

a) Connect the source of p-transistor to the well-

contact using the metal 1 layer.
b) Connect the source of n-transistor to the substrate-
contact using the metal 1 layer.
c) Add a contact to the gate (poly)
At this point, your layout should look something like
this.

o Add Pins:

You need to add pins for the input (named ip), output
(named op), vdd, and vss in order to pass DRC. Go to the
Creating I/O Pins section to get the procedure on how to add
pins to your layout.

o Design Rule Check (DRC)

DRC is used to check that all process-specific design rules

(such as spacing) have been met. Go to the DRC section to
get the DRC procedure.
This concludes the Inverter tutorial. Back to Top
 Schematic Entry with Composer
Authors: Jeannette Djigbenou, Carrie Aust and Meenatchi Jagasivamani
This tutorial explains how to copy gate & switch symbols into MOSIS library and
a procedure for gate-level and switch-level schematic entry. At this point, you
should have set up the environment. Otherwise, refer to Setting UP Your Unix
Environment. You are assumed to know how to use schematic editor, Composer.
If you don't know the schematic editor, follow the on-line tutorial in the cdsdoc.
The tutorial for Composer can be opened by typing "cdsdoc" in the command line
within your Cadence environment.
Select Docs by ICS 1.415 -> Cadence Platform -> Custom IC design -> Virtuoso
Schematic Editor User Guide
If you get an error message concerning the Viewer, start mozilla in your
command line first, then attempt to re-open the tutorial.

1. Creating a New Library (if necessary)

o Use a library to store related cell views. For example, use a library
to hold all the cell views for a single project.
 If you are using the NCSU design kit, you can create a new
library from the CIW window (use the Help button to get
instructions on creating a new library).
o To create library from the CIW window (for NCSU kit):

a) Select File -> New -> Library.

b) Enter a library name.
c) Enter the absolute path name if you want the library
created somewhere other than the working directory.
d) Choose the Attach to an existing techfile option.
e) Choose your library; for instance, for 0.25um in MOSIS
DEEP rule, choose NCSU_Techlib_tsmc03d.
f) Click OK.

2. Creating a New Schematic Cell View

o In the CIW window:

a) Select File -> New -> Cellview.

b) Choose the library under which you would like to create
the new cell view.
c) Enter a cell view name.
d) Choose Composer - Schematic as the Tool. View name
should be schematic.
e) Click OK.
A blank composer - schematic window should open.

3. Creating Logic Using Gate-Level or Switch-Level Logic

o Gate-Level

a) Create an instance of a logic gate from the technology

library.
 1. Select Add -> Instance or use the toolbar.
2. Choose logic gates from the NCSU_Digital_Parts
library for NCSU kit. Use the Browse button in the
Add Instance Form to choose a symbol view of a logic
gate.

b) Add pins for inputs and outputs.

3. Select Add -> Pin or use the toolbar.

4. Enter pin name(s) (You can enter several names at
once).
5. Choose appropriate direction: Input or Output or
InputOutput (bidirectional).
6. Place pin in the schematic.
7. Click Cancel when done placing pin(s).
8. Add wires to connect gates and pins: Add -> Wire or
use the toolbar.
o Switch-Level

a) Create instance of nmos or pmos from the analogLib

library.

1. Select Add -> Instance or use the toolbar.

2. Choose devices from NCSU_Analog_Parts for the
NCSU kit. Use the Browse button in the Add Instance
Form to choose a symbol view of a CMOS device.
3. Enter values for device parameters in the Add
Instance Form.
 Model Name: from NCSU_Analog_Parts for
the NCSU kit, N_Transistors (or
P_Transistors) -> nmos4 (or pmos4) in the
component browser; note that for NCSU kit,
single-click (not double-click) in the component
browser window chooses the device, and also,
VDD and ground connections are also
available under "supply nets" category in the
component browser.
 Bulk Node Connection: vss! for nmos device or
vdd! for pmos device.
 Width: Your chosen width (example: 600nm,
2.4um, or as necessary)
 Length: Your chosen length.

b) Add wire to source of nmos/pmos and type "l" to add wire

name as VDD! and VSS!.
c) Add pins for inputs and outputs.
 4. Select Add -> Pin or use the toolbar.
5. Enter pin name(s) (You can enter several names at
once).
6. Choose appropriate direction: Input or Output or
InputOutput (bidirectional).
7. Place pin in the schematic.
8. Click Cancel when done placing pin(s).

d) Add wires to connect gates and pins: Add -> Wire or use
the toolbar.

4. Use Check and Save to save design. Select Design -> Check and Save
or use the toolbar. Errors will be displayed in the CIW. Correct any
errors.
5. Further instruction is available in cdsdoc. To view Composer tutorial:

a) At the UNIX command line, type: cdsdoc

b) After the cdsdoc window has appeared, select Design
Entry -> Composer Tutorial. Scroll through the contents to
find the subjects of interest.
Have fun!