CpE 487: Digital System Design

Fall 2009

Lecture 10
Subprograms and overloading

Prof. Haibo He
Department of Electrical and Computer Engineering
Stevens Institute of Technology
Hoboken, NJ 07086

1
 Review of the previous lecture

• Generics and configurations

– Generics
– Why configurations?
– Configuration specification and declaration

2
 Outline of this lecture

• Subprograms
• Subprogram overloading
• Operator overloading

3
 Subprograms

A subprogram defines a sequential algorithm that performs

a certain computation. There are two kinds of subprograms:
Function:
Computes a single value.
executes in zero simulation time
Procedure:
can computes several values
may not execute in zero simulation time

4
 Essentials of Functions

function rising_edge (signal clock: std_logic) return boolean is

--
--declarative region: declare variables local to the function
--
begin
-- body
--
return (expression)
end rising_edge;

• Formal parameters and mode

– Default mode is of type in
• Functions cannot modify parameters
– Pure functions vs. impure functions
• Function variables initialized on each call
5
 Pure functions VS. impure functions

Syntax:
[pure | impure] function function-name (parameter-list) return return-type

Pure function: return the same value each time the function is called with
the same set of actuals.

Impure function: potentially returns different values each time the

function is called with the same set of actuals. For instances, NOW is an
impure function because it returns different values when called at
different times.

If neither keyword pure or impure is present in the function specification,

the function is, by default, a pure function

6
 Essentials of Functions (cont.)

function rising_edge (signal clock: std_logic) return boolean is

--
--declarative region: declare variables local to the function
--
begin
-- body
--
return (expression)
end rising_edge;

• Types of formals and actuals must match except for formals which are
constants (default)
– Formals which are constant match actuals which are variable,
constant or signal
• Wait statements are not permitted in a function!

7
 Placement of Functions

Architecture
visible in processes
function W
A, B & C

process A process B process C

function X function Y function Z

visible only in
process A

• Place function code in the declarative region of the

8
architecture or process
 Function: Example

architecture behavioral of dff is

function rising_edge (signal clock : std_logic) return boolean is
variable edge : boolean := FALSE;
begin Architecture
edge := (clock = ‘1’ and clock’event); Declarative
return (edge); Region
end rising_edge;

begin
output: process
begin
wait until (rising_edge(Clk));
Q <= D after 5 ns;
Qbar <= not D after 5 ns;
end process output;
end architecture behavioral;

9
 Function: Example

function to_bitvector (svalue : std_logic_vector) return bit_vector is

variable outvalue : bit_vector (svalue’length-1 downto 0);
begin
for i in svalue’range loop -- scan all elements of the array
case svalue (i) is
when ‘0’ => outvalue (i) := ‘0’;
when ‘1’ => outvalue (i) := ‘1’;
when others => outvalue (i) := ‘0’;
end case;
end loop;
return outvalue;
end to_bitvector

• A common use of functions: type conversion

• Use of attributes for flexible function definitions
– Data size is determined at the time of the call
• Browse the vendor supplied packages for many examples
10
 Revisit the resolution functions

driver

signal type is a resolved type

driver

• Resolution function is invoked whenever an event occurs

on this signal
11
 Procedures

Procedures allow decomposition of large behaviors

into modular sections. In contrast to a function, a
procedure can return zero or more values using mode
out and inout.

Procedures can be used in

sequential statement areas of a process
concurrent area of an architecture

12
 Essentials of Procedures
procedure read_v1d (variable f: in text; v :out std_logic_vector)
--declarative region: declare variables local to the procedure
--
begin
-- body
--
end read_v1d;

• Parameters may be of mode in (read only) and out (write

only)
• Default class of input parameters is constant
• Default class of output parameters is variable
• Variables declared within procedure are initialized on
each call

13
 Procedures: Placement

architecture behavioral of cpu is

--
-- declarative region
visible to all
-- procedures can be placed in their entirety here
processes
--
begin
process_a: process
visible only within
-- declarative region of a process
process_a
-- procedures can be placed here
begin
--
-- process body
--
end process_a;
process_b: process visible only within
--declarative regions process_b
begin
-- process body
end process_b;
end architecture behavioral;
14
 Placement of Procedures

Architecture
visible in processes
procedure W
A, B & C

process A process B process C

procedure X procedure Y procedure Z

visible only in
process A

• Placement of procedures determines visibility in its usage

15
 Procedures and Signals

procedure mread (address : in std_logic_vector (2 downto 0);

signal R : out std_logic;
signal S : in std_logic;
signal ADDR : out std_logic_vector (2 downto 0);
signal data : out std_logic_vector (31 downto 0)) is
begin
ADDR <= address;
R <= ‘1’;
wait until S = ‘1’;
data <= DO;
R <= ‘0’;
end mread;

• Procedures can make assignments to signals passed as input

parameters
• Procedures may not have a wait statement if the encompassing
process has a sensitivity list
16
 Procedures and Signals

procedure mread (address : in std_logic_vector (2 downto 0);

signal R : out std_logic;
signal S : in std_logic;
signal ADDR : out std_logic_vector (2 downto 0);
signal data : out std_logic_vector (31 downto 0)) is
begin
ADDR <= address;
R <= ‘1’;
wait until S = ‘1’;
data <= DO;
R <= ‘0’;
end mread;

• Procedures may modify signals not in the parameter list, e.g., ports
• Procedures may make assignments to signals not declared in the
parameter list

17
 Concurrent vs. Sequential Procedure Calls

a z
b Combinational
Logic
carry

Q D

Q Clk

ab/s
11/0
00/0 01/0
01/1 0 1 10/0
10/1 11/1
00/1

• Example: bit serial adder

18
 Concurrent Procedure Calls

architecture structural of serial_adder is

component comb signal s1, s2 : std_logic;
port (a, b, c_in : in std_logic; begin
z, carry : out std_logic); C1: comb port map (a => a, b => b,
end component; c_in => s1, z =>z, carry => s2);
procedure dff(signal d, clk, reset : in std_logic; --
signal q, qbar : out std_logic) is -- concurrent procedure call
begin --
if (reset = ‘0’) then dff(clk => clk, reset =>reset, d=> s2,
q <= ‘0’ after 5 ns; q=>s1, qbar =>open);
qbar <= ‘1’ after 5 ns; end architectural structural;
elsif (rising_edge(clk)) then
q <= d after 5 ns;
qbar <= (not D) after 5 ns;
end if;
end dff;

• Variables cannot be passed into a concurrent procedure call

• Explicit vs. positional association of formal and actual parameters 19
 Equivalent Sequential Procedure Call

architecture structural of serial_adder is

component comb signal s1, s2 : std_logic;
port (a, b, c_in : in std_logic; begin
z, carry : out std_logic); C1: comb port map (a => a, b => b,
end component; c_in => s1, z =>z, carry => s2);
procedure dff(signal d, clk, reset : in std_logic; --
signal q, qbar : out std_logic) is -- sequential procedure call
begin --
if (reset = ‘0’) then process
q <= ‘0’ after 5 ns; begin
qbar <= ‘1’ after 5 ns; dff(clk => clk, reset =>reset, d=> s2,
elsif (clk’event and clk = ‘1’) then q=>s1, qbar =>open);
q <= d after 5 ns; wait on clk, reset,s2;
qbar <= (not D) after 5 ns; end process;
end if; end architecture structural;
end dff;

20
 Subprogram Overloading

• Overloading: two or more subprograms with the same

name.

function COUNT (ORANGES : INTEGER) return INTEGER;

function COUNT (APPLES : BIT) return INTEGER;

Both functions are overloaded since they have the same name,
COUNT. When a call to either function is made, it is possible to
identify the exact function to which the call is made from the type
of actuals passed.

COUNT (20)
COUNT (‘1’)
21
 Subprogram Overloading

R
bit_vector
D Q
D Q
Clk Q
Clk Q

R S
std_logic_vector R
D Q
D Q
Clk Q
Clk Q

S
S

• Hardware components differ in number of inputs and the

type of input signals
• Model each component by a distinct procedure
• Procedure naming becomes tedious
22
 Subprogram Overloading

• Consider the following procedures for the previous components

dff_bit (clk, d, q, qbar)
asynch_dff_bit (clk, d,q,qbar,reset,clear)
dff_std (clk,d,q,qbar)
asynch_dff_std (clk, d,q,qbar,reset,clear)

• All of the previous components can use the same name 

subprogram overloading

• The proper procedure can be determined based on the arguments of

the call

23
 Hiding

architecture HIDING of DUMMY_ENTITY is

function ADD (A, B : BIT_VECTOR) return BIT_VECTOR is
begin
-- body of function here.
end ADD;
begin
SUM_IN_ARCH <= ADD (IN1, IN2);
process
function ADD (C, D : BIT_VECTOR) return BIT_VECTOR is
begin
-- body of function here.
end ADD;
begin
SUM_IN_PROCESS <= ADD (IN1, IN2) ;
SUM_IN_ARCH <= HIDING.ADD (IN1, IN2);
end process; 24
end HIDING;
 Use package

package P1 is
function ADD (A, B : BIT_VECTOR) return BIT_VECTOR;
end P1;

package P2 is
function ADD (X, Y : BIT_VECTOR) return BIT_VECTOR;
end P2;

use WORK.P1.all, WORK.P2.all;

architecture OVERLOADED of DUMMY_ENTITY is
begin
SUM_CORRECT <= ADD (X => IN1, Y => IN2);
SUM_ERROR <= ADD (IN1, IN2); -- this will give an error: ambiguious
end OVERLOADED;

25
 Operator overloading

When a standard operator symbol is made to behave differently based on the

type of its operands, the operator is said to be overloaded.

for instance, and operation is defined for arguments of type BIT and
BOOLEAN, and for one-dimensional arrays of BIT and BOOLEAN only.

so, what if the arguments were of type MVL (where MVL is a user defined
enumeration type with values ‘U’, ‘0’, ‘1’ and ‘Z’?)
It is possible to augment the and operation as a function that operates on
arguments of type MVL – the and operator is then said to be overloaded.

26
 Operator overloading

type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);

function “and” (L, R : MVL) return MVL;
function “or” (L, R : MVL) return MVL;
function “not” (R : MVL) return MVL;
-- note: since and, or and not operators are predefined operator symbols, they
have to be enclosed within double quotes when used as overloaded operator
function names.
example:
signal A, B, C : MVL;
signal X, Y, Z : BIT;
A <= ‘Z’ OR ‘1’; --- refer to the overloaded operator
B <= “or” (‘0’, ‘Z’); --- function call notion
X <= not Y; -- refer to predefined operator
Z <= X and Y; -- refer to predefined operator
C <= (A or B) and (not C); -- refer to the overloaded operator
Z <= (X and Y) or A; -- this is error: 27
 Default values for parameters

function MY_AND (A : in BIT := ‘0’, B : in BIT := ‘1’) return BIT;

Examples to call this function

… MY_AND() …
-- formal parameters A and B have the default values of ‘0’ and ‘1’
--respectively;
… MY_AND (B => SIG_P) …
-- SIG_P is passed in as the value for B, since no actual is specified for
-- A, A has its default value ‘0’
… MY_AND (B => SIG_P, A => SIG_Q) …
-- both the default values are ignored since actuals are explicitly
-- specified
… MY_AND (A => SIG_Q, B => open)…
-- using keyword open as an actual is equivalent to not specifying a value, thus,
-- B has a default value of ‘1’.

28
 Reference

The lectures notes and pictures are based on the following sources:

[1] J. Bhasker, A VHDL Primer,3rd edition, J. Bhasker, Prentice Hall, ISBN 0-13-096575-8, 1999
[2] S. Tewksbury, VHDL class notes
http://stewks.ece.stevens-tech.edu/CpE487-S05/
[2] J. V. Spiegel, VHDL tutorial.
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
[3] J. A. Starzyk, VHDL class lecture notes
http://www.ent.ohiou.edu/~starzyk/network/Class/ee515/index.html
[4] S. Yalamanchili, Introductory VHDL: From Simulation to Synthesis, Prentice Hall, ISBN 0-13-
080982-9, 2001.
[5] S. Yalamanchili, VHDL: A Starter's Guide,, Prentice Hall, ISBN: 0-13-145735-7, 2005.
[6] V. A. Pedroni, Circuit Design with VHDL,, MIT Press, ISBN: 0-262-16224-5, 2004.
[7] K. C. Chang, Digital Design and Modeling with VHDL and Synthesis, , IEEE Computer Society
Press, ISBN: 0-8186-7716-3, 1997
[8] J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital integrated circuits- a design perspective, 2nd
edition, prentice hall.

29