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Features
· Operating voltage: 2.4V~5.5V · Partial page write allowed
· Low power consumption · 16-byte page write modes
- Operation: 5mA max. · Write operation with built-in timer
- Standby: 5mA max. · Hardware controlled write protection
· Internal organization: 512´8 · 40-year data retention
· 2-wire serial interface · 106 erase/write cycles per word
· Write cycle time: 5ms max. · Commerical temperature range: 0°C to +70°C
· Automatic erase-before-write operation · 8-pin DIP/SOP/TSSOP package
General Description
The HT24LC04 is a 4K-bit serial read/write non-volatile low power and low voltage operation are essential. Up
memory device using the CMOS floating gate process. to four HT24LC04 devices may be connected to the
Its 4096 bits of memory are organized into 512 words same two-wire bus. The HT24LC04 is guaranteed for
and each word is 8 bits. The device is optimized for use 1M erase/write cycles and 40-year data retention.
in many industrial and commercial applications where
A 0 1 8 V C C
S C L I/O H V P u m p A 1 2 7 W P
C o n tro l
S D A L o g ic A 2 3 6 S C L
V S S 4 5 S D A
X
D E E P R O M H T 2 4 L C 0 4
M e m o ry E A rra y 8 D IP -A /S O P -A /T S S O P -A
W P C o n tro l
C
L o g ic
P a g e B u f
Y D E C
A d d re s s
A 0 ~ A 2 S e n s e A M P
C o u n te r
R /W C o n tro l
V C C
V S S
Pin Description
Pin No. Pin Name I/O Description
1~3 A0~A2 I Address inputs
4 VSS ¾ Negative power supply
5 SDA I/O Serial data inputs/output
6 SCL I Serial clock data input
7 WP I Write protect
8 VCC ¾ Positive power supply
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage ¾ ¾ 2.4 ¾ 5.5 V
ICC1 Operating Current 5V Read at 100kHz ¾ ¾ 2 mA
ICC2 Operating Current 5V Write at 100kHz ¾ ¾ 5 mA
VIL Input Low Voltage ¾ ¾ -1 ¾ 0.3VCC V
VIH Input High Voltage ¾ ¾ 0.7VCC ¾ VCC+0.5 V
VOL Output Low Voltage 2.4V IOL=2.1mA ¾ ¾ 0.4 V
ILI Input Leakage Current 5V VIN=0 or VCC ¾ ¾ 1 mA
ILO Output Leakage Current 5V VOUT=0 or VCC ¾ ¾ 1 mA
ISTB1 Standby Current 5V VIN=0 or VCC ¾ ¾ 5 mA
ISTB2 Standby Current 2.4V VIN=0 or VCC ¾ ¾ 4 mA
CIN Input Capacitance (See Note) ¾ f=1MHz 25°C ¾ ¾ 6 pF
COUT Output Capacitance (See Note) ¾ f=1MHz 25°C ¾ ¾ 8 pF
Note: These parameters are periodically sampled but not 100% tested
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.4V to 5.5V
For relative timing, refer to timing diagrams
Functional Description
· Serial clock (SCL) VSS. When the write protect pin is connected to Vcc,
The SCL input is used for positive edge clock data into the write protection feature is enabled and operates
each EEPROM device and negative edge clock data as shown in the following table.
out of each device. WP Pin Status Protect Array
· Serial data (SDA) At VCC Full Array (4K)
The SDA pin is bidirectional for serial data transfer. At VSS Normal Read/Write Operations
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector Memory organization
devices.
· HT24LC04, 4K Serial EEPROM
· A0, A1, A2 Internally organized with 512 8-bit words, random
The HT24LC04 uses the A2 and A1 inputs for hard word addressing requires a 9-bit data word address.
wire addressing and a total of four 4K devices may be
addressed on a single bus system. The A0 pin is not Device operations
connected. (The device addressing is discussed in · Clock and data transition
detail under the Device Addressing section).
Data transfer may be initiated only when the bus is not
· Write protect (WP) busy. During data transfer, the data line must remain
The HT24LC04 has a write protect pin that provides stable whenever the clock line is high. Changes in
hardware data protection. The write protect pin allows data line while the clock line is high will be interpreted
normal read/write operations when connected to the as a START or STOP condition.
· Start condition The 8th bit of device address is the read/write operation
A high-to-low transition of SDA with SCL high is a start select bit. A read operation is initiated if this bit is high
condition which must precede any other command and a write operation is initiated if this bit is low.
(refer to Start and Stop Definition Timing diagram). If the comparison of the device address succeed the
· Stop condition EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
1 0 1 0 A 2 A 1 A 0 R /W
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram). D e v ic e A d d r e s s
· Acknowledge
Write operations
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The · Byte write
EEPROM sends a zero to acknowledge that it has re- A write operation requires an 8-bit data word address
ceived each word. This happens during the ninth following the device address word and acknowledg-
clock cycle. ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
D a ta a llo w e d
to c h a n g e 8-bit data word. After receiving the 8-bit data word, the
S D A EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
S C L EEPROM enters an internally-timed write cycle to the
S ta rt A d d re s s o r S to p
c o n d itio n a c k n o w le d g e c o n d itio n non-volatile memory. All inputs are disabled during
v a lid this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
Device addressing
· Page write
The 4K EEPROM devices require an 8-bit device ad- The 4K device is capable of 16-byte page writes.
dress word following a start condition to enable the chip
A page write is initiated the same as byte write, but the
for a read or write operation. The device address word
microcontroller does not send a stop condition after
consist of a mandatory one, zero sequence for the first
the first data word is clocked in. Instead, after the
four most significant bits (refer to diagram showing the
EEPROM acknowledges the receipt of the first data
Device Address). This is common to all the EEPROM
word, the microcontroller can transmit up to fifteen
device.
more data words. The EEPROM will respond with a
The next three bits are the A2, A1 and A0 device ad-
ze r o a f t e r e a ch d a t a w o r d r e ce i ve d . T h e
dress bits for the 1K/2K EEPROM. These three bits
microcontroller must terminate the page write se-
must compare to their corresponding hard-wired input
quence with a stop condition.
pins.
The data word address lower four bits are internally in-
The 4K EEPROM only use the A2 and A1 device ad- cremented following the receipt of each data word.
dress bits with the third bit as a memory page address The higher data word address bits are not incre-
bit. The two device address bits must compare to their mented, retaining the memory page row location (re-
corresponding hardwired input pins. The A0 pin is not fer to Page write timing).
connected.
D e v ic e a d d r e s s W o rd a d d re s s D A T A
S D A S A 2 A 1 A 0 P
S ta rt R /W A C K A C K
A C K
S to p
D e v ic e a d d r e s s W o rd a d d re s s D A T A n D A T A n + 1 D A T A n + x
S D A S P
S ta rt A C K A C K A C K A C K
S t
Page write timing
D e v ic e a d d r e s s D A T A
S to p
S D A S A 2 A 1 A 0 P
S ta rt A C K N o A C K
D e v ic e a d d r e s s W o rd a d d re s s D e v ic e a d d r e s s D A T A
S to p
S D A S A 2 A 1 A 0 S P
A C K A C K A C K N o A C K
S ta rt S ta rt
· Sequential read words. When the memory address limit is reached, the
Sequential reads are initiated by either a current ad- data word address will roll over and the sequential read
dress read or a random address read. After the continues. The sequential read operation is terminated
microcontroller receives a data word, it responds with an when the microcontroller does not respond with a zero
acknowledgment. As long as the EEPROM receives an but generates a following stop condition (refer to Se-
acknowledgment, it will continue to increment the data quential read timing).
word address and serially clock out sequential data
D e v ic e a d d r e s s D A T A n D A T A n + 1 D A T A n + x
S D A S P
S ta rt A C K A C K A C K
S to p
Timing Diagrams
tF tH IG H
tR
S C L tL O W
tS U :S T A tH D :S T A tS U :D A T
tH D :D A T
tS U :S T O
S D A tS P
tB U F
tA A
S D A
V a lid V a lid
O U T
S C L
S D A 8 th b it A C K
W o rd n tW R
S to p S ta rt
C o n d itio n C o n d itio n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Package Information
8-pin DIP (300mil) outline dimensions
8 5
B
1 4
C
D
= I
E G
F
Dimensions in mil
Symbol
Min Nom Max
A 355 ¾ 375
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°
8 5
A B
1 4
C '
G
D H
E F =
Dimensions in mil
Symbol
Min Nom Max
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 189 ¾ 197
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°
E
L
E 1
C G
L 1
D
A A 2
e B A 1
R 0 .1 0 y
(4 C O R N E R S )
Dimensions in mm
Symbol
Min Nom Max
A 1.05 ¾ 1.20
A1 0.05 ¾ 0.15
A2 0.95 ¾ 1.05
B ¾ 0.25 ¾
C 0.11 ¾ 0.15
D 2.90 ¾ 3.10
E 6.20 ¾ 6.60
E1 4.30 ¾ 4.50
e ¾ 0.65 ¾
L 0.50 ¾ 0.70
L1 0.90 ¾ 1.10
y ¾ ¾ 0.10
q 0° ¾ 8°