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HT48R50A-1/HT48C50-1

I/O Type 8-Bit MCU


Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0013E HT48 & HT46 LCM Interface Design
- HA0021E Using the I/O Ports on the HT48 MCU Series
- HA0055E 2^12 Decoder (8+4 - Corresponds to HT12E)

Features
· Operating voltage: · 4096´15 program memory ROM
fSYS=4MHz: 2.2V~5.5V · 160´8 data memory RAM
fSYS=8MHz: 3.3V~5.5V
· Buzzer driving pair and PFD supported
· Low voltage reset function
· HALT function and wake-up feature reduce power
· 35 bidirectional I/O lines (max.)
consumption
· 1 interrupt input shared with an I/O line
· 6-level subroutine nesting
· 8-bit programmable timer/event counter with overflow
· Up to 0.5ms instruction cycle with 8MHz system clock
interrupt and 8-stage prescaler
at VDD=5V
· 16-bit programmable timer/event counter and over-
· Bit manipulation instruction
flow interrupts
· 15-bit table read instruction
· On-chip RC oscillator, external crystal and RC oscil-
· 63 powerful instructions
lator
· 32768Hz crystal oscillator for timing purposes only · All instructions in one or two machine cycles

· Watchdog Timer · 28-pin SKDIP/SOP, 48-pin SSOP package

General Description
The HT48R50A-1/HT48C50-1 are 8-bit high perfor- The advantages of low power consumption, I/O flexibil-
mance, RISC architecture microcontroller devices spe- ity, timer functions, oscillator options, HALT and
cifically designed for multiple I/O control product wake-up functions, watchdog timer, buzzer driver, as
applications. The mask version HT48C50-1 is fully pin well as low cost, enhance the versatility of these devices
and functionally compatible with the OTP version to suit a wide range of application possibilities such as
HT48R50A-1 device. industrial control, consumer products, subsystem con-
trollers, etc.

Rev. 2.01 1 January 9, 2009


HT48R50A-1/HT48C50-1

Block Diagram

T M R 1 C M
U
M X fS Y S /4
T M R 1 L U
IN T /P G 0 T M R 1 H
X T M R 1

In te rru p t
C ir c u it
T M R 0 C
S T A C K M fS Y S
M P r e s c a le r U
P ro g ra m P ro g ra m IN T C T M R 0 U
R O M C o u n te r X
X T M R 0

P G 0 fS Y S /4
E N /D IS
In s tr u c tio n W D T S
M
R e g is te r M P M D A T A W D T P r e s c a le r W D T U R T C O S C
U M e m o ry X
X

W D T O S C

P A C P O R T A
P A 0 ~ P A 7
In s tr u c tio n M U X P A
D e c o d e r
B Z /B Z
A L U S T A T U S P B C P O R T B
P B 0 ~ P B 7
T im in g S h ifte r P G 1 P B
G e n e ra to r P G 2

P C C P O R T C
P C 0 ~ P C 7
P C
O S C 2 / O S C 1 / A C C
P G 2 P G 1
R E S In te rn a l P D C P O R T D
V D D P D 0 ~ P D 7
R C O S C P D
V S S

P G C P O R T G
P G 0 ~ P G 2
P G

Rev. 2.01 2 January 9, 2009


HT48R50A-1/HT48C50-1

Pin Assignment
P B 5 1 4 8 P B 6
P B 4 2 4 7 P B 7
P A 3 3 4 6 P A 4
P A 2 4 4 5 P A 5
P A 1 5 4 4 P A 6
P A 0 6 4 3 P A 7
P B 3 7 4 2 N C
P B 2 8 4 1 N C
P B 1 /B Z 9 4 0 N C
P B 0 /B Z 1 0 3 9 N C
P B 5 1 2 8 P B 6 N C 1 1 3 8 O S C 2 /P G 2
P B 4 2 2 7 P B 7 N C 1 2 3 7 O S C 1 /P G 1
P A 3 3 2 6 P A 4 N C 1 3 3 6 V D D
P A 2 4 2 5 P A 5 N C 1 4 3 5 R E S
P A 1 5 2 4 P A 6 P D 7 1 5 3 4 T M R 1
P A 0 6 2 3 P A 7 P D 6 1 6 3 3 P D 3
P B 3 7 2 2 O S C 2 /P G 2 P D 5 1 7 3 2 P D 2
P B 2 8 2 1 O S C 1 /P G 1 P D 4 1 8 3 1 P D 1
P B 1 /B Z 9 2 0 V D D V S S 1 9 3 0 P D 0
P B 0 /B Z 1 0 1 9 R E S P G 0 /IN T 2 0 2 9 P C 7
V S S 1 1 1 8 P C 5 /T M R 1 T M R 0 2 1 2 8 P C 6
P G 0 /IN T 1 2 1 7 P C 4 P C 0 2 2 2 7 P C 5
P C 0 /T M R 0 1 3 1 6 P C 3 P C 1 2 3 2 6 P C 4
P C 1 1 4 1 5 P C 2 P C 2 2 4 2 5 P C 3

H T 4 8 R 5 0 A -1 /H T 4 8 C 5 0 -1 -A H T 4 8 R 5 0 A -1 /H T 4 8 C 5 0 -1 -A
2 8 S K D IP -A /S O P -A 4 8 S S O P -A

Pin Description
Pin Name I/O Options Description
Pull-high* Bidirectional 8-bit input/output port. Each bit can be configured as a
Wake-up wake-up input by options. Software instructions determine the CMOS out-
PA0~PA7 I/O
CMOS/Schmitt put or Schmitt trigger or CMOS input with pull-high resistor (determined by
trigger Input pull-high option).
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
PB0/BZ
Pull-high* pull-high option).
PB1/BZ I/O
I/O or BZ/BZ The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once
PB2~PB7
the PB0 and PB1 are selected as buzzer driving outputs, the output signals
come from an internal PFD generator (shared with Timer/Event Counter 0).
Bidirectional I/O lines. Software instructions determine the CMOS output
PD0~PD7 I/O Pull-high* or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tion).
VSS ¾ ¾ Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
PG0/INT I/O Pull-high*
tion). This external interrupt input is pin-shared with PG0. The external in-
terrupt input is activated on a high to low transition.
TMR0 I ¾ Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor)
Bidirectional I/O lines. Software instructions determine the CMOS output
PC0~PC7 I/O Pull-high* or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tion).
TMR1 I ¾ Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor)

Rev. 2.01 3 January 9, 2009


HT48R50A-1/HT48C50-1

Pin Name I/O Options Description


RES I ¾ Schmitt trigger reset input. Active low

VDD ¾ ¾ Positive power supply


OSC1, OSC2 are connected to an RC network or Crystal (determined by
option) for the internal system clock. In the case of RC operation, OSC2 is
Pull-high* the output terminal for 1/4 system clock. These two pins can also be
Crystal optioned as an RTC oscillator (32768Hz) or I/O lines. In these two cases,
OSC1/PG1 I
or RC the system clock comes from an internal RC oscillator whose frequency
OSC2/PG2 O
or Int. RC+I/O has 4 options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O option is se-
or Int. RC+RTC lected, the pull-high option can also be enabled or disabled. Otherwise the
PG1 and PG2 are used as internal registers (pull-high resistors are always
disabled).

Note: * The pull-high resistors of each I/O port (PA, PB, PC, PD, PG) are controlled by options.

Absolute Maximum Ratings


Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ fSYS=4MHz 2.2 ¾ 5.5 V


VDD Operating Voltage
¾ fSYS=8MHz 3.3 ¾ 5.5 V

Operating Current 3V ¾ 1 2 mA
IDD1 No load, fSYS=4MHz
(Crystal OSC, RC OSC) 5V ¾ 2.5 5 mA
Operating Current
IDD23 5V No load, fSYS=8MHz ¾ 4 8 mA
(Crystal OSC, RC OSC)

Standby Current 3V ¾ ¾ 5 mA
ISTB1 No load, system HALT
(WDT OSC Enabled RTC Off) 5V ¾ ¾ 10 mA

Standby Current 3V ¾ ¾ 1 mA
ISTB2 No load, system HALT
(WDT OSC Disabled RTC Off) 5V ¾ ¾ 2 mA

Standby Current 3V ¾ ¾ 5 mA
ISTB3 No load, system HALT
(WDT OSC Disabled, RTC On) 5V ¾ ¾ 10 mA
VIL1 Input Low Voltage for I/O Ports ¾ ¾ 0 ¾ 0.3VDD V
VIH1 Input High Voltage for I/O Ports ¾ ¾ 0.7VDD ¾ VDD V
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ LVR enabled 2.7 3.0 3.3 V

3V VOL=0.1VDD 4 8 ¾ mA
IOL I/O Port Sink Current
5V VOL=0.1VDD 10 20 ¾ mA

Rev. 2.01 4 January 9, 2009


HT48R50A-1/HT48C50-1

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
3V VOH=0.9VDD -2 -4 ¾ mA
IOH I/O Port Source Current
5V VOH=0.9VDD -5 -10 ¾ mA

3V ¾ 20 60 100 kW
RPH Pull-high Resistance
5V ¾ 10 30 50 kW

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ 2.2V~5.5V 400 ¾ 4000 kHz


fSYS1 System Clock (Crystal OSC)
¾ 3.3V~5.5V 400 ¾ 8000 kHz

¾ 2.2V~5.5V 400 ¾ 4000 kHz


fSYS2 System Clock (RC OSC)
¾ 3.3V~5.5V 400 ¾ 8000 kHz

3.2MHz 1800 ¾ 5400 kHz

System Clock 1.6MHz 900 ¾ 2700 kHz


fSYS3 5V
(Internal RC OSC) 800kHz 450 ¾ 1350 kHz

400kHz 225 ¾ 675 kHz

¾ 2.2V~5.5V 0 ¾ 4000 kHz


fTIMER Timer I/P Frequency (TMR)
¾ 3.3V~5.5V 0 ¾ 8000 kHz

3V ¾ 45 90 180 ms
tWDTOSC Watchdog Oscillator Period
5V ¾ 32 65 130 ms

Watchdog Time-out Period 3V Without WDT 11 23 46 ms


tWDT1
(WDT OSC) 5V prescaler 8 17 33 ms
Watchdog Time-out Period Without WDT
tWDT2 ¾ ¾ 1024 ¾ *tSYS
(System Clock) prescaler
Watchdog Time-out Period Without WDT
tWDT3 ¾ ¾ 7.812 ¾ ms
(RTC OSC) prescaler
External Reset Low Pulse
tRES ¾ ¾ 1 ¾ ¾ ms
Width
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ tSYS

tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms

Note: *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3

Rev. 2.01 5 January 9, 2009


HT48R50A-1/HT48C50-1

Functional Description
Execution Flow When executing a jump instruction, conditional skip ex-
The system clock for the microcontroller is derived from ecution, loading PCL register, subroutine call, initial re-
either a crystal or an RC oscillator. The system clock is set, internal interrupt, external interrupt or return from
internally divided into four non-overlapping clocks. One subroutine, the PC manipulates the program transfer by
instruction cycle consists of four system clock cycles. loading the address corresponding to each instruction.

Instruction fetching and execution are pipelined in such The conditional skip is activated by instructions. Once
a way that a fetch takes an instruction cycle while de- the condition is met, the next instruction, fetched during
coding and execution takes the next instruction cycle. the current instruction execution, is discarded and a
However, the pipelining scheme causes each instruc- dummy cycle replaces it to get the proper instruction.
tion to effectively execute in a cycle. If an instruction Otherwise proceed with the next instruction.
changes the program counter, two cycles are required to The lower byte of the program counter (PCL) is a read-
complete the instruction. able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
Program Counter - PC within 256 locations.
The program counter (PC) controls the sequence in
When a control transfer takes place, an additional
which the instructions stored in the program ROM are
dummy cycle is required.
executed and its contents specify a full range of pro-
gram memory. Program Memory - ROM
After accessing a program memory word to fetch an in- The program memory is used to store the program in-
struction code, the contents of the program counter are structions which are to be executed. It also contains
incremented by one. The program counter then points to data, table, and interrupt entries, and is organized into
the memory word containing the next instruction code. 4096´15 bits, addressed by the program counter and ta-
ble pointer.

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k

O S C 2 ( R C o n ly )

P C P C P C + 1 P C + 2

F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )

Execution Flow

Program Counter
Mode
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 1 0 0 0
Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 0 1 1 0 0
Skip Program Counter+2
Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *11~*0: Program counter bits S11~S0: Stack register bits


#11~#0: Instruction code bits @7~@0: PCL bits

Rev. 2.01 6 January 9, 2009


HT48R50A-1/HT48C50-1

0 0 0 H · Table location
D e v ic e In itia liz a tio n P r o g r a m
Any location in the ROM space can be used as
0 0 4 H look-up tables. The instructions ²TABRDC [m]² (the
E x te r n a l In te r r u p t S u b r o u tin e
current page, one page=256 words) and ²TABRDL
0 0 8 H
T im e r /E v e n t C o u n te r 0 [m]² (the last page) transfer the contents of the
In te r r u p t S u b r o u tin e
0 0 C H
lower-order byte to the specified data memory, and
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e the higher-order byte to TBLH (08H). Only the desti-
P ro g ra m nation of the lower-order byte in the table is
M e m o ry well-defined, the other bits of the table word are trans-
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s ) ferred to the lower portion of TBLH, and the remaining
n F F H 1-bit words are read as ²0². The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the lo-
L o o k - u p T a b le ( 2 5 6 w o r d s ) cation must be placed in the TBLP. The TBLH is read
F F F H
1 5 b its only and cannot be restored. If the main routine and
N o te : n ra n g e s fro m 0 to F the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
Program Memory main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
Certain locations in the program memory are reserved
words, using the table read instruction in the main rou-
for special usage:
tine and the ISR simultaneously should be avoided.
· Location 000H However, if the table read instruction has to be applied
This area is reserved for program initialization. After in both the main routine and the ISR, the interrupt is
chip reset, the program always begins execution at lo- supposed to be disabled prior to the table read in-
cation 000H. struction. It will not be enabled until the TBLH has
· Location 004H been backed up. All table related instructions require
This area is reserved for the external interrupt service two cycles to complete the operation. These areas
program. If the INT input pin is activated, the interrupt may function as normal program memory depending
is enabled and the stack is not full, the program begins upon the requirements.
execution at location 004H.
Stack Register - STACK
· Location 008H
This is a special part of the memory which is used to
This area is reserved for the Timer/Event Counter 0 in-
save the contents of the Program Counter only. The
terrupt service program. If a timer interrupt results from a
stack is organized into 6 levels and is neither part of the
Timer/Event Counter 0 overflow, and if the interrupt is
data nor part of the program space, and is neither read-
enabled and the stack is not full, the program begins ex-
able nor writeable. The activated level is indexed by the
ecution at location 008H.
stack pointer (SP) and is neither readable nor writeable.
· Location 00CH At a subroutine call or interrupt acknowledge signal, the
This location is reserved for the Timer/Event Counter contents of the program counter are pushed onto the
1 interrupt service program. If a timer interrupt results stack. At the end of a subroutine or an interrupt routine,
from a Timer/Event Counter 1 overflow, and the inter- signaled by a return instruction (RET or RETI), the pro-
rupt is enabled and the stack is not full, the program gram counter is restored to its previous value from the
begins execution at location 00CH. stack. After a chip reset, the SP will point to the top of the
stack.

Table Location
Instruction
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: *11~*0: Table location bits P11~P8: Current program counter bits
@7~@0: Table pointer bits

Rev. 2.01 7 January 9, 2009


HT48R50A-1/HT48C50-1

If the stack is full and a non-masked interrupt takes 0 0 H In d ir e c t A d d r e s s in g R e g is te r 0


place, the interrupt request flag will be recorded but the 0 1 H M P 0
acknowledge signal will be inhibited. When the stack 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
pointer is decremented (by RET or RETI), the interrupt 0 3 H M P 1
will be serviced. This feature prevents stack overflow al- 0 4 H
lowing the programmer to use the structure more easily. 0 5 H A C C
In a similar case, if the stack is full and a ²CALL² is sub- 0 6 H P C L
sequently executed, stack overflow occurs and the first 0 7 H T B L P
0 8 H T B L H
entry will be lost (only the most recent 6 return ad-
0 9 H W D T S
dresses are stored).
0 A H S T A T U S
0 B H IN T C
Data Memory - RAM
0 C H S p e c ia l P u r p o s e
The data memory is designed with 184´8 bits. The 0 D H T M R 0 D A T A M E M O R Y
data memory is divided into two functional groups: spe- 0 E H T M R 0 C
cial function registers and general purpose data mem- 0 F H T M R 1 H
ory (160´8). Most are read/write, but some are read 1 0 H T M R 1 L
only. 1 1 H T M R 1 C
1 2 H P A
The special function registers include the indirect ad-
1 3 H P A C
dressing registers (00H, 02H), Timer/Event Counter 0
1 4 H P B
(TMR0;0DH), Timer/Event Counter 0 control register
1 5 H P B C
(TMR0C;0EH), Timer/Event Counter 1 higher-order
1 6 H P C
byte register (TMR1H;0FH), Timer/Event Counter 1
1 7 H P C C
lower-order byte register (TMR1L;10H), Timer/Event
1 8 H P D
Counter 1 control register (TMR1C;11H), Program
1 9 H P D C
counter lower-order byte register (PCL;06H), Memory 1 A H : U n u s e d
pointer registers (MP0;01H, MP1;03H), Accumulator 1 B H
R e a d a s "0 0 "
(ACC;05H), Table pointer (TBLP;07H), Table 1 C H
higher-order byte register (TBLH;08H), Status register 1 D H
(STATUS;0AH), Interrupt control register (INTC;0BH), 1 E H P G
Watchdog Timer option setting register (WDTS;09H), 1 F H P G C
I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, 2 0 H
PG;1EH) and I/O control registers (PAC;13H, 5 F H
PBC;15H, PCC;17H, PDC;19H, PGC;1FH). The re- 6 0 H
maining space before the 60H is reserved for future ex- G e n e ra l P u rp o s e
panded usage and reading these locations will get D A T A M E M O R Y
(1 6 0 B y te s )
²00H². The general purpose data memory, addressed
from 60H to FFH, is used for data and control informa- F F H
tion under instruction commands. RAM Mapping
All of the data memory areas can handle arithmetic,
Accumulator
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the The accumulator is closely related to ALU operations. It
data memory can be set and reset by ²SET [m].i² and is also mapped to location 05H of the data memory and
²CLR [m].i². They are also indirectly accessible through can carry out immediate data operations. The data
memory pointer registers (MP0 or MP1). movement between two data memory locations must
pass through the accumulator.
Indirect Addressing Register
Arithmetic and Logic Unit - ALU
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op- This circuit performs 8-bit arithmetic and logic operations.
eration of [00H] ([02H]) will access data memory pointed The ALU provides the following functions:
to by MP0 (MP1). Reading location 00H (02H) itself indi- · Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
rectly will return the result 00H. Writing indirectly results · Logic operations (AND, OR, XOR, CPL)
in no operation. · Rotation (RL, RR, RLC, RRC)

The memory pointer registers (MP0 and MP1) are 8-bit · Increment and Decrement (INC, DEC)

registers. · Branch decision (SZ, SNZ, SIZ, SDZ ....)


The ALU not only saves the results of a data operation but
also changes the status register.

Rev. 2.01 8 January 9, 2009


HT48R50A-1/HT48C50-1

Status Register - STATUS rupt requires servicing within the service routine, the
This 8-bit register (0AH) contains the zero flag (Z), carry EMI bit and the corresponding bit of the INTC may be set
flag (C), auxiliary carry flag (AC), overflow flag (OV), to allow interrupt nesting. If the stack is full, the interrupt
power down flag (PDF), and watchdog time-out flag request will not be acknowledged, even if the related in-
(TO). It also records the status information and controls terrupt is enabled, until the SP is decremented. If immedi-
the operation sequence. ate service is desired, the stack must be prevented from
becoming full.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like All these kinds of interrupts have a wake-up capability.
most other registers. Any data written into the status As an interrupt is serviced, a control transfer occurs by
register will not change the TO or PDF flag. In addi- pushing the program counter onto the stack, followed by
tion operations related to the status register may give a branch to a subroutine at specified location in the pro-
different results from those intended. The TO flag gram memory. Only the program counter is pushed onto
can be affected only by system power-up, a WDT the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
time-out or executing the ²CLR WDT² or ²HALT² in-
which corrupts the desired control sequence, the con-
struction. The PDF flag can be affected only by exe-
tents should be saved in advance.
cuting the ²HALT² or ²CLR WDT² instruction or
during a system power-up. External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
The Z, OV, AC and C flags generally reflect the status of
bit 4 of INTC) will be set. When the interrupt is enabled,
the latest operations.
the stack is not full and the external interrupt is active, a
In addition, on entering the interrupt sequence or exe- subroutine call to location 04H will occur. The interrupt
cuting the subroutine call, the status register will not be request flag (EIF) and EMI bits will be cleared to disable
pushed onto the stack automatically. If the contents of other interrupts.
the status are important and if the subroutine can cor-
The internal Timer/Event Counter 0 interrupt is initial-
rupt the status register, precautions must be taken to
ized by setting the Timer/Event Counter 0 interrupt re-
save it properly.
quest flag (T0F; bit 5 of INTC), caused by a timer 0
Interrupt overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
The device provides an external interrupt and internal
08H will occur. The related interrupt request flag (T0F)
timer/event counter interrupts. The Interrupt Control
will be reset and the EMI bit cleared to disable further in-
Register (INTC;0BH) contains the interrupt control bits
terrupts.
to set the enable or disable and the interrupt request
flags. The internal timer/even counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
Once an interrupt subroutine is serviced, all the other in-
flag (;bit 6 of INTC), caused by a timer 1 overflow. When
terrupts will be blocked (by clearing the EMI bit). This
the interrupt is enabled, the stack is not full and the T1F
scheme may prevent any further interrupt nesting. Other
is set, a subroutine call to location 0CH will occur. The
interrupt requests may occur during this interval but only
related interrupt request flag (T1F) will be reset and the
the interrupt request flag is recorded. If a certain inter-
EMI bit cleared to disable further interrupts.
Bit No. Label Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
0 C take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
1 AC
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
3 OV
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
4 PDF
PDF is set by executing the ²HALT² instruction.
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
5 TO
TO is set by a WDT time-out.
6~7 ¾ Unused bit, read as ²0²

Status (0AH) Register

Rev. 2.01 9 January 9, 2009


HT48R50A-1/HT48C50-1

Bit No. Label Function


0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled)
1 EEI Controls the external interrupt (1= enabled; 0= disabled)
2 ET0I Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3 ET1I Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
4 EIF External interrupt request flag (1= active; 0= inactive)
5 T0F Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6 T1F Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
7 ¾ Unused bit, read as ²0²

INTC (0BH) Register

During the execution of an interrupt subroutine, other in- Oscillator configuration


terrupt acknowledge signals are held until the ²RETI² in- There are 3 oscillator circuits in the microcontroller.
struction is executed or the EMI bit and the related V D D

interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an in- O S C 1 O S C 1
terrupt service, but RET will not. 4 7 0 p F

Interrupts, occurring in the interval between the rising


O S C 2 fS Y S /4 O S C 2
edges of two consecutive T2 pulses, will be serviced on N M O S O p e n D r a in
the latter of the two T2 pulses, if the corresponding inter- C r y s ta l O s c illa to r R C O s c illa to r
( In c lu d e 3 2 7 6 8 H z )
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied. System Oscillator
These can be masked by resetting the EMI bit.
All of them are designed for system clocks, namely the
No. Interrupt Source Priority Vector external RC oscillator, the external Crystal oscillator and
a External Interrupt 1 04H the internal RC oscillator, which are determined by op-
tions. No matter what oscillator type is selected, the sig-
b Timer/Event Counter 0 Overflow 2 08H
nal provides the system clock. The HALT mode stops
c Timer/Event Counter 1 Overflow 3 0CH the system oscillator and ignores an external signal to
The Timer/Event Counter 0/1 interrupt request flag conserve power.
(T0F/T1F), external interrupt request flag (EIF), enable If an RC oscillator is used, an external resistor between
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en- OSC1 and VDD is required and the resistance must
able external interrupt bit (EEI) and enable master inter- range from 24kW to 1MW. The system clock, divided by
rupt bit (EMI) constitute an interrupt control register 4, is available on OSC2, which can be used to synchro-
(INTC) which is located at 0BH in the data memory. EMI, nize external logic. The RC oscillator provides the most
EEI, ET0I and ET1I are used to control the enabling or cost effective solution. However, the frequency of oscil-
disabling of interrupts. These bits prevent the requested lation may vary with VDD, temperatures and the chip it-
interrupt from being serviced. Once the interrupt request self due to process variations. It is, therefore, not
flags (T0F, T1F, EIF) are set, they will remain in the INTC suitable for timing sensitive operations where an accu-
register until the interrupts are serviced or cleared by a rate oscillator frequency is desired.
software instruction.
If the Crystal oscillator is used, a crystal across OSC1
It is recommended that a program does not use the and OSC2 is needed to provide the feedback and phase
²CALL subroutine² within the interrupt subroutine. In- shift required for the oscillator. No other external compo-
terrupts often occur in an unpredictable manner or nents are required. In stead of a crystal, a resonator can
need to be serviced immediately in some applications. also be connected between OSC1 and OSC2 to get a
If only one stack is left and enabling the interrupt is not frequency reference, but two external capacitors in
well controlled, the original control sequence will be dam- OSC1 and OSC2 are required. If the internal RC oscilla-
aged once the ²CALL² operates in the interrupt subrou- tor is used, the OSC1 and OSC2 can be selected as
tine. general I/O lines or an 32768Hz crystal oscillator (RTC

Rev. 2.01 10 January 9, 2009


HT48R50A-1/HT48C50-1

OSC). Also, the frequencies of the internal RC oscillator WS2 WS1 WS0 Division Ratio
can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends 0 0 0 1:1
on the options). 0 0 1 1:2
The WDT oscillator is a free running on-chip RC oscillator, 0 1 0 1:4
and no external components are required. Even if the sys-
0 1 1 1:8
tem enters the power down mode, the system clock is
1 0 0 1:16
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by op- 1 0 1 1:32
tions to conserve power. 1 1 0 1:64
1 1 1 1:128
Watchdog Timer - WDT
WDTS (09H) Register
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), RTC clock or instruction The WDT overflow under normal operation will initialize
clock (system clock divided by 4), determines the op- ²chip reset² and set the status bit ²TO². But in the HALT
tions. This timer is designed to prevent a software mal- mode, the overflow will initialize a ²warm reset² and only
function or sequence from jumping to an unknown the Program Counter and SP are reset to zero. To clear
location with unpredictable results. The Watchdog the contents of WDT (including the WDT prescaler),
Timer can be disabled by options. If the Watchdog Timer three methods are adopted; external reset (a low level to
is disabled, all the executions related to the WDT result RES), software instruction and a ²HALT² instruction.
in no operation. The RTC clock is enabled only in the in- The software instruction include ²CLR WDT² and the
ternal RC+RTC mode. other set - ²CLR WDT1² and ²CLR WDT2². Of these
Once the internal WDT oscillator (RC oscillator with a two types of instruction, only one can be active depend-
period of 65ms at 5V normally) is selected, it is first di- ing on the option - ²CLR WDT times selection option². If
vided by 256 (8-stage) to get the nominal time-out pe- the ²CLR WDT² is selected (i.e. CLRWDT times equal
riod of 17ms at 5V. This time-out period may vary with one), any execution of the ²CLR WDT² instruction will
temperatures, VDD and process variations. By invoking clear the WDT. In the case that ²CLR WDT1² and ²CLR
the WDT prescaler, longer time-out periods can be real- WDT2² are chosen (i.e. CLRWDT times equal two),
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the these two instructions must be executed to clear the
WDTS) can give different time-out periods. If WS2, WDT; otherwise, the WDT may reset the chip as a result
WS1, and WS0 are all equal to 1, the division ratio is up of time-out.
to 1:128, and the maximum time-out period is 2.1s at 5V
seconds. If the WDT oscillator is disabled, the WDT Power Down Operation - HALT
clock may still come from the instruction clock and oper-
The HALT mode is initialized by the ²HALT² instruction
ates in the same manner except that in the HALT state
and results in the following...
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by · The system oscillator will be turned off but the WDT

external logic. The high nibble and bit 3 of the WDTS are oscillator remains running (if the WDT oscillator is se-
reserved for user's defined flags, which can be used to lected).
indicate some specified status. · The contents of the on chip RAM and registers remain
unchanged.
If the device operates in a noisy environment, using the
· WDT and WDT prescaler will be cleared and re-
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-
counted again (if the WDT clock is from the WDT os-
tor (RTC OSC) is strongly recommended, since the HALT cillator).
will stop the system clock.

S y s te m C lo c k /4
W D T P r e s c a le r
R T C O S C
O p tio n 8 - b it C o u n te r 7 - b it C o u n te r
S e le c t
W D T
O S C
8 -to -1 M U X W S 0 ~ W S 2

W D T T im e - o u t

Watchdog Timer

Rev. 2.01 11 January 9, 2009


HT48R50A-1/HT48C50-1

· All of the I/O ports maintain their original status. V D D


· The PDF flag is set and the TO flag is cleared. R E S
tS S T
The system can leave the HALT mode by means of an
S S T T im e - o u t
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset C h ip R e s e t
causes a device initialization and the WDT overflow per-
Reset Timing Chart
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined. V D D

The PDF flag is cleared by system power-up or execut- 0 .0 1 m F *


ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT 1 0 0 k W

time-out occurs, and causes a wake-up that only resets R E S


the Program Counter and SP; the others remain in their 1 0 k W
original status.
0 .1 m F *
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the Reset Circuit
device by options. Awakening from an I/O port stimulus,
Note: ²*² Make the length of the wiring, which is con-
the program will resume execution of the next instruc-
nected to the RES pin as short as possible, to
tion. If it awakens from an interrupt, two sequence may avoid noise interference.
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume H A L T W a rm R e s e t
execution at the next instruction. If the interrupt is en-
W D T
abled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
R E S
²1² before entering the HALT mode, the wake-up func-
C o ld
tion of the related interrupt will be disabled. Once a R e s e t
wake-up event occurs, it takes 1024 tSYS (system clock S S T
O S C 1 1 0 - b it R ip p le
period) to resume normal operation. In other words, a C o u n te r
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal, S y s te m R e s e t
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next Reset Configuration
instruction execution, this will be executed immediately
after the dummy period is finished. TO PDF RESET Conditions

To minimize power consumption, all the I/O pins should 0 0 RES reset during power-up
be carefully managed before entering the HALT status. u u RES reset during normal operation
The RTC oscillator still runs in the HALT mode (if the
0 1 RES wake-up HALT
RTC oscillator is enabled).
1 u WDT time-out during normal operation
Reset
1 1 WDT wake-up HALT
There are three ways in which a reset can occur:
Note: ²u² stands for ²unchanged²
· RES reset during normal operation
· RES reset during HALT To guarantee that the system oscillator is started and
· WDT time-out reset during normal operation stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
The WDT time-out during HALT is different from other
tem reset (power-up, WDT time-out or RES reset) or the
chip reset conditions, since it can perform a ²warm re -
system awakes from the HALT state.
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis- When a system reset occurs, the SST delay is added
ters remain unchanged during other reset conditions. during the reset period. Any wake-up from HALT will en-
able the SST delay.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and An extra option load time delay is added during system
TO flags, the program can distinguish between different reset (power-up, WDT time-out at normal mode or RES
²chip resets². reset).

Rev. 2.01 12 January 9, 2009


HT48R50A-1/HT48C50-1

The functional unit chip reset status are shown below.


Program Counter 000H
Interrupt Disable
Prescaler Clear
WDT Clear. After master reset, WDT begins counting
Timer/Event Counter Off
Input/Output Ports Input mode
Stack Pointer Points to the top of the stack

The states of the registers is summarized in the table.


Reset WDT Time-out RES Reset RES Reset WDT Time-out
Register
(Power-on) (Normal Operation) (Normal Operation) (HALT) (HALT)*
TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---
Program
000H 000H 000H 000H 000H
Counter
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PG ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu
PGC ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu

Note: ²*² stands for ²warm reset²


²u² stands for ²unchanged²
²x² stands for ²unknown²

Rev. 2.01 13 January 9, 2009


HT48R50A-1/HT48C50-1

Timer/Event Counter (can always be optioned) or fRTC (enable only the sys-
Two timer/event counters (TMR0, TMR1) are imple- tem oscillator in the Int. RC+RTC mode) by options.
mented in the microcontroller. The Timer/Event Counter Using external clock input allows the user to count exter-
0 contains an 8-bit programmable count-up counter and nal events, measure time internals or pulse widths, or
the clock may come from an external source or from the generate an accurate time base. While using the inter-
system clock or RTC. nal clock allows the user to generate an accurate time
The Timer/Event Counter 1 contains an 16-bit program- base.
mable count-up counter and the clock may come from The Timer/Event Counter 0 can generate PFD signal by
an external source or from the system clock divided by 4 using external or internal clock and PFD frequency is
or RTC. determine by the equation fINT/[2´(256-N)].
Using the internal clock sources, there are 2 reference There are 2 registers related to the Timer/Event Counter
time-bases for Timer/Event Counter 0. The internal 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers
clock source can be selected as coming from fSYS (can are mapped to TMR0 location; writing TMR0 makes the
always be optioned) or fRTC (enabled only system oscil- starting value be placed in the Timer/Event Counter 0
lator in the Int. RC+RTC mode) by options. preload register and reading TMR0 gets the contents of
the Timer/Event Counter 0. The TMR0C is a timer/event
Using the internal clock sources, there are 2 reference
counter control register, which defines some options.
time-bases for Timer/Event Counter 1. The internal
clock source can be selected as coming from fSYS/4

Bit No. Label Function


To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS/2 or fRTC/2
001: fINT=fSYS/4 or fRTC/4
0 T0PSC0 010: fINT=fSYS/8 or fRTC/8
1 T0PSC1 011: fINT=fSYS/16 or fRTC/16
2 T0PSC2 100: fINT=fSYS/32 or fRTC/32
101: fINT=fSYS/64 or fRTC/64
110: fINT=fSYS/128 or fRTC/128
111: fINT=fSYS/256 or fRTC/256
To define the TMR0 active edge of Timer/Event Counter 0
3 T0E
(0=active on low to high; 1=active on high to low)
4 T0ON To enable or disable timer 0 counting (0=disabled; 1=enabled)
5 ¾ Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external clock)
6 T0M0
10=Timer mode (internal clock)
7 T0M1
11=Pulse width measurement mode
00=Unused

TMR0C (0EH) Register

Bit No. Label Function


0~2, 5 ¾ Unused bit, read as ²0²
To define the TMR1 active edge of Timer/Event Counter 1
3 T1E
(0=active on low to high; 1=active on high to low)
4 T1ON To enable or disable timer 1 counting (0=disabled; 1=enabled)
To define the operating mode
01=Event count mode (external clock)
6 T1M0
10=Timer mode (internal clock)
7 T1M1
11=Pulse width measurement mode
00=Unused

TMR1C (11H) Register

Rev. 2.01 14 January 9, 2009


HT48R50A-1/HT48C50-1

There are 3 registers related to Timer/Event Counter 1; In the pulse width measurement mode with the
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing T0ON/T1ON and T0E/T1E bits equal to one, once the
TMR1L will only put the written data to an internal TMR0/TMR1 has received a transient from low to high
lower-order byte buffer (8 bits) and writing TMR1H will (or high to low if the T0E/T1E bits is ²0²) it will start
transfer the specified data and the contents of the counting until the TMR0/TMR1 returns to the original
lower-order byte buffer to TMR1H and TMR1L preload level and resets the T0ON/T1ON. The measured result
registers, respectively. The Timer/Event Counter 1 will remain in the Timer/Event Counter 0/1 even if the
preload register is changed by each writing TMR1H op- activated transient occurs again. In other words, only
erations. Reading TMR1H will latch the contents of one cycle measurement can be done. Until setting the
TMR1H and TMR1L counters to the destination and the T0ON/T1ON, the cycle measurement will function again
lower-order byte buffer, respectively. Reading the as long as it receives further transient pulse. Note that,
TMR1L will read the contents of the lower-order byte in this operating mode, the Timer/Event Counter 0/1
buffer. The TMR1C is the Timer/Event Counter 1 control starts counting not according to the logic level but ac-
register, which defines the operating mode, counting en- cording to the transient edges. In the case of counter
able or disable and active edge. overflows, the counter 0/1 is reloaded from the
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) bits Timer/Event Counter 0/1 preload register and issues the
define the operating mode. The event count mode is interrupt request just like the other two modes. To en-
used to count external events, which means the clock able the counting operation, the timer ON bit (T0ON: bit
source comes from an external (TMR0/TMR1) pin. The 4 of TMR0C; T1ON: bit 4 of TMR1C) should be set to 1.
timer mode functions as a normal timer with the clock In the pulse width measurement mode, the T0ON/T1ON
source coming from the fINT clock/instruction clock or RTC will be cleared automatically after the measurement cy-
clock (Timer0/Timer1). The pulse width measurement cle is completed. But in the other two modes the
mode can be used to count the high or low level duration of T0ON/T1ON can only be reset by instructions. The
the external signal (TMR0/TMR1). The counting is based overflow of the Timer/Event Counter 0/1 is one of the
on the f INT clock/instruction clock or RTC clock wake-up sources. No matter what the operation mode
(Timer0/Timer1). is, writing a 0 to ET0I/ET1I can disable the correspond-
ing interrupt services.
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current In the case of Timer/Event Counter 0/1 OFF condition,
contents in the Timer/Event Counter 0/1 to FFH or FFFFH. writing data to the Timer/Event Counter 0/1 register
Once overflow occurs, the counter is reloaded from the will also reload that data to the Timer/Event Counter 0/1.
Timer/Event Counter 0/1 preload register and generates But if the Timer/Event Counter 0/1 is turned on, data
the interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the written to it will only be kept in the Timer/Event Counter
same time. 0/1 preload register. The Timer/Event Counter 0/1 will still

fS Y S M
U 8 - s ta g e P r e s c a le r
fR T C X
f IN T D a ta B u s
8 -1 M U X
M a s k O p tio n T 0 M 1
T 0 M 0 T im e r /E v e n t C o u n te r 0 R e lo a d
T 0 P S C 2 ~ T 0 P S C 0 T M R 0 P r e lo a d R e g is te r

T 0 E

P u ls e W id th T im e r /E v e n t O v e r flo w
T 0 M 1 M e a s u re m e n t C o u n te r 0 to In te rru p t
T 0 M 0 M o d e C o n tro l
T 0 O N
1 /2 B Z
B Z

Timer/Event Counter 0

D a ta B u s
fS Y S /4 M
U
fR X T 1 M 1
T C
T 1 M 0 1 6 B its
T im e r /E v e n t C o u n te r L o w B y te
T M R 1 P r e lo a d R e g is te r B u ffe r
M a s k O p tio n
T 1 E R e lo a d

P u ls e W id th 1 6 B its
T 1 M 1 M e a s u re m e n t T im e r /E v e n t C o u n te r O v e r flo w
T 1 M 0 M o d e C o n tro l (T M R 1 H /T M R 1 L )
T 1 O N to In te rru p t

Timer/Event Counter 1

Rev. 2.01 15 January 9, 2009


HT48R50A-1/HT48C50-1

operate until overflow occurs (a Timer/Event Counter 0/1 For output function, CMOS is the only configuration.
reloading will occur at the same time). When the These control registers are mapped to locations 13H,
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read, 15H, 17H, 19H and 1FH.
the clock will be blocked to avoid errors. As clock blocking After a chip reset, these input/output lines remain at high
may results in a counting error, this must be taken into levels or floating state (depending on the pull-high op-
consideration by the programmer. tion). Each bit of these input/output latches can be set or
The bit0~bit2 of the TMR0C can be used to define the cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
pre-scaling stages of the internal clock sources of 16H, 18H or 1EH) instructions.
Timer/Event Counter 0. The definitions are as shown.
Some instructions first input data and then follow the
The overflow signal of Timer/Event Counter 0 can be
output operations. For example, ²SET [m].i², ²CLR
used to generate PFD signals for buzzer driving.
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
Input/Output Ports into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
There are 35 bidirectional input/output lines in the
latches or the accumulator.
microcontroller, labeled from PA to PD and PG, which are
mapped to the data memory of [12H], [14H], [16H], [18H] Each line of port A has the capability of waking-up the de-
and [1EH], respectively. All of these I/O ports can be used vice. The highest 5-bit of port G are not physically imple-
for input and output operations. For input operation, these mented; on reading them a ²0² is returned whereas writing
ports are non-latching, that is, the inputs must be ready at then results in no-operation. See Application note.
the T2 rising edge of instruction ²MOV A,[m]² (m=12H, There is a pull-high option available for all I/O lines.
14H, 16H, 18H or 1EH). For output operation, all the data Once the pull-high option of an I/O line is selected, the
is latched and remains unchanged until the output latch is I/O line have pull-high resistor. Otherwise, the pull-high
rewritten. resistor is absent. It should be noted that a non-pull-high
Each I/O line has its own control register (PAC, PBC, I/O line operating in input mode will cause a floating
PCC, PDC, PGC) to control the input/output configura- state.
tion. With this control register, CMOS output or Schmitt The PB0 and PB1 are pin-shared with BZ and BZ signal,
trigger input with or without pull-high resistor structures respectively. If the BZ/BZ option is selected, the output
can be reconfigured dynamically (i.e. on-the-fly) under signal in output mode of PB0/PB1 will be the PFD signal
software control. To function as an input, the corre- generated by Timer/Event Counter 0 overflow signal.
sponding latch of the control register must write ²1². The The input mode always remain in its original functions.
input source also depends on the control register. If the Once the BZ/BZ option is selected, the buzzer output
control register bit is ²1², the input will read the pad signals are controlled by the PB0 data register only.
state. If the control register bit is ²0², the contents of the
latches will move to the internal bus. The latter is possi-
ble in the ²read-modify-write² instruction.

P G 1 /P G 2 I/O M o d e O n ly V D D
P u ll- H ig h
C o n tr o l B it O p tio n
D a ta B u s D Q

W r ite C o n tr o l R e g is te r C K Q
S
C h ip R e s e t P A 0 ~ P A 7
P B 0 ~ P B 7
P C 0 ~ P C 7
R e a d C o n tr o l R e g is te r P D 0 ~ P D 7
D a ta B it P G 0 ~ P G 2
D Q

W r ite D a ta R e g is te r C K Q
S
M
P B 0 U
( P B 0 , P B 1 O n ly ) X
B Z /B Z
M B Z E N
U ( P B 0 , P B 1 O n ly )
R e a d D a ta R e g is te r X
S y s te m W a k e -u p
( P A o n ly ) O P 0 ~ O P 7
IN T fo r P G 0 O n ly
Input/Output Ports

Rev. 2.01 16 January 9, 2009


HT48R50A-1/HT48C50-1

The I/O functions of PB0/PB1 are shown below.


PB0 I/O I I O O O O O O O O
PB1 I/O I O I I I O O O O O
PB0 Mode x x C B B C B B B B
PB1 Mode x C x x x C C C B B
PB0 Data x x D 0 1 D0 0 1 0 1
PB1 Data x D x x x D1 D D x x
PB0 Pad Status I I D 0 B D0 0 B 0 B
PB1 Pad Status I D I I I D1 D D 0 B
Note: ²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer option, BZ or BZ, ²x² don't care
²C² CMOS output

The PG0 is pin-shared with INT. The LVR includes the following specifications:
In case of ²Internal RC+I/O² system oscillator, the PG1 · The low voltage (0.9V~VLVR) has to remain in its origi-
and PG2 are pin-shared with OSC1 and OSC2 pins. nal state for longer than 1ms. If the low voltage state
Once the ²Internal RC+I/O² mode is selected, the PG1 does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
and PG2 can be used as general purpose I/O lines. Oth-
erwise, the pull-high resistors and I/O functions of PG1 · The LVR uses an ²OR² function with the external RES

and PG2 will be disabled. signal to perform a chip reset.


The relationship between VDD and VLVR is shown below.
It is recommended that unused or not bonded out I/O
V D D V O P R
lines should be set as output pins by software instruction 5 .5 V 5 .5 V
to avoid consuming power under input floating state.

Low Voltage Reset - LVR


The microcontroller provides low voltage reset circuit in V L V R

3 .0 V
order to monitor the supply voltage of the device. If the
2 .2 V
supply voltage of the device is within the range
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally. 0 .9 V

Note: VOPR is the voltage range for proper chip opera-


tion at 4MHz system clock.
V D D

5 .5 V

V L V R L V R D e te c t V o lta g e

0 .9 V

0 V

R e s e t S ig n a l

R e s e t N o r m a l O p e r a tio n R e s e t

*1 *2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024
system clock pulses before starting the normal operation.
*2: Since low voltage has to be maintained its original state for longer than 1ms, therefore a 1ms delay
enters the reset mode.

Rev. 2.01 17 January 9, 2009


HT48R50A-1/HT48C50-1

Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
Items Options
1 WDT clock source: WDT oscillator or fSYS/4 or RTC oscillator or disable
2 CLRWDT instructions: 1 or 2 instructions
3 Timer/Event Counter 0 clock sources: fSYS or RTCOSC
4 Timer/Event Counter 1 clock sources: fSYS/4 or RTCOSC
5 PA bit wake-up enable or disable
6 PA CMOS or Schmitt input
7 PA, PB, PC, PD, PG pull-high enable or disable (By port)
8 BZ/BZ enable or disable
9 LVR enable or disable
System oscillator
10
Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PG1/PG2
11 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz

Rev. 2.01 18 January 9, 2009


HT48R50A-1/HT48C50-1

Application Circuits
V D D

R O S C
R C S y s te m O s c illa to r
O S C 1 2 4 k W < R O S C < 1 M W
4 7 0 p F
O S C 2
N M O S o p e n d r a in
V D D
C 1
0 .0 1 m F * O S C 1
V D D P A 0 ~ P A 7 C ry s ta l S y s te m O s c illa to r
1 0 0 k W P B 2 ~ P B 7 C 2 F o r th e v a lu e s ,
s e e ta b le b e lo w
P C 0 ~ P C 7 O S C 2
R E S R 1
0 .1 m F
1 0 k W P D 0 ~ P D 7

0 .1 m F *
V S S O S C 1 In te r n a l R C O s c illa to r
P B 0 /B Z
O S C 1 a n d O S C 2 le ft
P B 1 /B Z O S C 2 u n c o n n e c te d

O S C O S C 1
C ir c u it O S C 2 T M R 0

T M R 1 O S C 1
S e e R ig h t S id e
In te r n a l R C O s c illa to r
1 0 p F 3 2 7 6 8 H z
w ith R T C
P G 0 /IN T O S C 2

H T 4 8 R 5 0 A -1 /H T 4 8 C 5 0 -1 O S C C ir c u it

Note: The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and re-
mains in a valid range of the operating voltage before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For refer-
ence only)

Crystal or Resonator C1, C2 R1


4MHz Crystal 0pF 10kW
4MHz Resonator 10pF 12kW
3.58MHz Crystal 0pF 10kW
3.58MHz Resonator 25pF 10kW
2MHz Crystal & Resonator 25pF 10kW
1MHz Crystal 35pF 27kW
480kHz Resonator 300pF 9.1kW
455kHz Resonator 300pF 10kW
429kHz Resonator 300pF 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-
tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.

Rev. 2.01 19 January 9, 2009


HT48R50A-1/HT48C50-1

Instruction Set
Introduction subtract instruction mnemonics to enable the necessary
Central to the successful operation of any arithmetic to be carried out. Care must be taken to en-
microcontroller is its instruction set, which is a set of pro- sure correct handling of carry and borrow data when re-
gram instruction codes that directs the microcontroller to sults exceed 255 for addition and less than 0 for
perform certain operations. In the case of Holtek subtraction. The increment and decrement instructions
microcontrollers, a comprehensive and flexible set of INC, INCA, DEC and DECA provide a simple means of
over 60 instructions is provided to enable programmers increasing or decreasing by a value of one of the values
to implement their application with the minimum of pro- in the destination specified.
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
The standard logical operations such as AND, OR, XOR
codes, they have been subdivided into several func-
and CPL all have their own instruction within the Holtek
tional groupings.
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
Instruction Timing
through the Accumulator which may involve additional
Most instructions are implemented within one instruc- programming steps. In all logical data operations, the
tion cycle. The exceptions to this are branch, call, or ta- zero flag may be set if the result of the operation is zero.
ble read instructions where two instruction cycles are Another form of logical data manipulation comes from
required. One instruction cycle is equal to 4 system the rotate instructions such as RR, RL, RRC and RLC
clock cycles, therefore in the case of an 8MHz system which provide a simple means of rotating one bit right or
oscillator, most instructions would be implemented left. Different rotate instructions exist depending on pro-
within 0.5ms and branch or call instructions would be im- gram requirements. Rotate instructions are useful for
plemented within 1ms. Although instructions which re- serial port programming applications where data can be
quire one more cycle to implement are generally limited rotated from an internal register into the Carry bit from
to the JMP, CALL, RET, RETI and table read instruc- where it can be examined and the necessary serial bit
tions, it is important to realize that any other instructions set high or low. Another application where rotate data
which involve manipulation of the Program Counter Low operations are used is to implement multiplication and
register or PCL will also take one more cycle to imple- division calculations.
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one Branches and Control Transfer
more cycle will be required. Examples of such instruc- Program branching takes the form of either jumps to
tions would be ²CLR PCL² or ²MOV PCL, A². For the specified locations using the JMP instruction or to a sub-
case of skip instructions, it must be noted that if the re- routine using the CALL instruction. They differ in the
sult of the comparison involves a skip operation then sense that in the case of a subroutine call, the program
this will also take one more cycle, if no skip is involved must return to the instruction immediately when the sub-
then only one cycle is required. routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
Moving and Transferring Data
the program to jump back to the address right after the
The transfer of data within the microcontroller program CALL instruction. In the case of a JMP instruction, the
is one of the most frequently used operations. Making program simply jumps to the desired location. There is
use of three kinds of MOV instructions, data can be no requirement to jump back to the original jumping off
transferred from registers to the Accumulator and point as in the case of the CALL instruction. One special
vice-versa as well as being able to move specific imme- and extremely useful set of branch instructions are the
diate data directly into the Accumulator. One of the most conditional branches. Here a decision is first made re-
important data transfer applications is to receive data garding the condition of a certain data memory or indi-
from the input ports and transfer data to the output ports. vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
Arithmetic Operations jump to the following instruction. These instructions are
The ability to perform certain arithmetic operations and the key to decision making and branching within the pro-
data manipulation is a necessary feature of most gram perhaps determined by the condition of certain in-
microcontroller applications. Within the Holtek put switches or by the condition of internal data bits.
microcontroller instruction set are a range of add and

Rev. 2.01 20 January 9, 2009


HT48R50A-1/HT48C50-1

Bit Operations Other Operations


The ability to provide single bit operations on Data Mem- In addition to the above functional instructions, a range
ory is an extremely flexible feature of all Holtek of other instructions also exist such as the ²HALT² in-
microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to
output port bit programming where individual bits or port control the operation of the Watchdog Timer for reliable
pins can be directly set high or low using either the ²SET program operations under extreme electric or electro-
[m].i² or ²CLR [m].i² instructions respectively. The fea- magnetic environments. For their relevant operations,
ture removes the need for programmers to first read the refer to the functional related sections.
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port Instruction Set Summary
with the correct new data. This read-modify-write pro- The following table depicts a summary of the instruction
cess is taken care of automatically when these bit oper- set categorised according to function and can be con-
ation instructions are used. sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of x: Bits immediate data
fixed data, the volume involved often makes it inconve- m: Data Memory address
nient to store the fixed data in the Data Memory. To over-
A: Accumulator
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where i: 0~7 number of bits
data can be directly stored. A set of easy to use instruc- addr: Program memory address
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.

Mnemonic Description Cycles Flag Affected


Arithmetic
ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV
ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV
ADD A,x Add immediate data to ACC 1 Z, C, AC, OV
ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV
ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV
SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV
SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV
SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV
SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV
DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C
Logic Operation
AND A,[m] Logical AND Data Memory to ACC 1 Z
OR A,[m] Logical OR Data Memory to ACC 1 Z
XOR A,[m] Logical XOR Data Memory to ACC 1 Z
ANDM A,[m] Logical AND ACC to Data Memory 1Note Z
ORM A,[m] Logical OR ACC to Data Memory 1Note Z
XORM A,[m] Logical XOR ACC to Data Memory 1Note Z
AND A,x Logical AND immediate Data to ACC 1 Z
OR A,x Logical OR immediate Data to ACC 1 Z
XOR A,x Logical XOR immediate Data to ACC 1 Z
CPL [m] Complement Data Memory 1Note Z
CPLA [m] Complement Data Memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment Data Memory with result in ACC 1 Z
INC [m] Increment Data Memory 1Note Z
DECA [m] Decrement Data Memory with result in ACC 1 Z
DEC [m] Decrement Data Memory 1Note Z

Rev. 2.01 21 January 9, 2009


HT48R50A-1/HT48C50-1

Mnemonic Description Cycles Flag Affected


Rotate
RRA [m] Rotate Data Memory right with result in ACC 1 None
RR [m] Rotate Data Memory right 1Note None
RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C
RRC [m] Rotate Data Memory right through Carry 1Note C
RLA [m] Rotate Data Memory left with result in ACC 1 None
RL [m] Rotate Data Memory left 1Note None
RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C
RLC [m] Rotate Data Memory left through Carry 1Note C
Data Move
MOV A,[m] Move Data Memory to ACC 1 None
MOV [m],A Move ACC to Data Memory 1Note None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of Data Memory 1Note None
SET [m].i Set bit of Data Memory 1Note None
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if Data Memory is zero 1Note None
SZA [m] Skip if Data Memory is zero with data movement to ACC 1note None
SZ [m].i Skip if bit i of Data Memory is zero 1Note None
SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None
SIZ [m] Skip if increment Data Memory is zero 1Note None
SDZ [m] Skip if decrement Data Memory is zero 1Note None
SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None
SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read table (current page) to TBLH and Data Memory 2Note None
TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear Data Memory 1Note None
SET [m] Set Data Memory 1Note None
CLR WDT Clear Watchdog Timer 1 TO, PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF
CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF
SWAP [m] Swap nibbles of Data Memory 1Note None
SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None
HALT Enter power down mode 1 TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.

Rev. 2.01 22 January 9, 2009


HT48R50A-1/HT48C50-1

Instruction Definition

ADC A,[m] Add Data Memory to ACC with Carry


Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation ACC ¬ ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADCM A,[m] Add ACC to Data Memory with Carry


Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation [m] ¬ ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADD A,[m] Add Data Memory to ACC


Description The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + [m]
Affected flag(s) OV, Z, AC, C

ADD A,x Add immediate data to ACC


Description The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + x
Affected flag(s) OV, Z, AC, C

ADDM A,[m] Add ACC to Data Memory


Description The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation [m] ¬ ACC + [m]
Affected flag(s) OV, Z, AC, C

AND A,[m] Logical AND Data Memory to ACC


Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s) Z

AND A,x Logical AND immediate data to ACC


Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s) Z

ANDM A,[m] Logical AND ACC to Data Memory


Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s) Z

Rev. 2.01 23 January 9, 2009


HT48R50A-1/HT48C50-1

CALL addr Subroutine call


Description Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s) None

CLR [m] Clear Data Memory


Description Each bit of the specified Data Memory is cleared to 0.
Operation [m] ¬ 00H
Affected flag(s) None

CLR [m].i Clear bit of Data Memory


Description Bit i of the specified Data Memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s) None

CLR WDT Clear Watchdog Timer


Description The TO, PDF flags and the WDT are all cleared.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

CLR WDT1 Pre-clear Watchdog Timer


Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

CLR WDT2 Pre-clear Watchdog Timer


Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF

Rev. 2.01 24 January 9, 2009


HT48R50A-1/HT48C50-1

CPL [m] Complement Data Memory


Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation [m] ¬ [m]
Affected flag(s) Z

CPLA [m] Complement Data Memory with result in ACC


Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s) Z

DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation [m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s) C

DEC [m] Decrement Data Memory


Description Data in the specified Data Memory is decremented by 1.
Operation [m] ¬ [m] - 1
Affected flag(s) Z

DECA [m] Decrement Data Memory with result in ACC


Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] - 1
Affected flag(s) Z

HALT Enter power down mode


Description This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation TO ¬ 0
PDF ¬ 1
Affected flag(s) TO, PDF

Rev. 2.01 25 January 9, 2009


HT48R50A-1/HT48C50-1

INC [m] Increment Data Memory


Description Data in the specified Data Memory is incremented by 1.
Operation [m] ¬ [m] + 1
Affected flag(s) Z

INCA [m] Increment Data Memory with result in ACC


Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] + 1
Affected flag(s) Z

JMP addr Jump unconditionally


Description The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation Program Counter ¬ addr
Affected flag(s) None

MOV A,[m] Move Data Memory to ACC


Description The contents of the specified Data Memory are copied to the Accumulator.
Operation ACC ¬ [m]
Affected flag(s) None

MOV A,x Move immediate data to ACC


Description The immediate data specified is loaded into the Accumulator.
Operation ACC ¬ x
Affected flag(s) None

MOV [m],A Move ACC to Data Memory


Description The contents of the Accumulator are copied to the specified Data Memory.
Operation [m] ¬ ACC
Affected flag(s) None

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
Affected flag(s) None

OR A,[m] Logical OR Data Memory to ACC


Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s) Z

Rev. 2.01 26 January 9, 2009


HT48R50A-1/HT48C50-1

OR A,x Logical OR immediate data to ACC


Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²OR² x
Affected flag(s) Z

ORM A,[m] Logical OR ACC to Data Memory


Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²OR² [m]
Affected flag(s) Z

RET Return from subroutine


Description The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation Program Counter ¬ Stack
Affected flag(s) None

RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation Program Counter ¬ Stack
ACC ¬ x
Affected flag(s) None

RETI Return from interrupt


Description The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s) None

RL [m] Rotate Data Memory left


Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s) None

RLA [m] Rotate Data Memory left with result in ACC


Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s) None

Rev. 2.01 27 January 9, 2009


HT48R50A-1/HT48C50-1

RLC [m] Rotate Data Memory left through Carry


Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s) C

RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s) C

RR [m] Rotate Data Memory right


Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s) None

RRA [m] Rotate Data Memory right with result in ACC


Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s) None

RRC [m] Rotate Data Memory right through Carry


Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s) C

RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s) C

Rev. 2.01 28 January 9, 2009


HT48R50A-1/HT48C50-1

SBC A,[m] Subtract Data Memory from ACC with Carry


Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation ACC ¬ ACC - [m] - C
Affected flag(s) OV, Z, AC, C

SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m] - C
Affected flag(s) OV, Z, AC, C

SDZ [m] Skip if decrement Data Memory is 0


Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s) None

SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s) None

SET [m] Set Data Memory


Description Each bit of the specified Data Memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s) None

SET [m].i Set bit of Data Memory


Description Bit i of the specified Data Memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s) None

Rev. 2.01 29 January 9, 2009


HT48R50A-1/HT48C50-1

SIZ [m] Skip if increment Data Memory is 0


Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s) None

SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s) None

SNZ [m].i Skip if bit i of Data Memory is not 0


Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation Skip if [m].i ¹ 0
Affected flag(s) None

SUB A,[m] Subtract Data Memory from ACC


Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ¬ ACC - [m]
Affected flag(s) OV, Z, AC, C

SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m]
Affected flag(s) OV, Z, AC, C

SUB A,x Subtract immediate data from ACC


Description The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation ACC ¬ ACC - x
Affected flag(s) OV, Z, AC, C

Rev. 2.01 30 January 9, 2009


HT48R50A-1/HT48C50-1

SWAP [m] Swap nibbles of Data Memory


Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation [m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s) None

SWAPA [m] Swap nibbles of Data Memory with result in ACC


Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s) None

SZ [m] Skip if Data Memory is 0


Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation Skip if [m] = 0
Affected flag(s) None

SZA [m] Skip if Data Memory is 0 with data movement to ACC


Description The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation ACC ¬ [m]
Skip if [m] = 0
Affected flag(s) None

SZ [m].i Skip if bit i of Data Memory is 0


Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation Skip if [m].i = 0
Affected flag(s) None

TABRDC [m] Read table (current page) to TBLH and Data Memory
Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s) None

TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s) None

Rev. 2.01 31 January 9, 2009


HT48R50A-1/HT48C50-1

XOR A,[m] Logical XOR Data Memory to ACC


Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s) Z

XORM A,[m] Logical XOR ACC to Data Memory


Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s) Z

XOR A,x Logical XOR immediate data to ACC


Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s) Z

Rev. 2.01 32 January 9, 2009


HT48R50A-1/HT48C50-1

Package Information
28-pin SKDIP (300mil) Outline Dimensions

2 8 1 5
B
1 1 4

D
I
E F G

Dimensions in mil
Symbol
Min. Nom. Max.
A 1375 ¾ 1395
B 278 ¾ 298
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I ¾ ¾ 375

Rev. 2.01 33 January 9, 2009


HT48R50A-1/HT48C50-1

28-pin SOP (300mil) Outline Dimensions

2 8 1 5

A B

1 1 4

C '
G
D H

E F a

· MS-013

Dimensions in mil
Symbol
Min. Nom. Max.
A 393 ¾ 419
B 256 ¾ 300
C 12 ¾ 20
C¢ 697 ¾ 713
D ¾ ¾ 104
E ¾ 50 ¾
F 4 ¾ 12
G 16 ¾ 50
H 8 ¾ 13
a 0° ¾ 8°

Rev. 2.01 34 January 9, 2009


HT48R50A-1/HT48C50-1

48-pin SSOP (300mil) Outline Dimensions

4 8 2 5

A B

1 2 4

C '
G
D H
a
E F

Dimensions in mil
Symbol
Min. Nom. Max.
A 395 ¾ 420
B 291 ¾ 299
C 8 ¾ 12
C¢ 613 ¾ 637
D 85 ¾ 99
E ¾ 25 ¾
F 4 ¾ 10
G 25 ¾ 35
H 4 ¾ 12
a 0° ¾ 8°

Rev. 2.01 35 January 9, 2009


HT48R50A-1/HT48C50-1

Product Tape and Reel Specifications


Reel Dimensions

D
T 2

A B C

T 1

SOP 28W (300mil)


Symbol Description Dimensions in mm
A Reel Outer Diameter 330.0±1.0
B Reel Inner Diameter 100.0±1.5
C Spindle Hole Diameter 13.0+0.5/-0.2

D Key Slit Width 2.0±0.5


T1 Space Between Flange 24.8+0.3/-0.2

T2 Reel Thickness 30.2±0.2

SSOP 48W
Symbol Description Dimensions in mm
A Reel Outer Diameter 330.0±1.0
B Reel Inner Diameter 100.0±0.1
C Spindle Hole Diameter 13.0+0.5/-0.2

D Key Slit Width 2.0±0.5


T1 Space Between Flange 32.2+0.3/-0.2

T2 Reel Thickness 38.2±0.2

Rev. 2.01 36 January 9, 2009


HT48R50A-1/HT48C50-1

Carrier Tape Dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0
A 0

R e e l H o le

IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .

SOP 28W (300mil)


Symbol Description Dimensions in mm
W Carrier Tape Width 24.0±0.3
P Cavity Pitch 12.0±0.1
E Perforation Position 1.75±0.10
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5+0.1/-0.0
D1 Cavity Hole Diameter 1.50+0.25/-0.00
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 10.85±0.10
B0 Cavity Width 18.34±0.10
K0 Cavity Depth 2.97±0.10
t Carrier Tape Thickness 0.35±0.01
C Cover Tape Width 21.3±0.1

Rev. 2.01 37 January 9, 2009


HT48R50A-1/HT48C50-1

P 0 P 1 t
D

F
W C B 0

K 1
D 1 P
K 2

A 0

R e e l H o le ( C ir c le )
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .

R e e l H o le ( E llip s e )

SSOP 48W
Symbol Description Dimensions in mm
W Carrier Tape Width 32.0±0.3
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.10
F Cavity to Perforation (Width Direction) 14.2±0.1
D Perforation Diameter 2 Min.
D1 Cavity Hole Diameter 1.50+0.25/-0.00
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 12.0±0.1
B0 Cavity Width 16.2±0.1
K1 Cavity Depth 2.4±0.1
K2 Cavity Depth 3.2±0.1
t Carrier Tape Thickness 0.35±0.05
C Cover Tape Width 25.5±0.1

Rev. 2.01 38 January 9, 2009


HT48R50A-1/HT48C50-1

Holtek Semiconductor Inc. (Headquarters)


No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)


4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)


G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103
Tel: 86-21-5422-4590
Fax: 86-21-5422-4705
http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)


5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)


Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)


709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)


46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com

Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.


The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Rev. 2.01 39 January 9, 2009

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