DSP Manual

Department of Electronics and Communication Engineering
Digital Signal Processing Lab
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD IV Year B.Tech. ECE I-Sem T 0 P 3 C 2
DIGITAL SIGNAL PROCESSING LAB LIST OF EXPERIMENTS 1. To study the architecture of DSP chips TMS 320C 5X/6X Instructions. 2. To verify linear convolution. 3. To verify the circular convolution. 4. To design FIR filter (LP/HP) using windowing technique a) Using rectangular window b) Using triangular window c) Using Kaiser window 5. To Implement IIR filter (LP/HP) on DSP Processors 6. N-point FFT algorithm. 7. MATLAB program to generate sum of sinusoidal signals. 8. MATLAB program to find frequency response of analog LP/HP filters. 9. To compute power density spectrum of a sequence. 10. To find the FFT of given 1-D signal and plot.
Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram
Equipment and Software
1. PCs 40 No.s Model: HP Compaq DX6120MT Processor: Intel Pentium-4 3.00 GHz Chipset: Intel 915 GV Express Chipset RAM: 512 MB DDR-II Hard Disk: 80 GB SATA Monitor: HP 17
2. CROs 12 No.s APLAB, 20 MHz Dual Trace
3. Function Generators 12 No.s APLAB, 3 MHz
4. DSP Starter kits 12 No.s Texas Instruments Floating point DSP TMS320C6713
5. MATLAB 15 Users Signal Processing Toolbox Filter Design Toolbox Communication Toolbox
6. Code Composer Studio Software
System Requirements
Minimum Recommended
3 GHz or Higher Pentium 3 GHz or Higher Pentium Compatible CPU Compatible CPU 600 MB of free hard disk space 512 MB RAM 512 MB of RAM SVGA (800 x 600 ) display 32 bit Color Internet Explorer (6.0 or later) or Local CD-ROM drive Supported Operating Systems Windows XP Windows NT 4.0 Service Pack 4 or higher
DSK Hardware installation: Shut down and power off the PC Connect the supplied USB port cable to the board Connect the other end of the cable to the USB port of PC Note: If you plan to install a Microphone, speaker, or signal generator/CRO these must be plugged in properly before you connect power to the DSK. Plug the power cable into the board Plug the other end of the power cable into a power outlet The user LEDs should flash several times to indicate board is operational When you connect your DSK through USB for the first time on a Windows loaded PC the new hardware found wizard will come up. So, Install the drivers (The CCS CD contains the require drivers for C6713 DSK). Install the CCS software for C6713 DSK.
Troubleshooting DSK Connectivity: If Code Composer Studio IDE fails to configure your port correctly, perform the following steps: Test the USB port by running DSK Port test from the start menu Click on the icon, Diagnostic Utility placed on desktop The below Screen will appear Select Start Option Utility Program will test the board After testing Diagnostic Status you will get PASS
If the board fails to detect 1. Reset the kit. 2. Check whether CCS is running or not. If running, close the application and run the diagnostic utility. 3. Check the USB ports of kit and the PC. 4. If board still fails, remove the power supply and reconnect the supply.
1. MATLAB
INTRODUCTION: MATLAB is a high-performance language for technical computing. It integrates computation, visualization, and programming in an easy-to-use environment where problems and solutions are expressed in familiar mathematical notation. Its wide range of commands, functions, and language constructs permit users to solve and analyze difficult computational problems from science and engineering without programming in a general purpose language. Typical uses include: Math and computation Algorithm development Modeling, simulation and prototyping Data analysis, exploration and visualization Scientific and engineering graphics Application development, including graphical user interface building. MATLAB is an interactive system whose basic data element is an array that does not require dimensioning. This allows us to solve many technical computing problems, especially those with matrix and vector formulations, in a fraction of the time it would take to write a program in a scalar non-interactive language such as C or FORTRAN. The name MATLAB stands for matrix laboratory. MATLAB features a family of application-specific solutions called toolboxes. The toolboxes allow us to learn and apply specialized technology. Toolboxes are comprehensive collections of MATLAB functions (M-files) that extend the MATLAB environment to solve particular classes of problems. Areas in which toolboxes are available include signal processing, control systems, communications, neural networks, fuzzy logic, wavelets simulation and many others. The MATLAB System: Development Environment: This is the set of tools and facilities that help you use MATLAB functions and files. Many of these tools are graphical user interfaces. It includes the MATLAB desktop and Command Window, a command history, and browsers for viewing help, the workspace, files, and the search path. Mathematical Function Library: This is a vast collection of computational algorithms ranging from elementary functions like sum, sine, cosine, and complex arithmetic, to more sophisticated functions like matrix inverse, matrix eigenvalues, fast Fourier transforms and Bessel functions. The MATLAB Language: This is a high-level matrix/array language with control flow statements, functions, data structures, input/output, and object-oriented programming features. It allows both programming in the small to rapidly create quick and dirty throw-away programs, and programming in the large to create complete large and complex application programs.
Handle Graphics: This is the MATLAB graphics system including high-level commands for 2-D and 3-D data visualization, image processing, animation, and presentation graphics. The MATLAB Application Program Interface (API): This is a library that allows you to write C and Fortran programs that interact with MATLAB. It include facilities for calling routines from MATLAB (dynamic linking), calling MATLAB as a computational engine, and for reading and writing MAT-files. MATLAB Desktop: When we start MATLAB, the desktop appears, containing tools (graphical user interfaces) for managing files, variables, and applications associated with MATLAB.The first time MATLAB starts, the desktop appears as shown below.
View or Change current directory Click to move window outside of desktop Close window
Get help.
Enter Matlab Functions
View or use previously run functions
Use tabs to go to workspace browser or current directory browser
Drag the separator bar to resize windows
Department of Electronics and Communication Engineering Command Window:
Command Window is used to enter variables and run functions and M-files.
Type functions and variables at the MATLAB MATLAB displays the
Editor/Debugger: Editor/Debugger is used to create and debug M-files, which are the programs to be run. This provides a graphical user interface for basic text editing, as well as for M-file debugging.
Comment selected lines and specify indenting style using the Text menu Find and replace strings.
Set breakpoints where you want execution to pause so you can examine variables
Hold the cursor over a variable and its current value appears ( known as data tip)
Signal Processing Toolbox: The Signal Processing Toolbox is a collection of tools built on MATLAB numeric computing environment which supports a wide range of signal processing operations, from waveform generation to filter design and implementation, parametric modeling, and spectral analysis. Signal Processing Toolbox Central Features: The Signal Processing Toolbox functions are algorithms, expressed mostly in Mfiles, that implement a variety of signal processing tasks. These toolbox functions are a specialized extension of the MATLAB computational and graphical environment. The
toolbox provides functions for generating widely used periodic waveforms like sawtooth which generate a sawtooth wave with peaks at 1 and a period of 2PI. Following is an example to generate 1.5 seconds of a 50 Hz sawtooth wave with a sample rate of 10 kHz and to plot 0.2 seconds of the generated waveform. This is obtained by the following. fs = 10000; t = 0:1/fs:1.5; x = sawtooth(2*pi*50*t); plot(t,x); axis([0 0.2 -1 1])
Frequency Response: The Signal Processing Toolbox enables us to perform frequency domain analysis of both analog and digital filters. Digital Domain: The command, freqz uses an FFT-based algorithm to calculate the ztransform frequency response of a digital filter. Specifically, [h,w] = freqz(b,a,p) returns the p-point complex frequency response, H(ejw), of the digital filter.
freqz accepts the filter coefficient vectors b and a, and an integer p specifying the number of points at which complex frequency response is calculated in vector h, and the actual frequency points in vector w in rad/s. [b,a] = cheby1(12,0.5,200/500); % 12th order Chebyshev type I filter [h,f] = freqz(b,a,256,1000); % 256-point frequency response with fs = 1000 Hz. This toolbox uses the convention that unit frequency is the Nyquist frequency, defined as half the sampling frequency. The cutoff frequency parameter for all basic filter design functions is normalized by the Nyquist frequency. For a system with a 1000 Hz sampling frequency, for e.g., 300 Hz is 300/500 = 0.6. To convert normalized frequency to angular frequency around the unit circle, multiply by 2/fs. To convert normalized freq. back to hertz, multiply by half the sample frequency.
Department of Electronics and Communication Engineering FIR Filter Design:
Digital filters with finite-duration impulse response (all-zero, or FIR filters) have both advantages and disadvantages compared to IIR filters. FIR filters have exactly linear phase, always stable and the design methods are generally linear. They can be realized efficiently in hardware. The filter startup transients have finite duration. The primary disadvantage of FIR filters is that they often require a much higher filter order than IIR filters to achieve a given level of performance. Correspondingly, the delay of these filters is often much greater than for an equal performance IIR filter. Complete Classical IIR Filter Design: We can easily create a filter of any order with a lowpass, highpass, bandpass, or bandstop configuration using the filter design functions. By default, each of these functions returns a lowpass filter; we need only specify the desired cutoff frequency Wn in normalized frequency (Nyquist frequency = 1 Hz). For a highpass filter, append the string 'high' to the function's parameter list. For a bandpass or bandstop filter, specify Wn as a two-element vector containing the passband edge frequencies, appending the string 'stop' for the bandstop configuration. Here are some example digital filters: [b,a] = butter(5,0.4); % Lowpass Butterworth [b,a] = cheby1(4,1,[0.4 0.7]); % Bandpass Chebyshev Type I [b,a] = cheby2(6,60,0.8,'high'); % Highpass Chebyshev Type II [b,a] = ellip(3,1,60,[0.4 0.7],'stop');% Bandstop elliptic To design an analog filter, perhaps for simulation, use a trailing 's' and specify cutoff frequencies in rad/s: [b,a] = butter(5,.4,'s'); % Analog Butterworth filter Designing IIR Filters to Frequency Domain Specifications: This toolbox provides order selection functions that calculate the minimum filter order that meets a given set of requirements. These are useful in conjunction with the filter design functions. An example is given below. % BPF with passband 1-2 KHz and stopband 500 Hz away on either side (Wp,Ws) % Sampling frequency 10 KHz, p.b. ripple-1 dB, s.b. attenuation 60 dB (Rp,Rs) [n,Wn] = buttord([1000 2000]/5000,[500 2500]/5000,1,60); Above command gives back order and cutoff frequencies of the filter as n = 12, Wn = 0.1951 0.4080 [b,a] = butter(n,Wn);
Department of Electronics and Communication Engineering The filter Function:
Filter is implemented as the transposed direct-form II structure, where n-1 is the filter order. This is a canonical form that has the minimum number of delay elements.
Filtering with the filter Function: It is simple to work back to a difference equation from the z-transform relation. Assume a(1) = 1. Move the denominator to the left-hand side and take the inverse ZT.
A filter in this form is easy to implement with the filter function. For example, a simple single-pole filter (lowpass) is b = 1; % Numerator a = [1 -0.9]; % Denominator Where the vectors b and a represent the coefficients of a filter in transfer function form. y = filter(b,a,x); filter gives as many output samples as there are input samples, that is, the length of y is the same as the length of x. If the first element of a is not 1, filter divides the coefficients by a (1) before implementing the difference equation. Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram
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2. Digital Signal Processors

INTRODUCTION: A digital signal processor (DSP) is an integrated circuit designed for high-speed data manipulations, and is used in audio, communications, image manipulation, and other data-acquisition and data-control applications. The microprocessors used in personal computers are optimized for tasks involving data movement and inequality testing. The typical applications requiring such capabilities are word processing, database management, spread sheets, etc. When it comes to mathematical computations the traditional microprocessor are deficient particularly where real-time performance is required. Digital signal processors are microprocessors optimized for basic mathematical calculations such as additions and multiplications. Fixed versus Floating Point: Digital Signal Processing can be divided into two categories, fixed point and floating point which refer to the format used to store and manipulate numbers within the devices. Fixed point DSPs usually represent each number with a minimum of 16 bits, although a different length can be used. There are four common ways that these 216 i,e., 65,536 possible bit patterns can represent a number. In unsigned integer, the stored number can take on any integer value from 0 to 65,535, signed integer uses two's complement to include negative numbers from -32,768 to 32,767. With unsigned fraction notation, the 65,536 levels are spread uniformly between 0 and 1 and the signed fraction format allows negative numbers, equally spaced between -1 and 1. The floating point DSPs typically use a minimum of 32 bits to store each value. This results in many more bit patterns than for fixed point, 232 i,e., 4,294,967,296 to be exact. All floating point DSPs can also handle fixed point numbers, a necessity to implement counters, loops, and signals coming from the ADC and going to the DAC. However, this doesn't mean that fixed point math will be carried out as quickly as the floating point operations; it depends on the internal architecture. The primary trade-offs between fixed and floating point DSPs are shown below. Fixed point arithmetic is much faster than floating point in general purpose computers.
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Department of Electronics and Communication Engineering C versus Assembly:
DSPs are programmed in the same languages as other scientific and engineering applications, usually assembly or C. Programs written in assembly can execute faster, while programs written in C are easier to develop and maintain. In traditional applications, such as programs run on PCs and mainframes, C is almost always the first choice. If assembly is used at all, it is restricted to short subroutines that must run with the utmost speed. How fast are DSPs? The primary reason for using a DSP instead of a traditional microprocessor is speed: the ability to move samples into the device and carry out the needed mathematical operations, and output the processed data. The usual way of specifying the fastness of a DSP is: fixed point systems are often quoted in MIPS (million integer operations per second). Likewise, floating point devices can be specified in MFLOPS (million floating point operations per second). TMS320 Family: The Texas Instruments TMS320 family of DSP devices covers a wide range, from a 16-bit fixed-point device to a single-chip parallel-processor device. In the past, DSPs were used only in specialized applications. Now they are in many mass-market consumer products that are continuously entering new market segments. The Texas Instruments TMS320 family of DSP devices and their typical applications are mentioned below. C1x, C2x, C2xx, C5x, C54x: The width of the data bus on these devices is 16 bits. All have modified Harvard architectures. They have been used in toys, hard disk drives, modems, cellular phones, and active car suspensions. C3x: The width of the data bus in the C3x series is 32 bits. Because of the reasonable cost and floating-point performance, these are suitable for many applications. These include almost any filters, analyzers, hi-fi systems, voice-mail, imaging, bar-code readers, motor control, 3D graphics, or scientific processing. C4x: This range is designed for parallel processing. The C4x devices have a 32-bit data bus and are floating-point. They have an optimized on-chip communication channel, which enables a number of them to be put together to form a parallel-processing cluster. The C4x range devices have been used in virtual reality, image recognition, telecom routing, and parallel-processing systems. C6x: The C6x devices feature VelociTI , an advanced very long instruction word (VLIW) architecture developed by Texas Instruments. Eight functional units, including two multipliers and six arithmetic logic units (ALUs), provide 1600 MIPS of costeffective performance. The C6x DSPs are optimized for multi-channel, multifunction applications, including wireless base stations, pooled modems, remote-access servers, digital subscriber loop systems, cable modems, and multi-channel telephone systems.
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Department of Electronics and Communication Engineering Introduction to TMS320C6713:
The TMS320C6000 digital signal processor (DSP) platform is part of the TMS320 DSP family. The TMS320C62x DSP generation and the TMS320C64x DSP generation comprise fixed-point devices and the TMS320C67x DSP generation comprises floating point devices in the C6000 DSP platform. All three uses the VelociTI architecture, a high-performance, advanced VLIW (very long instruction word) architecture. The VelociTI architecture of the C6000 platform of devices makes them the first off-the-shelf DSPs to use advanced VLIW to achieve high performance through increased instruction-level parallelism. A traditional VLIW architecture consists of multiple execution units running in parallel, performing multiple instructions during a single clock cycle. Parallelism is the key to extremely high performance, taking these DSPs well beyond the performance capabilities of traditional superscalar designs. VelociTI is a highly deterministic architecture, having few restrictions on how or when instructions are fetched, executed, or stored. VelociTIs advanced features include: Instruction packing: reduced code size All instructions can operate conditionally: flexibility of code Variable-width instructions: flexibility of data types Fully pipelined branches: zero-overhead branching.
TMS320 Family Overview The TMS320 DSP family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320 DSPs have an architecture designed specifically for real-time signal processing. In 1982, Texas Instruments (TI) introduced the TMS32010 the first fixed-point DSP in the TMS320 family. Today, the TMS320 family consists of many generations: C1x, C2x, C2xx, C5x, and C54x fixed-point DSPs, C3x and C4x floating-point DSPs, C8x multiprocessor DSPs and TMS320C6x DSPs. Typical Applications for the TMS320 Family The TMS320 DSPs offer adaptable approaches to traditional signal-processing problems and support complex applications that often require multiple operations to be performed simultaneously.
Automotive Adaptive ride control Cellular telephones Digital radios Navigation Vibration analysis Consumer Digital radios/TVs Music synthesizers Pagers Radar detectors Solid-state answering machines Control Disk drive control Laser printer control Motor control Servo control
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General-Purpose Adaptive filtering Convolution Correlation Digital filtering Fast Fourier transforms Instrumentation Digital filtering Function generation Pattern matching Phase-locked loops Seismic processing Spectrum analysis Transient analysis Telecommunications 1200- to 56 600-bps modems Adaptive equalizers ADPCM transcoders Echo cancellation Channel multiplexing Data encryption Digital PBXs Digital speech interpolation DTMF encoding/decoding Graphics/Imaging 3-D transformations Animation/digital maps Homomorphic processing Image compression/transmission Image enhancement Medical Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultra sound equipment Sonar processing Faxing Future terminals Line repeaters X.25 packet switching PDA Speaker phones Spread spectrum Video conferencing

Industrial Numeric control Power-line monitoring Robotics Security access Military Image processing Missile guidance Navigation Radar processing Radio frequency modems Secure communications GPS Voice/Speech Speaker verification Speech enhancement Speech recognition Speech synthesis Speech coding Text-to-speech Voice mail
Typical Applications of TMS320 DSPs Features and Options of TMS320C67X: The C6000 devices execute up to eight 32-bit instructions per cycle. The C67x devices core CPU consists of 32 general-purpose registers of 32-bit word length and eight functional units. The C6000 generation has a complete set of optimized development tools, including an efficient C compiler, an assembly optimizer for simplified assembly-language programming and scheduling, and a Windows based debugger interface for visibility into source code execution characteristics.
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3. TMS320C6713 DSK
Package Contents: The C6713 DSK builds on TI's DSP Starter Kit (DSK) development boards. The high-performance board features the TMS320C6713 floating-point DSP capable of performing 1350 million floating-point operations per second (MFLOPS). The DSK is USB port interfaced platform that allows efficiently developing and testing applications for the C6713.
Fig: 3.1 DSK Accessories The C6713 DSK has a TMS320C6713 DSP onboard that allows full-speed verification of code with CCS. The C6713 DSK provides a USB Interface, SDRAM and ROM, an analog interface circuit for Data conversion (AIC), an I/O port and Embedded JTAG emulation support. Connectors on the C6713 DSK provide DSP external memory interface (EMIF) and peripheral signals that enable its functionality to be expanded with custom or third party daughter boards. The C6713 DSK includes a stereo codec. This analog interface circuit (AIC) has the following characteristics: High-Performance Stereo Codec 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz) 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz) 8-kHz 96-kHz Sampling-Frequency Support Software Control Via TI McBSP-Compatible Multiprotocol Serial Port I2C-Compatible and SPI-Compatible Serial-Port Protocols Glueless Interface to TI McBSPs Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC Standard I 2 S, MSB, or LSB Justified-Data Transfers 16/20/24/32-Bit Word Lengths Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram 15
Department of Electronics and Communication Engineering Features of C6713 DSK:
The 6713 DSK enables us to evaluate and develop applications for TI C67XX DSP family. An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP0 is used for the codec control interface and McBSP1 is used for data. Analog audio I/O is done through four 3.5mm audio jacks that correspond to microphone input, line input, line output and headphone output. The codec can select the microphone or the line i/p as the active i/p. The analog o/p is driven to both line out and headphone connectors. McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device, CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to the CPLD registers. The DSK includes 4 LEDs and 4 DIP switches to provide the user with interactive feedback, accessed by reading and writing to the CPLD registers. Code Composer Studio communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.
Fig 3.2 TMS320C6713 DSK Overview Block Diagram
Fig 3.3 TMS320C6713 DSK Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram 16
Department of Electronics and Communication Engineering Introduction to CCS
Code Composer Studio is the DSP industry's first fully integrated development environment (IDE) with DSP-specific functionality. Code Composer Studio lets us edit, build, debug, profile and manage projects from a single unified environment. Other unique features include graphical signal analysis, injection/extraction of data signals via file I/O, multi-processor debugging, automated testing and customization via a Cinterpretive scripting language and much more. Code Composer Studio features: IDE Debug IDE Advanced watch windows Integrated editor File I/O, Probe Points, and graphical algorithm scope probes Advanced graphical signal analysis Interactive profiling Automated testing and customization via scripting Visual project management system Compile in the background while editing and debugging Multi-processor debugging Help on the target DSP
Documents for Reference: spru509 spru189 spru190 slws106d spru402 sprs186j Code Composer Studio getting started guide TMS320C6000 CPU & Instruction set guide TMS320C6000 Peripherals guide codec(TLV320AIC23) Data Manual Programmers Reference Guide TMS320C6713 DSP
Softcopy of documents are available at: C:\CCStudio\docs\pdf.
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Department of Electronics and Communication Engineering Procedure to work on CCS: 1. Create New Project Project New (File Name. pjt , Eg: Vectors.pjt)
2. Create a Source file File New Type the code (Save & give file name, Eg: demo.c).
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Department of Electronics and Communication Engineering 3. Add Source files to Project Project Add files to Project
demo.c
4. Add library file, rts.lib file & Hello.cmd: Project Add files to Project rts6700.lib Path: C:\CCStudio\c6000\cgtools\lib\rts6700.lib) Note: Select Object & Library in (*.o,*.l) in Files of type.
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Department of Electronics and Communication Engineering 1. Add Hello.cmd: Project Add files to Project hello.cmd CMD file is Common for all non real time programs. Path:C:\CCstudio\tutorial\dsk6713\hello1\hello.cmd Note: Select Linker Command file (*.cmd) in Files of type
2. Compile Project Compile
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6. Rebuild: Project rebuild, which will create the final .out executable file.(Eg. Vectors.out).
7. Load program File Load program
Vectors. Out
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Department of Electronics and Communication Engineering 8. Execute project Debug Run
Example program: # include<stdio.h> main() { int i=0; i++; printf("%d",i); } Single Step Debugging: 1. Keep the cursor on the line from where you want to start single step debugging.(eg: set a break point on to first line int i=0; of your project.) 2. 3. 4. 5. 6. 7. 8. icon from tool bar menu. a. To set break point select Load the Vectors. out file onto the target. Go to view and select Watch window. Debug Run. Execution should halt at break point. Now press F10. See the changes happening in the watch window. Similarly go to view & select CPU registers to view the changes happening in CPU registers. Repeat steps 2 to 6.
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Configuration of CODEC (TLV320AIC23) using Board Support Library: The prerequisites to configure the codec TLV320AIC23 through program using the board support library (BSL) are TMS320C6713 DSP Starter Kit, PC with Code Composer Studio, CRO, Audio Source, Speakers and Signal Generator. Steps for Configuring CODEC (TLV320AIC23) Connect CRO to the Socket Provided for LINE OUT. Connect a Signal Generator to the LINE IN Socket. Switch on the Signal Generator with a sine wave of frequency 500 Hz. Now Switch on the DSK and Bring Up Code Composer Studio on the PC. Create a new project with name XXXX.pjt. From the File Menu new DSP/BIOS Configuration select dsk6713.cdb and save it as YYYY.cdb and add it to the current project. 7. Add the generated YYYYcfg.cmd file to the current project. 8. Add the given codec.c file to the current project which has the main function and calls all the other necessary routines. 9. View the contents of the generated file YYYYcfg_c.c and copy the include header file YYYYcfg.h to the codec.c file. 10. Add the library file dsk6713bsl.lib from the location C:\CCStudio\c6000\dsk6713\lib\dsk6713bsl.lib to the current project 11. Build, Load and Run the program. 12. You can notice the input signal of 500 Hz. appearing on the CRO verifying the codec configuration. 13. You can also pass an audio input and hear the output signal through the speakers. 14. You can also vary the sampling frequency using the DSK6713_AIC23_setFreq function in the codec.c file and repeat the above steps. 1. 2. 3. 4. 5. 6.
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4. University prescribed experiments

1. TMS320C67XX Architecture
Aim: To study the architectural details of floating point Digital Signal Processor TMS320C6713 and instruction set. Architecture: The block diagram for TMS320C67xx DSP is shown the figure below. The C6000 devices come with program memory, which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power-down logic, and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are on only certain devices.
Fig. TMS320C67XX Block Diagram Central Processing Unit (CPU): The TMS320C67X CPU showed above contains Program fetch unit, Instruction decode unit, Two data paths, each with four functional units, thirty two 32-bit registers, Control registers, Control logic and Test, emulation, and interrupt logic. The program fetch, instruction dispatch and instruction decode units can deliver upto eight 32-bit instructions to the functional units every CPU clock cycle.
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The processing of instructions occurs in each of the two data paths, A&B each of which contains four functional units .L, .S, .M, and .D and sixteen 32-bit general-purpose registers for TMS320C67xx. A control register file provides the means to configure and control various processor operations. Internal Memory: The TMS320C67x have a 32-bit, byte-addressable address space. Internal (onchip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF). The TMS320C67xx have two 32-bit internal ports to access internal data memory. The TMS320C67x have a single internal port to access internal program memory, with an instruction-fetch width of 256 bits. Memory and Peripheral Options: A variety of memory and peripheral options are available for the C6000 platform. Large on-chip RAM up to 7Mb, Program cache and 2-level caches. 32-bit EMIF supports SDRAM, SBSRAM, SRAM and other asynchronous memories for a broad range of external memory requirements and maximum system performance. DMA Controller transfers data between address ranges in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel. EDMA Controller performs the same functions as the DMA controller. The EDMA has 16 programmable channels, as well as a RAM space to hold multiple configurations for future transfers. HPI is a parallel port through which a host processor can directly access the CPUs memory space. The host device has ease of access because it is the master of the interface. The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals. Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF. The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. McBSP (multichannel buffered serial port) is based on the standard serial port interface found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDNA controller. It also has multichannel capability compatible with the T1, E1, SCSA, and MVIP networking standards. Timers in the C6000 devices are two 32-bit general-purpose timers used for time events, count events, generate pulses, interrupt the CPU, send synchronization events to the DMA/EDMA controller and power-down logic allows reduced clocking to reduce power consumption.
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Department of Electronics and Communication Engineering Paths and Control: The components of the data path for TMS320C67X are: 1. Two general-purpose register files (A and B) 2. Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2) 3. Two load-from-memory data paths (LD1 and LD2) 4. Two store-to-memory data paths (ST1 and ST2) 5. Two data address paths (DA1 and DA2) 6. Two register file data cross paths (1X and 2X).
Fig. TMS320C67xx CPU Data Path General-Purpose Register Files: There are two general-purpose register files A & B in the C6000 data paths. For the C67x DSPs, each of these files contains 16 32-bit registers, A0-A15 for file A and B0-B15 for file B. The general-purpose registers can be used for data, data address pointers, or condition registers. The C67x general-purpose register files support data ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating point data. Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored in register pairs. Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram 26
In these the 32 LSBs of data are placed in an even-numbered register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). Packed data types store either four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values in a 64-bit register pair. There are 16 valid register pairs for 40-bit and 64-bit data in the C67x cores In assembly language syntax, a colon between the register names denotes the register pairs, and the odd-numbered register is specified first.
Register A A1:A0 A3:A2 A5:A4 A7:A6 A9:A8 A11:A10 A13:A12 A15:A14 Files B B1:B0 B3:B2 B5:B4 B7:B6 B9:B8 B11:B10 B13:B12 B15:B14
Fig. Register storage scheme for 40-bit long data. Functional Units: The eight functional units in the C6000 data paths can be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. Most data lines in the CPU support 32-bit operands, and some support long (40bit) and double word (64-bit) operands. Each functional unit has its own 32-bit write port into a general-purpose register file. All units ending in 1 (for example, .L1) write to register file A, and all units ending in 2 write to register file B. Each functional unit has two 32-bit read ports for source operands src1 and src2. Four units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as well as an 8-bit input for 40bit long reads. Because each unit has its own 32-bit write port, when performing 32-bit operations all eight units can be used in parallel every cycle. Register File Cross Paths: Each functional unit reads directly from and writes directly to the register file within its own data path. That is, the .L1, .S1, .D1, and .M1 units write to register file A and the .L2, .S2, .D2, and .M2 units write to register file B. The register files are connected to the opposite-side register files functional units via 1X and 2X cross paths. These cross paths allow functional units from one data path to access a 32-bit operand from the opposite side register file. The 1X cross path allows the functional units of data path A to read their source from register file B, and 2X cross path allows the functional units of data path B to read their source from register file A. On C67X 6 of the 8 functional units have access to register file on the opposite side, via a cross path. The .M1, .M2, .S1 and .S2 units src2 units are selectable between the cross path and the same side register file. In case of .L1 and .L2, both src1 and src2 inputs are also selectable between the cross path and the same-side register file. Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram 27
Only two cross paths, 1X and 2X exist in the C6000 architecture. Thus the limit is one source read from each data paths opposite register file per cycle, or a total of two cross path source reads per cycle. In the C67x only one functional unit per data path, per execute packet, can get an operand from the opposite register file. Memory, Load, and Store Paths: The C67x has a second 32-bit load path for both register files A and B. This allows the LDDW instruction to simultaneously load two 32-bit values into register file A and two 32-bit values into register file B. For side A, LD1a is the load path for the 32 LSBs and LD1b is the load path for the 32 MSBs. For side B, LD2a is the load path for the 32 LSBs and LD2b is the load path for the 32 MSBs. There are also two 32-bit paths, ST1 and ST2, for storing register values to memory from each register file. Data Address Paths: The data address paths DA1 and DA2 are each connected to .D units in both data paths. Data addresses generated by any one path can access data to or from any register. The DA1 and DA2 resources and their associated data paths are specified as T1 and T2 respectively. T1 consists of the DA1 address path and the LD1 and ST1 data paths. Addressing Mode Register (AMR): For each of the eight registers (A4A7, B4B7) that can perform linear or circular addressing, the AMR specifies the addressing mode. A 2-bit field for each register selects the address modification mode: linear (the default) or circular mode. With circular addressing, the field also specifies which BK (block size) field to use for a circular buffer. In addition, the buffer must be aligned on a byte boundary equal to the block size Legend: R Readable by the MVC instruction W Writeable by the MVC instruction +0 Value is zero after reset TMS320C67x Fixed-Point Instruction Set: The TMS320C62x, TMS320C64x, and the TMS320C67x share an instruction set. All of the instructions valid for the C62x are also valid for the C64x and C67x. However, because the C67x is a floating-point device, there are some instructions that are unique to it and do not execute on the fixed-point device. Mapping Between Instructions and Functional Units: Instruction to Functional Unit Mapping
.L Unit ABS ADD ADDU AND CMPEQ CMPGT .M Unit MPY MPYU MPYUS MPYSU MPYH MPYHU ADD ADDK ADD2 AND B disp B IRP .S SET SHL SHR SHRU SSHL SUB .D Unit Addressing Modes: ADD STB (15-bit offset) ADDAB STH (15-bit offset) ADDAH STW (15-bit offset) ADDAW SUB LDB SUBAB LDBU SUBAH
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CMPGTU CMPLT CMPLTU LMBD MV NEG NORM NOT OR SADD SAT SSUB SUB SUBU SUBC XOR ZERO MPYHUS MPYHSU MPYHL MPYHLU MPYHULS MPYHSLU MPYLH MPYLHU MPYLUHS MPYLSHU SMPY SMPYHL SMPYLH SMPYH B NRP SUBU LDH

SUBAW ZERO
B reg SUB2 LDHU CLR XOR LDW EXT ZERO LDB (15-bit offset) EXTU LDBU (15-bit offset) MV LDH (15-bit offset) MVC LDHU (15-bit offset) MVK LDW (15-bit offset) MVKH MV MVKLH STB NEG NOT OR STH STW
S2 only D2 only INSTRUCTION SET:
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2. Linear convolution
Aim: To compute the response of a discrete a LTI system with input sequence x[n] and impulse response h[n] by using linear convolution. Theory: Linear Convolution involves the operations, 1.Folding, 2.Multiplication, 3. Addition and 4. Shifting. These operations are represented by a mathematical expression,
y[n] =
k =
x[k ]h[n k ]
x[k]= Input signal Samples h[k] = Impulse response co-efficient. y[n]= Convolution output.
Algorithm:
Step 1: Enter the sequence x[n]. Step 2: Find the length of sequence,N1. Step 3: Enter another sequence h[n]. Step 4: Find the length of sequence N2. Step 5: Find N=N1+N2-1. Step 6: Append N2-1 zeros to x[n]. Step 7: Append N1-1 zeros to h[n]. Step 8: Fold the h[n] and shift by delay l. Step 9: Multiply h[n-l] by x[n] and sum all the values to obtain y[n] Step 10: Repeat the steps 8& 9 for values of l=N1+N2-1. Step 11: Plot the output y[n].
Program:
x=input('Enter any sequence X:') h=input('Enter any sequence H:') n1=length(x) n2=length(h) j=0:1:n1-1; l=0:1:n2-1; p=n1+n2-1 x=[x zeros(1,p-n1)] h=[h zeros(1,p-n2)] for t=1:p sum=0 for k=1:t
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%if((t-k+1)>0) sum=sum+[x(k)*h(t-k+1)] %end end y(t)=sum end subplot(311) stem(x) axis([0 6 0 5]) xlabel('n'),ylabel('x(n)') subplot(312) stem(h) axis([0 6 0 5]) xlabel('n'),ylabel('h(n)') subplot(313) stem(y) axis([0 10 0 10]) xlabel('n'),ylabel('y(n)') Inputs: Enter any sequence X:[1 2 3 4] Enter any sequence H:[4 3 2 1]
Output: y = 4 11 20 30 20 11
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3. Circular Convolution
Aim: To compute circular convolution of the two input sequences x[n] and h[n]. Theory: The circular convolution of two sequences is given as
N 1
y (n ) = x(m ) h((n m )) N Where h((n m ))N is a circular shift of h(n).

Algorithm: Step 1: Enter the sequence x[n]. Step 2: Find the length of sequence (N1). Step 3: Enter another sequence h[n]. Step 4: Find the length of sequence (N2). Step 5: Find N = maximum of N1 and N2. Step 6: if N2>N1, append N2-N1 zeros to x[n]. Step 7: if N1>N2, append N1-N2 zeros to h[n]. Step 8: Fold h[n] and apply circular shift by a number l. Step 9: Multiply h[n-l] by x[n] and sum all the values to obtain y[n] Step 10: Repeat the steps 8 & 9 for values of l=N1+N2-1. Step 11: Plot the output y[n]. C Program:
m =0
#include<stdio.h> main() { int lenx, lenh, i, j, p, t, k, sum; int x[50], h[50], y[50]; printf("enter the length of sequence X:"); scanf("%d", &lenx); printf("enter the length of sequence h:"); scanf("%d",&lenh); for(i=0;i<lenx;i++) { printf("x[%d]=",i); scanf("%d",&x[i]); } for(i=0;i<lenh;i++) { printf("h[%d]=",i); scanf("%d",&h[i]); } if(lenx>lenh) { P=lenx; for(i=1;i<=(p-lenh);i++)
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h[lenh-1+i]=0; } else { P=lenh; for(i=1;i<=(p-lenx);i++) x[lenx-1+i]=0; } for(t=0;t<p;t++) { sum = 0; for(k=0;K<t;k++) { z=p+t-k; if(z>=p) z=z-p; sum=sum+(x[k]*h[z]); } y[t]=sum; } for(i=0;i<p;i++) printf("\nx[%d]=%d",i,x[i]); printf("\n"); for(i=0;i<p;i++) printf("\n h[%d]=%d",i,h[i]); printf("\n"); printf("\n"); for(i=0;i<p;i++) printf("\n y[%d]=%d", i, y[i]); }
Input:
Enter The Length Of Sequence X: 4 Enter The Length Of Sequence H: 4 Enter The Sequence X: X[0] = 1 X[1] = 1 X[2] = 1 X[3] = 2 Enter The Sequence H: H[0] = 2 H[1] = 1 H[2] = 3 H[3] = 2
Output: Y[0] = 9 Y[1] = 11 Y[2] = 10 Y[3] = 10
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4. Design of FIR Filter

Aim: To design coefficients of a low pass or high pass FIR filter using windowing technique. Theory: The design of FIR filter using windowing method involves finding:
h(n) = hd(n)w(n) for all |n| (N-1)/2 = 0 for |n| > (N-1)/2
1 H (e jw )e jwn dw 2 w(n) is a weighing sequence or window and it is defined as
where hd(n) is obtained as hd (n ) =
w(n) = w(-n) 0 for |n| (N-1)/2 = 0 for |n| > (N-1)/2 For rectangular window, w(n) = 1 |n| (N-1)/2 = 0 for |n| > (N-1)/2 For triangular or Bartlett window, w(n) =1 2 |n| / (N 1) for |n| (N-1)/2 = 0 for |n| > (N-1)/2 For Hanning window, w(n) = 0.5 + 0.5 cos 2 n/(N-1) for |n| (N-1)/2 = 0 for |n| > (N-1)/2
MATLAB program:
N=input('Enter the order: '); Wc=input('Enter cutoff freq in rad/sec: '); a=(N-1)/2; filtyp=input('Enter 1/2 for LP/HP: '); switch(filtyp) case 1 for n=1:N if((n-1)==a) hd(n)=Wc/pi; else hd(n)=(sin(Wc*((n-1)-a)))/(pi*((n-1)-a)); end end
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case 2 for n=1:N if((n-1)==a) hd(n)=1-Wc/pi; else hd(n)=(sin(pi*(n-a))-sin(Wc*((n-1)-a)))/(pi*((n-1)-a)); end end end sel=input('Enter 1,2 or 3 for Rec/Triang/Kaiser: '); switch(sel) case 1 disp('You have selected Rect Window '); for n=1:N, W(n)=1; end case 2 disp('You have selected Triangular Window '); for n=1:N, W(n)=1.0-(2.0*abs(n-1-(N-1)/2.0)/(N-1)); end case 3 disp('You have selected Kaiser Window '); W=kaiser(N); end for n=1:N, h(n)=hd(n)*W(n); end disp('The FIR filter coefficents are') disp(h)
Result:
Enter the order: 5 Enter cutoff freq in rad/sec: pi/4 Enter 1/2 for LP/HP: 2 Enter 1,2 or 3 for Rec/Triang/Kaiser: 2 You have selected Triangular Window The FIR filter coefficents are 0 -0.1125 0.7500 -0.1125 0
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5. Real Time Implementation of IIR Filter

Aim: To design and implement a Digital IIR Filter & observe its frequency response. Equipment needed:
1. PC 2. TMS320C6713 DSP Starter Kit (DSK). 3. Oscilloscope and Function generator.

ALGORITHM:
The Butterworth bandpass IIR filter is realized by implementing the difference equation: y[n] = b0x[n] + b1x[n-1]+b2x[n-2]-a1y[n-1]-a2y[n-2] where b0 b2, a0 - a2 are feed forward and feedback word coefficients respectively [assume 2nd order of filter]. These coefficients are calculated using MATLAB. A direct form I implementation approach is taken. Step 1 - Initialize the McBSP, the DSP board and the on board codec. (refer the topic: Configuration of 6713Codec using BSL) Step 2 - Initialize the discrete time system, that is, specify the initial conditions. Generally zero initial conditions are assumed. Step 3 - Take sampled data from codec while input is fed to DSP kit from the signal generator. Since Codec is stereo , take average of input data read from left and right channel . Store sampled data at a memory location Step 4 - Perform filter operation using above said difference equation and store filter Output at a memory location . Step 5 - Output the value to codec (left channel and right channel) and view the output at Oscilloscope. Step 6 - Go to step 3.
MATLAB program to generate filter coefficients:
% IIR Low pass Butterworth filter % sampling rate - 24000 order = 2; cf=[2500/12000]; % cutoff frequency - 2500 [num_bw1,den_bw1]=butter(order,cf);
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Start
Flow Chart: Initialize the DSP Board
Set initial conditions of discrete time system by making x[0]-x[2] and y[0]y[2] equal to zeros and a0-a2,b0-b2 with MATLAB filter coefficients
Take a new input and store it in x[0].
Do y[-3] = y[-2],y[-2]=y[-1] and Y[-1] = output . x[-3] = x[-2], x[-2]=x[-1] x[-1]=x[0] Poll for ready bit Poll the ready bit, when asserted proceed.
output = x[0]b0+x[-1]b1+ x[-2]b2 - y[-1]a1 - y[-2]a2
Write output to analog i/o.
MATLAB code to get filter coefficients:
Stop
% IIR Low pass Butterworth filter % sampling rate - 24000 order = 2; cf=[2500/12000]; % cutoff frequency - 2500 [num_bw1,den_bw1]=butter(order,cf); IIR_BUTTERWORTH_LP FILTER CO-EFFICIENTS:
Fc=2500Hz Floating Point Fixed Point Values Values(Q15) B0 B1 B2 A0 A1 A2 0.072231 0.144462 0.072231 1.000000 -1.109229 0.398152 2366 2366[B1/2] 2366 32767 -18179[A1/2] 13046 Fc=800Hz Floating Fixed Point Point Values(Q15) Values 0.009526 312 0.019052 312[B1/2] 0.009526 312 1.000000 32767 -1.705552, -27943[A1/2] 0.743655 24367 Fc=8000Hz Floating Fixed Point Point Values(Q15) Values 0.465153 15241 0.930306 15241[B1/2] 0.465153 15241 1.000000 32767 0.620204 10161[A1/2] 0.240408 7877
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Note: Floating Point Values are multiplied with 32767(215) to get Fixed Point Values.
C Program to implement IIR filter:
#include "filtercfg.h" #include "dsk6713.h" #include "dsk6713_aic23.h" const signed int filter_Coeff[] = { 12730,-12730,12730,2767,-18324,21137 /*HP 2500 */ } ; /* Codec configuration settings */ DSK6713_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; / * main() - Main code routine, initializes BSL and generates tone */ void main() { DSK6713_AIC23_CodecHandle hCodec; int l_input, r_input, l_output, r_output; /* Initialize the board support library, must be called first */ DSK6713_init(); hCodec = DSK6713_AIC23_openCodec(0, &config); /* Start the codec */ DSK6713_AIC23_setFreq(hCodec, 3); while(1) { /* Read a sample to the left channel */ while (!DSK6713_AIC23_read(hCodec, &l_input)); /* Read a sample to the right channel */ while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=IIR_FILTER(&filter_Coeff ,l_input); r_output=l_output; /* Send a sample to the left channel */ while (!DSK6713_AIC23_write(hCodec, l_output)); /* Send a sample to the right channel */ while (!DSK6713_AIC23_write(hCodec, r_output)); } DSK6713_AIC23_closeCodec(hCodec); /* Close the codec */ }
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signed int IIR_FILTER(const signed int * h, signed int x1) { static signed int x[6] = { 0, 0, 0, 0, 0, 0 }; /* x(n), x(n-1), x(n-2). Must be static */ static signed int y[6] = { 0, 0, 0, 0, 0, 0 }; /* y(n), y(n-1), y(n-2). Must be static */ int temp=0; temp = (short int)x1; /* Copy input to temp */ x[0] = (signed int) temp; /* Copy input to x[stages][0] */ temp = ( (int)h[0] * x[0]) ; temp += ( (int)h[1] * x[1]); temp += ( (int)h[1] * x[1]); temp += ( (int)h[2] * x[2]); temp -= ( (int)h[4] * y[1]); temp -= ( (int)h[4] * y[1]); temp -= ( (int)h[5] * y[2]); temp >>= 15; /* B0 * x(n) */ /* B1/2 * x(n-1) */ /* B1/2 * x(n-1) */ /* B2 * x(n-2) */ /* A1/2 * y(n-1) */ /* A1/2 * y(n-1) */ /* A2 * y(n-2) */
/* Divide temp by coefficients[A0] */
if ( temp > 32767 ) { temp = 32767; } else if ( temp < -32767) { temp = -32767; } y[0] = temp ; /* Shuffle values along one place for next time */ y[2] = y[1]; /* y(n-2) = y(n-1) */ y[1] = y[0]; /* y(n-1) = y(n) */ x[2] = x[1]; /* x(n-2) = x(n-1) */ x[1] = x[0]; /* x(n-1) = x(n) */ return (temp<<2); /* temp is used as input next time through */ }
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Department of Electronics and Communication Engineering PROCEDURE:
1. Click on the Icon
to launch DSK 6713 Code Composer Studio
2. Connect the target processor. Debug connect.
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3. Create a new project from project new . Select the target as TMS 320C67XX which is your DSP processor.
4. Create a new BIOS configuration. file new DSP/BIOS Configuration
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5. Select dsk6713.cdb and save it with .cdb extension. Example: code.cdb
6. Save the created .cdb file in your project directory.
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7. Add the created .cdb file to your project. Project add files to project
8. Select the .cdb file and click on open.
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9. Create new source file. file new source file. Enter the source code and save it in your project directory. Ex: filter.c. 10. Add the created source file to your project. Project add files to project. 11. Include the header file ****cfg.h in source code **** is the name of the .cdb file, here it is codecfg.h
12. Copy the dsk6713.h and dsk6713_aic23.h files in C:\CCstudio\dsk6713\ include and paste them in your project folder. Note: Do not cut or add these files to your project
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13. Add dsk6713bsl.lib to your project Path: C:\CCstudio\dsk6713\lib\ dsk6713bsl.lib.
14. Compile the program. Project compile. 15. Build the program. Project Build. 16. Rebuild the program. Project rebuild all. This creates .out executable file in debug folder with project name.out
17. Load the program from file Load program
18. After loading the program run the program. Debug Run. 19. Verify the output on CRO.
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6. Fast Fourier Transform

Aim: To obtain Fast Fourier Transform of a given sequence. Theory: A fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier transform (DFT) and its inverse. FFTs are of great importance to a wide variety of applications, from digital signal processing and solving partial differential equations to algorithms for quick multiplication of large integers. Evaluating the sums of DFT directly would take O(N 2) arithmetical operations. An FFT is an algorithm to compute the same result in only O(N log N) operations. In general, such algorithms depend upon the factorization of N, but there are FFTs with O(N log N) complexity for all N, even for prime N. Since the inverse DFT is the same as the DFT, but with the opposite sign in the exponent and a 1/N factor, any FFT algorithm can easily be adapted for it as well.
C Program:
#include<math.h> #include<stdio.h> short FFT(short int dir,long m,float *x,float *y) { long n,i,i1,j,k,i2,l,l1,l2; float c1,c2,tx,ty,t1,t2,u1,u2,z; /* Calculate the number of points */ n = 1; for (i=0;i<m;i++) n *= 2;
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/* Do the bit reversal */ i2 = n >> 1; j = 0; for (i=0;i<n-1;i++) { if (i < j) { tx = x[i]; ty = y[i]; x[i] = x[j]; y[i] = y[j]; x[j] = tx; y[j] = ty; } k = i2; while (k <= j ) { j -= k; k >>= 1; } j += k; } /* Compute the FFT*/ c1 = -1.0; c2 = 0.0; l2 = 1; for (l=0;l<m;l++) { l1 = l2; l2 <<= 1; u1 = 1.0; u2 = 0.0; for (j=0;j<l1;j++) { for (i=j;i<n;i+=l2) { i1 = i + l1; t1 = u1 * x[i1] - u2 * y[i1]; t2 = u1 * y[i1] + u2 * x[i1]; x[i1] = x[i] - t1; y[i1] = y[i] - t2; x[i] += t1; y[i] += t2; } z = u1 * c1 - u2 * c2; u2 = u1 * c2 + u2 * c1; u1 = z; }
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c2 = sqrt((1.0 - c1) / 2.0); if (dir == 1) c2 = -1*c2; c1 = sqrt((1.0 + c1) / 2.0); } /* Scaling for forward transform */ if (dir == 2) { for (i=0;i<n;i++) { x[i] /= n; y[i] /= n; } } return(1); } void main() { short int dir; long m,t; int i,j=1; float *q,*w; float x[10],y[10]; clrscr(); q=&x[0]; w=&y[0]; printf("enter no of t point dft"); scanf("%ld",&t); m=log(t)/log(2); for(i=0;i<m;i++) j*=2; printf("enter no's"); for(i=0;i<j;i++) { scanf("%f",&x[i]); scanf("%f",&y[i]); } printf("\n\t1 --------> fft\n"); printf("\t2 --------> ifft"); printf("\n\nenter your choice"); scanf("%d",&dir); FFT(dir,m,q,w); printf("\n o/p of given sequence\n\n"); for(i=0;i<j;i++) { printf("%f + %fi\n",x[i],y[i]); }
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getch(); }
Result:
Enter no of t point dft:- 8 11 11 11 11 11 11 11 11 1 --------> fft 2 --------> ifft Enter your choice:-1 o/p of given sequence 8.000000 + 8.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i 0.000000 + 0.000000i
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7. Addition of two sinusoidal signals

Aim: To write a MATLAB program for addition of two sinusoidal signals. Algorithm:
Step 1: Get the number of samples for both sinusoids. Step 2: Take the input values, number of cycles of both sinusoids Step 3: Generate the sinusoids using function sin (x) Step 4: Add the two sinusoids. Step 5: Plot the output.
Model Output:
First Signal 1 Amplitude 0 -1
10
20
30
40 50 60 Discrete time Second Signal
70
80
90
100
Amplitude
1 0 -1 0 10 20 30 40 50 60 Discrete time SUM=x1+x2 Signal 70 80 90 100
2 Amplitude 0 -2
10
20
30
40 50 60 Discrete time
70
80
90
100
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8. Frequency response of analog IIR low pass filters

Aim: To find frequency response of IIR Butterworth analog LP filter Theory:
The Butterworth filter is designed to have a frequency response which is as flat as mathematically possible in the passband. Another name for this filter is 'maximally flat magnitude' filters. The frequency response of the Butterworth filter is maximally flat (has no ripples) in the passband, and rolls off towards zero in the stopband. Butterworth filters have a monotonically changing magnitude function with . The Butterworth is the only filter that maintains this same shape for higher orders (but with a steeper decline in the stopband) whereas other varieties of filters (Bessel, Chebyshev, elliptic) have different shapes at higher orders. Compared with a Chebyshev Type I/Type II filter or an elliptic filter, the Butterworth filter has a slower roll-off, and thus will require a higher order to implement a particular stopband specification. However, Butterworth filter will have a more linear phase response in the passband than the Chebyshev Type I/Type II and elliptic filters. The magnitude function of the Butterworth lowpass filter is given by
H ( j ) =
MATLAB program:
[1 + ( / ) ]
c
2N 1 / 2
N = 1,2,3,
w1=input('enter pass band cutoff frequency:'); w2=input('enter stop band cutoff frequency:'); rp=input('enter pass band ripple in db'); rs=input('enter stop band ripple in db'); fs=input('enter the sampling frequency'); w1=2*wp/fs; w2=2*ws/fs; [N,wn]=buttord(w1,w2,rp,rs,'s'); %[z,p,k]=butter(N,wn); %[b,a]=zp2tf(z,p,k); [b,a]=butter(N,wn,'s'); w=0:0.01:pi; [h,omega]=freqs(b,a,w); gain=20*log10(abs(h)); an=angle(h); subplot(2,1,1); title('mag res of lpf');
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plot(omega/pi,gain); ylabel('gain in db-------->'); xlabel('normalized frequency------>'); subplot(2,1,2); title('p res lpf'); plot(omega/pi,an); xlabel('normalized frequency---->'); ylabel('phase in radians---->')
Result:
enter pass band cutoff frequency:1500 enter stop band cutoff frequency:3000 enter pass band ripple in db10 enter stop band ripple in db40 enter the sampling freqency7000 b = 0 0 0 0 0 0 0.0040 a = 1.0000 1.5372 1.1815 0.5757 0.1870 0.0385 0.0040
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9. Power spectrum of a signal

Aim: To obtain power spectrum of given signal using MATLAB. Theory: In statistical signal processing the power spectral density is a positive real function of a frequency variable associated with a stationary stochastic process, or a deterministic function of time, which has dimensions of power per Hz, or energy per Hz. It is often called simply the spectrum of the signal. Intuitively, the spectral density captures the frequency content of a stochastic process and helps identify periodicities. The PSD is the FT of autocorrelation function, R() of the signal if the signal can be treated as a wide-sense stationary random process. MATLAB Program:
t = 0:0.001:0.6 x = sin(2*pi*50*t)+sin(2*pi*120*t) y = x+2*randn(size(t)); subplot(211) plot(1000*t(1:50),y(1:50)) title('signal corrupted with noise') xlabel('time (milliseconds)') y = fft(y,512) Pyy = y.*conj(y)/512; f = 1000*(0:256)/512; subplot(212) plot(f, Pyy(1:257)) title('Power spectrum of y'); xlabel('Frequency (Hz)');
Output:
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10. Real Time implementation Fast Fourier Transform (FFT)

Aim: To find the FFT of given 1-D signal and plot. Theory: The DFT Equation is
FFT Algorithm:
Decimation In Time method: 1. Pad input sequence, of N samples, with ZERO's until the number of samples is the nearest power of two. e.g. 500 samples are padded to 512 (2^9) 2. Bit reverse the input sequence. e.g. 3 = 011 goes to 110 = 6 3. Compute (N / 2) two sample DFT's from the shuffled inputs. 4. Compute (N / 4) four sample DFT's from the two sample DFT's. 5. Compute (N / 2) eight sample DFT's from the four sample DFT's. Until all the samples combine into one N-sample DFT
ALGORITHM :
Step 1 - Select number of points for FFT Step 2 Generate a sine wave of frequency f (eg: 10 Hz with a sampling rate = No. of points of FFT using math library function. Step 3 - Take sampled data and apply FFT algorithm . Step 4 Use Graph option to view the Input & Output. Step 5 - Repeat Step-1 to 4 for different number of points & frequencies.
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C PROGRAM: Main.c (fft 256.c): #include <math.h> #define PTS 64 //# of points for FFT #define PI 3.14159265358979 typedef struct {float real,imag;} COMPLEX; void FFT(COMPLEX *Y, int n); //FFT prototype float iobuffer[PTS]; //as input and output buffer float x1[PTS]; //intermediate buffer short i; //general purpose index variable short buffercount = 0; //number of new samples in iobuffer short flag = 0; //set to 1 by ISR when iobuffer full COMPLEX w[PTS]; //twiddle constants stored in w COMPLEX samples[PTS]; //primary working buffer
main() { for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w { w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants w[i].imag =-sin(2*PI*i/(PTS*2.0)); //Im component of twiddle constants } for (i = 0 ; i < PTS ; i++) //swap buffers { iobuffer[i] = sin(2*PI*10*i/64.0);/*10- > freq; /* 64 -> sampling freq*/ samples[i].real=0.0; samples[i].imag=0.0; } for (i = 0 ; i < PTS ; i++) //swap buffers { samples[i].real=iobuffer[i]; //buffer with new data } for (i = 0 ; i < PTS ; i++) samples[i].imag = 0.0; //imag components = 0 FFT(samples,PTS); //call function FFT.c for (i = 0 ; i < PTS ; i++) //compute magnitude { x1[i] = sqrt(samples[i].real*samples[i].real + samples[i].imag*samples[i].imag); } } //end of main fft.c: #define PTS 64 //# of points for FFT typedef struct {float real,imag;} COMPLEX;
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extern COMPLEX w[PTS];
//twiddle constants stored in w
void FFT(COMPLEX *Y, int N) //input sample array, # of points { COMPLEX temp1,temp2; //temporary storage variables int i,j,k; //loop counter variables int upper_leg, lower_leg; //index of upper/lower butterfly leg int leg_diff; //difference between upper/lower leg int num_stages = 0; //number of FFT stages (iterations) int index, step; //index/step through twiddle constant i = 1; //log(base2) of N points= # of stages do { num_stages +=1; i = i*2; }while (i!=N); leg_diff = N/2; //difference between upper&lower legs step = (PTS*2)/N; //step between values in twiddle.h for (i = 0;i < num_stages; i++) //for N-point FFT { index = 0; for (j = 0; j < leg_diff; j++) { for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff)) { lower_leg = upper_leg+leg_diff; temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real; temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag; temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real; temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag; (Y[lower_leg]).real = temp2.real*(w[index]).real -temp2.imag*(w[index]).imag; (Y[lower_leg]).imag = temp2.real*(w[index]).imag +temp2.imag*(w[index]).real; (Y[upper_leg]).real = temp1.real; (Y[upper_leg]).imag = temp1.imag; } index += step; } leg_diff = leg_diff/2; step *= 2; } j = 0; for (i = 1; i < (N-1); i++) //bit reversal for resequencing data {
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k = N/2; while (k <= j) { j = j - k; k = k/2; } j = j + k; if (i<j) { temp1.real = (Y[j]).real; temp1.imag = (Y[j]).imag; (Y[j]).real = (Y[i]).real; (Y[j]).imag = (Y[i]).imag; (Y[i]).real = temp1.real; (Y[i]).imag = temp1.imag; } } return;}
Input:
Output:
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5. Additional Experiments 1. Periodic waveform generation

Aim: To generate the following periodic waveforms for the given number of cycles and frequency respectively using MATLAB. 1 Sine waveform 2 Saw tooth waveform 3 Square waveform Theory:
Waveform means the shape and form of a signal such as a wave moving in a solid, liquid or gaseous medium. In many cases the medium in which the wave is being propagated does not permit a direct visual image of the form. In these cases, the term 'waveform' refers to the shape of a graph of the varying quantity against time or distance. An instrument called an oscilloscope can be used to pictorially represent the wave as a repeating image on a CRT or LCD screen. Common periodic waveforms include
Sine wave: The amplitude of the waveform follows a trigonometric sine function with respect to time. Saw tooth wave: This looks like the teeth of a saw and found often in time bases for display scanning. It is used as a saw tooth wave of constant period. Square wave: This waveform is commonly used to represent digital information. Triangle wave: This is the integral of the square wave. Algorithm:
Step 1: Take inputs, frequency and time . Step 2: Generate Sine waveform using function, sin(x) Step 3: Generate Square waveform using function, square(x) Step 4: Generate sawtooth waveform using function, sawtooth (x) Step 5: Plot the output
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Model Output:
------->amplitude
sinusoidal waveform 1 0 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 ---------->time 0.07 0.08 0.09 0.1
------->amplitude
sawtooth waveform 1 0 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 ---------->time 0.07 0.08 0.09 0.1
square waveform ------> m litu e a p d 1 0 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 ---------->time 0.07 0.08 0.09 0.1
2. Complex exponential series

Aim: To generate a complex exponential series of the form y = kecn where k is constant, c is the complex number and to plot the real and imaginary parts of y using MATLAB. Theory:
In general, raising e to a positive integer exponent has a simple interpretation in terms of repeated multiplication of e. Raising e to zero or a negative integer exponent can be understood as repeated division. A rational number exponent can be defined by radicals of e, and an irrational number exponent can be defined by finding rationalnumber exponents that are arbitrarily close to the irrational-number exponent, in a limit process. However, to define and understand a complex number exponent of e, a different type of generalization is required for the concept of exponentiation.
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Department of Electronics and Communication Engineering Algorithm:
Step 1: Get a complex number as input Step 2: Get a constant value (K) as another input Step 2: Generate exponential series using the form of Y = Kecn Step 3: Separate the real and imaginary parts Step 3: Plot the real and imaginary sequences separately.
Model Output:
real part 0.4 --amplitude 0.2 0 -0.2 -0.4 0 2 4 6 8 10 12 --------->n imaginary part 14 16 18 20
0.8 --amplitude 0.6 0.4 0.2 0 0 2 4 6 8 10 12 --------->n 14 16 18 20
4. Magnitude and phase response of a system

Aim: To obtain the polezero plot and magnitude and phase responses of a LTI system. Theory:
The Fourier transform of a LTI system input and output are related by
Y(ejw)=H(ejw) X(ejw). where Y(ejw) and X(ejw) are the Fourier transforms of system input and output and the complex frequency response of a LTI system is given as:
With the frequency response expressed in polar form, the magnitude and phase of the Fourier transforms of the system input and output are related by |Y(ejw)|=|H(ejw) X(ejw) Y(ejw)= H(ejw)+ X(ejw)
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Department of Electronics and Communication Engineering Algorithm:
Step1: Take input for coefficients a and b Step 2: Get the frequency response using the function, freqz( ). Step 3: Obtain the magnitude response using the function, abs( ) Step 4: Get the phase response using function, angle( ) Step 4: Plot the pole-zero plot and responses separately.
Model Output:
magnitude response 2 amplitude 1 0
0.5
1.5 interval phase response
2.5
amplitude
0 -0.2 -0.4 0 0.5 1 1.5 interval Z-plane 2 2.5 3
1 Imag(Z) 0 -1 -5 0 Real(Z) 5
5. Impulse and Step responses of a LTI system

Aim: To obtain unit impulse and unit step responses of a LTI system. Algorithm:
Step 1: Take coefficients a, b of an LTI system. Step 2: Take Impusle as input. Step 3: Find the response of a LTI system by using function filter(). Step 4: Plot the response. Step 5: Take Step as input. Step 6: Find the response of a LTI system by using function filter(). Step 7: Plot the response.
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MATLAB Output:
6. Moving Average Filter

Aim: To write a MATLAB program for moving average filter to filter a corrupted exponential sequence. Theory: The general moving average system is defined by equation
Y[n]= 1/(M1+M2+1)*
k = M1
X[n k]
M2
= 1/(M1+M2+1) *{X[n+M1]+X[n+M1-1] +...+X[n]+X[n-1] ++ X[n-M2]} This system computes the nth sample of the output sequence as the average of (M1+M2+1) samples of the input sequence around the nth sample.
Program:
r= 50; d= rand(r,1)-0.5; m=0:1:r-1; s=2*m.*(0.9.^m); x=s+d'; plot(m,d,'-',m,s,'--',m,x,':'); legend('d[n]','s[n]','x[n]'); grid

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xlabel('time index'); ylabel ('amplitude'); pause n=input('Number of input samples:'); b=ones(n,1)/n; y=filter(b,1,x); plot(m,s,'-',m,y,'--'); legend('s[n]','y[n]'); grid xlabel('------> n'); ylabel('Amplitue');
input:
Number of input samples: 5

Output:
8 7 6 5 amplitude 4 3 2 1 0 -1 d[n] s[n] x[n]
10
15
20
25 30 time index
35
40
45
50
Input and corrupted signals

8 7 6 5 Amplitue 4 3 2 1 0 s[n] y[n]
10
15
20
Corrupted and filtered signals
25 ------> n
30
35
40
45
50
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7. Auto correlation
Aim: To find the auto correlation of two given sequences. Theory: Autocorrelation is a mathematical tool for finding repeating patterns, such as the presence of a periodic signal which has been buried under noise, or identifying the missing fundamental frequency in a signal implied by its harmonic frequencies. It is used frequently in signal processing for analyzing functions or series of values, such as time domain signals. Informally, it is the similarity between observations as a function of the time separation between them. More precisely, it is the cross-correlation of a signal with itself. Algorithm:
Step 1: Enter the sequence x[n]. Step 2: Find the length of sequence, N. Step 3: Add N-1 zeros to the given sequence. Step 4: Create another sequence h[n]=x[n]. Step 5: Obtain h[n-l] by shifting the sequence right by delay l. Step 6: Multiply h[n-l] by x[n] and sum all the values to obtain y[l] Step 7: Repeat the steps 5 & 6 for all values of l. Step 8: Plot the output y[n].
Program:
x=input('Enter any sequence X:') h=x n1=length(x) n2=length(h) p=n1+n2-1 x=[x zeros(1,p-n1)] h=[zeros(1,p-n2) h] for t=1:p sum=0 for k=1:t sum=sum+[x(k)*h(k-t+p)] end y(t)=sum end subplot(311) stem(x) axis([0 7 0 5]) xlabel('n'),ylabel('x(n)') subplot(312) stem(h) axis([0 7 0 5])
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xlabel('n'),ylabel('h(n)') subplot(313) stem(y) axis([0 10 0 40]) xlabel('lag index'),ylabel('y(n)')

Inputs:
Enter any sequence X: [1 2 3 4]

Output:
4 11 20 30 20 11
Output:
5 x(n) 0 0
3 n
5 h(n) 0 0
3 n
40 y(n) 20 0
5 lag index
10
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8. Cross correlation
Aim: To obtain the cross correlation of two given sequences by using MATLAB and C. Theory: The cross-correlation is a measure of similarity of two signals, commonly used to find features in an unknown signal by comparing it to a known one. It is a function of the relative time between the signals, is sometimes called the sliding dot product, and has applications in pattern recognition and cryptanalysis. The cross-correlation is similar in nature to the convolution of two functions. Correlation only involves shifting it and multiplying (no reversing) whereas convolution involves reversing a signal, then shifting it and multiplying by another signal.
yx(l) = y(n+l)x(n)
n=
Algorithm:
Step 1: Enter the sequence of x[n]. Step 2: Find the length of sequence (N). Step 3: Add N-1 zeros to the given sequence. Step 4: Enter another sequence y[n]. Step 5: Obtain y[n-l] by shifting the sequence right by delay l. Step 6: Multiply y[n-l] by x[n] and sum all the values to obtain [l] Step 7: Repeat the steps 5& 6 for all values of l. Step 8: Plot the output [n].
MATLAB Program:
x=input('Enter any sequence X:'); h=input('Enter any sequence H:'); n1=length(x); n2=length(h); j=0:1:n1-1; l=0:1:n2-1; p=n1+n2-1; x=[x zeros(1,p-n1)]; h=[zeros(1,p-n2) h]; for t=1:p; sum=0; for k=1:t; sum=sum+[x(k)*h(k-t+p)]; end y(t)=sum; end
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subplot(311); stem(x); axis([0 6 0 5]); xlabel('n'),ylabel('x(n)'); subplot(312); stem(h); axis([0 6 0 5]); xlabel('n'),ylabel('h(n)'); subplot(313); stem(y); axis([0 10 0 10]); xlabel('lag index'),ylabel('y(n)'); title('Cross Correlation');
Input:
Enter any sequence X: [1 2 3 4] Enter any sequence H: [4 3 2 1]

Outputs:
4 10 20 25 24 16
Output:
x(n)
4 n
h(n)
4 5 n Cross Correlation
30 y(n) 20 10 0 0 1 2 3 4 5 lag index 6 7 8 9 10
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9. Discrete Fourier Transform

Aim: To obtain the discrete fourier transform (DFT) of a given input discrete time sequence. Theory: The DFT transforms one function in time domain into another, which is called the frequency domain representation, or simply the DFT, of the original function (which is often a function in the time domain). But the DFT requires an input function that is discrete and whose non-zero values have a limited (finite) duration. Such inputs are often created by sampling a continuous function, like a person's voice. Since the input function is a finite sequence of real or complex numbers, the DFT is ideal for processing information stored in computers. Algorithm :
Step 1: Take length of input sequence. Step 2: Take input values of X[n] Step 3: Find the sum of real values by using X[n]*cos((2*3.14285714*n*k)/len Step 4: Find the sum of imaginary values by using X[n]*sin((2*3.14285714*n*k)/len Step 5: Add the real and imaginary parts to get the result.
C Program:
#include<stdio.h> #include<conio.h> void main() { double yr[10], yi[10], sumi=0, sumr=0; int x[10], i,k,n,len; printf("enter the length of sequence:"); scanf("%d", &len); for(i=0;i<Len;i++) { printf("enter the x[%d]=",i); scanf("%d",&x[i]); } for(k=0;k<len;k++) { sumr=0; sumi=0; for(n=0,n<len;n++) { sumr = sumr+(x[n]*cos((2*3.14285714*n*k)/len); sumi = sumi+(x[n]*sin((2*3.14285714*n*k)/len); }
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yr[k]=sumr; yi[k]=-1*sumi; } printf("the result is :\n"); for(i=0;i<len;i++) { if(yi[i]>=0) { printf("yr[%d]+jyi[%d] = %lf+%lfj",i,i,yr[i],yi[i]); printf("\n"); } else { printf("yr[%d]+jyi[%d] = %lf%lfj",i,i,yr[i],yi[i]); printf("\n"); } } }
Input:
Enter The Length Of Sequence : 4 Enter the x[0]: 1 Enter the x[1]: 1 Enter the x[2]: -2 Enter the x[3]: -2
Output:
yr[0] + j yi[0] = -2.000000 + 0.000000j yr[1] + j yi[1] = 2.995573 - 3.002525j yr[2] + j yi[2] = -0.000007 - 0.001264j yr[3] + j yi[3] = 3.013263 + 2.992379j
10. Butterworth Lowpass filter

Aim: To obtain frequency response characteristics of Butterworth Lowpass filter. Algorithm:
Step 1: Take passband, stopband frequencies and attenuations. Step 2: Find cutoff frequency and order of the filter by using the function, buttord( ) Step 3: Calculate system function (a and b coefficients) using a function, butter( ). Specify the type of filter (LPF, HPF or BPF). Step 4: Obtain the frequency response using the function freqz( ). Step 5: Plot the output.
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Department of Electronics and Communication Engineering Model output:

200 0 -200 -400 -600 0 0.1 0.2 0.3 0.4 0.5 0.6 Normailzed frequency 0.7 0.8
Gain in dB
0.9
4 Phase in radians 2 0 -2 -4 0 0.1 0.2 0.3 0.4 0.5 0.6 Normailzed frequency 0.7 0.8 0.9 1
11. Chebyshev type-I bandpass filter

Aim: To obtain frequency response charcterstics of IIR chebyshev type1 bandpassfilter. Theory: Type I chebyshev filters are all pole filters that exhibit equi ripple behavior in the passband and a monotonic characteristic in the stopband. The analog lowpass type I chebyshev filter is optimum all pole filter because for given order N and given passband and stopband constrains; no other all-pole filter has narrower transition bandwidth. Its magnitude response is given by (H (j 2 =1/( +2T2N( ) )) 1 / P a Where is a constant parameter of the filter related to the ripple in the passband Algorithm:
Step 1: Take the passband, stopband frequencies and attenuations. Step 2: Find the cutoff frequency and order of the filter by using function, cheb1ord ( ). Step 3: Calculate system function using cheby1 command.(Specify which type of filter characteristics.) Step 4: Obtain the frequency response using the function, freqz( ). Step 5: Plot the output.
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1 --------->gain
0.5
100
200
300
400 500 600 --------->frquency
700
800
900
1000
--------->phase in degrees
4 2 0 -2 -4 0 100 200 300 400 500 600 --------->frquency 700 800 900 1000
12. IIR Chebyshev type-II highpass filter

Aim: To obtain frequency response charcterstics of IIR chebyshev type2 highpassfilter. Theory: There are two types of chebyshev filters, namely type I and type II. The type II chebyshev filters contain both poles and zeros and exhibit monotonic behavior in the passband and equi-ripple behavior in the stopband. Algorithm:
Step 1: Take passband, stopband frequencies and attenuations. Step 2: To find cutoff frequency and order of the filter by using cheb2ord command. Step 3: Calculate system function using cheby2 command.(Specify which filter characteristics.) Step 4: Obtain the frequency response using freqz command. Step 5: Plot the output.
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13. Addition of two 32-bit numbers

Aim: To add two 32 bit fixed point numbers using assembly language program. Program:
.global _main _main: mvkl .s1 3250h,a6 mvkl .s1 9532h,a6 mvkh .s1 00013250h,a2 mvkh .s1 12349532h,a2 addu .l1 a6,a2,a9:a8 b b3 nop 5
Output:
A6:0001 3250 A2:1234 9532 A8:1235 C782
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Department of Electronics and Communication Engineering Register output in CCS Simulator:
14. Subtraction of two 16-bit numbers

Aim: To subtract two 16 bit numbers using assembly language program. Program:
.global _main _main: mvkl .s1 5688h,a2 mvkl .s2 1469h,b1 mvkh .s1 0000h,a2 mvkh .s2 0000h,b1 sub .l2 a2,b1,b0 b b3 nop5
Output:
A2:5688h B1:1469h B0:0000421F
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15. Multiplication of two 16-bit numbers

Aim: To obtain multiplication of two 16 bit numbers using assembly language program. Program:
.global _main _main: mvkl .s1 6178h,a2 mvkl .s2 2121h,b1 mpy .m2 a2,b1,b0 b b3 nop 5 Output: A2:6178h B1:2121h B0:0C9D0878
16. Real Time Implementation of FIR Filter

Aim: To design and implement a Digital FIR Filter & observe its frequency response. Equipment needed: 1. PC 2. TMS320C6713 DSP Starter Kit (DSK). 3. Oscilloscope and Function generator. Design of FIR filter: 1. Clearly specify the filter specifications. Eg: Order = 30; Sampling Rate = 8000 samples/sec, Cut off Freq. = 400 Hz. 2. Compute the cut-off frequency Wc Eg: Wc = 2*pie* fc / Fs, = 2*pie* 400/8000 = 0.1*pie 3. Compute the desired Impulse Response h d (n) using particular Window Eg: b_rect1=fir1(order, Wc , 'high',boxcar(31)); 4. Convolve input sequence with truncated Impulse Response x (n)*h (n) Determination of filter coefficients: B = FIR1(N,Wn) designs an Nth order lowpass FIR digital filter and returns the filter coefficients in length N+1 vector B. The cut-off frequency must be 0 < Wn < 1.0, with Wn = 1.0 corresponding to half the sample rate. B = FIR1(N,Wn,'high') designs a highpass filter and B = FIR1(N,Wn,'stop') is for a bandstop filter if Wn = [W1 W2]. MATLAB program to generate FIR Filter-Low Pass Coefficients: % FIR Low pass filters using rectangular window % sampling rate - 8000 order = 30; cf = 2 * 500/8000; cf--> cut-off frequency [Wc ]
b_rect1=fir1(order,cf(1),boxcar(31)); % Rectangular
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Flow Chart to implement FIR filter:
Start
Initialize the DSP Board.
Take a new input in data from the analog in of codec
Initialize Counter = 0 Initialize Output = 0 , i = 0
Output += coeff[N-i]*val[i] Shift the input value by one
No Is the loop Cnt = order Poll the ready bit, when asserted proceed. Yes Output += coeff[0]*data Put the data in val array.
Write the value Output to Analog output of the codec
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Department of Electronics and Communication Engineering C Program:
#include "filtercfg.h" #include "dsk6713.h" #include "dsk6713_aic23.h" float filter_Coeff[] ={0.000000,-0.001591,-0.002423,0.000000,0.005728, 0.011139,0.010502,-0.000000,-0.018003,-0.033416,-0.031505,0.000000, 0.063010,0.144802,0.220534,0.262448,0.220534,0.144802,0.063010,0.000000, -0.031505,-0.033416,-0.018003,-0.000000,0.010502,0.011139,0.005728, 0.000000,-0.002423,-0.001591,0.000000 }; static short in_buffer[100]; DSK6713_AIC23_Config config = {\ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Leftline input channel volume */\ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume*/\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */\ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */\ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */\ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */\ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */\ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */\ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */\ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; /* * main() - Main code routine, initializes BSL and generates tone */ void main() { DSK6713_AIC23_CodecHandle hCodec; Uint32 l_input, r_input,l_output, r_output; /* Initialize the board support library, must be called first */ DSK6713_init(); /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config); DSK6713_AIC23_setFreq(hCodec, 1); while(1)
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{ /* Read a sample to the left channel */ while (!DSK6713_AIC23_read(hCodec, &l_input)); /* Read a sample to the right channel */ while (!DSK6713_AIC23_read(hCodec, &r_input)); l_output=(Int16)FIR_FILTER(&filter_Coeff ,l_input); r_output=l_output; /* Send a sample to the left channel */ while (!DSK6713_AIC23_write(hCodec, l_output)); /* Send a sample to the right channel */ while (!DSK6713_AIC23_write(hCodec, r_output)); } /* Close the codec */ DSK6713_AIC23_closeCodec(hCodec); } signed int FIR_FILTER(float * h, signed int x) { int i=0; signed long output=0; in_buffer[0] = x; /* new input at buffer[0] */ for(i=30;i>0;i--) in_buffer[i] = in_buffer[i-1]; /* shuffle the buffer */ for(i=0;i<31;i++) output = output + h[i] * in_buffer[i]; return(output); }
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17. Linear Convolution

Aim: To verify Linear Convolution of two sequences using assembly language program and to view graphical output using CCS. Theory: Linear Convolution Involves the following operations. 1. Folding 2. Multiplication 3. Addition 4. Shifting
These operations can be represented by a Mathematical Expression as follows:
y[n] =
k =
x ( k ) h( n k )
x[ ]= Input signal Samples h[ ]= Impulse response co-efficient. y[ ]= Convolution output. n = No. of Input samples h = No. of Impulse response co-efficient.
Algorithm:
Eg:
x[n] = {1, 2, 3, 4} h[k] = {1, 2, 3, 4} ;Values of n & k should be a multiple of 4. If n & k are not multiples of 4, pad with zeros to make multiples of 4 ; Size of output sequence.
Where: n=4, k=4. r = n+k-1 = 4+4-1 = 7.
r= 0 1 2 3 4 5 6 n= 0 x[0]h[0] x[0]h[1] x[0]h[2] x[0]h[3] 1 x[1]h[0] x[1]h[1] x[1]h[2] x[1]h[3] 2 x[2]h[0] x[2]h[1] x[2]h[2] x[2]h[3] 3 x[3]h[0] x[3]h[1] x[3]h[2] x[3]h[3] Output: y[r] = { 1, 4, 10, 20, 25, 24, 16}.
NOTE: At the end of input sequences pad n and k no. of zeros
86
Department of Electronics and Communication Engineering ASSEMBLY PROGRAM:
X H
.global _main .half 1,2,3,4,0,0,0,0 ;input1, M=4 .half 1,2,3,4,0,0,0,0 ;input2, N=4 .bss Y,14,2 ;OUTPUT, R=M+N-1
; At the end of input sequences pad M and N no. of zeros _main: MVKL .S1 X,A4 MVKH .S1 X,A4 MVKL .S2 H,B4 MVKH .S2 H,B4 MVKL .S1 Y,A5 MVKH .S1 Y,A5 MVK .S2 7,B2 ;POINTER TO X ;POINTER TO H ;POINTER TO Y ;R=M+N-1
; MOVE THE VALUE OF RTO B2 FOR DIFFERENT LENGTH OF I/P SEQUENCES ZERO .L1 A7 ZERO .L1 A3 ;I=0 LL2: ZERO .L1 A2 ZERO .L1 A8 ;J=0, for(i=0;i<m+n-1;i++) LL1: LDH .D1 *A4[A8],A6 ; for(j=0;j<=i;j++) MV .S2X A8,B5 ; y[i]+=x[j]*h[i-j]; SUB .L2 A3,B5,B7 LDH .D2 *B4[B7],B6 NOP 4 MPY .M1X A6,B6,A7 ADD .L1 A8,1,A8 ADD .L1 A2,A7,A2 CMPLT .L2X B5,A3,B0 [B0] B .S2 LL1 NOP 5 STH .D1 A2,*A5[A3] ADD .L1 A3,1,A3 CMPLT .L1X A3,B2,A2 [A2] B .S1 LL2 NOP 5 B B3 NOP 5 To View output graphically Select view graph time and frequency.
87
Configure the graphical window as shown below
INPUT x[n] = {1, 2, 3, 4,0,0,0,0} h[k] = {1, 2, 3, 4,0,0,0,0} OUTPUT:
88

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Department of Electronics and Communication Engineering

Digital Signal Processing Lab

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD IV Year B.Tech. ECE I-Sem T 0 P 3 C 2

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Equipment and Software

2. CROs 12 No.s APLAB, 20 MHz Dual Trace

3. Function Generators 12 No.s APLAB, 3 MHz

6. Code Composer Studio Software

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Enter Matlab Functions

View or use previously run functions

Use tabs to go to workspace browser or current directory browser

Drag the separator bar to resize windows

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering Command Window:

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering FIR Filter Design:

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering The filter Function:

Digital Signal Processing Lab

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

2. Digital Signal Processors

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering C versus Assembly:

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering Introduction to TMS320C6713:

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Department of Electronics and Communication Engineering

Digital Signal Processing Lab

Department of Electronics and Communication Engineering Features of C6713 DSK:

Digital Signal Processing Lab

Fig 3.2 TMS320C6713 DSK Overview Block Diagram

Department of Electronics and Communication Engineering Introduction to CCS

Digital Signal Processing Lab

Softcopy of documents are available at: C:\CCStudio\docs\pdf.

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Digital Signal Processing Lab

Maharaj Vijayaram Gajapathi Raj College of Engineering, Vizianagaram

Digital Signal Processing Lab