CMOS CHIP DESIGN

Presented By M.BHUVANESWARI

Complementary MOS fabrication

CMOS Technology depends on using both N-Type and P-Type devices on the same chip. The two main technologies to do this task are: P-Well (Will discuss the process steps involved with this technology)
The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.

N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate, while the Pchannel device is built into a N-type well within the parent P-Type substrate.

Two more advanced technologies to do this task are:

Becoming more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes.

Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.

Silicon-on-Insulator (SOI) CMOS Process

SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.

P-well on N-substrate
Steps : N-type substrate Oxidation, and mask (MASK 1) to create P-well (4-5m deep) P-well doping
P-well acts as substrate for nMOS devices. The two areas are electrically isolated using thick field oxide (and often isolation implants [not shown here])
SiO2

P-well
N-type substrate

Polysilicon Gate Formation

Steps : Remove p-well definition oxide Grow thick field oxide Pattern (MASK 2) to expose nMOS and pMOS active regions Grow thin layer of SiO2 (~0.1m) gate oxide, over the entire chip surface Deposit polysilicon on top of gate oxide to form gate structure Pattern poly on gate oxide (MASK 3)

Thin gate oxide (SiO2)

Gate (patterned polysilicon on thin oxide)

Thick field oxide pMOS active region N-type substrate

nMOS active region

nMOS P+ Source/Drain difusion self-aligned to Poly gate

Implant P+ nMOS S/D regions (MASK 4)

P+ implant/diffusion

P+ mask

Thick field oxide N-type substrate

pMOS N+ Source/Drain difusion self-aligned to Poly gate

Implant N+ pMOS S/D regions (MASK 5 often the inverse of MASK 4)

N+ implant/diffusion N+ mask

P+ N-type substrate

N+

pMOS N+ Source/Drain difusion, contact holes & metallisation

Oxide and pattern for contact holes (MASK 6) Deposit metal and pattern (MASK 7) Passivation oxide and pattern bonding pads (MASK 8) P-well acts as substrate for nMOS devices. Two separate substrates : requires two separate substrate connections Definition of substrate connection areas can be included in MASK 4/MASK5
Vin N+ for N-substrate contact)
Vdd

Vout

Vss

P+ (for P-substrate contact)

P
P+
P channel Device

N+

N channel Device

N-type substrate

CMOS N-well process

An N-well process is also widely used

Vin

P+ for P-substrate Vdd contact)

Vout

Vss

N+ (for Nsubstrate contact)

N+

N channel Device

P+

N-well
P channel Device

P-type substrate

MOS Transistor
0 Volts S (Source) 0 Volts G (Gate)

VDD Volts D (D rain)

n-ChannelTransistor OFF - no D-to-S Cur : rent

Channel length

Location of conducting layer

Substrate

MOS Transistor
0 Volts S (Source) n-Channel Transistor: ON - D -to-S Current V D D Volts G (Gate) V D D Volts D (D rain)

Channel length

Location of conducting layer

Substrate

Switch Models for MOS Transistors

n-Channel Normally Open (NO) Switch Contact
D G
X

X:
S Symbol

X:X
Simplifed Switch M odel

Switch M odel:

p-Channel Normally Closed (NC) Switch Contact

S G
X

D Symbol

X:

X:X
Simplified Switch M odel

Switch M odel

Circuits of Switch Models

Series
X: X

X A ND Y
Y: Y

Series

Parallel
X: X Y: Y X OR Y

Parallel

Fully-Complementary CMOS Circuit

Circuit structure for fully-complementary CMOS gate logic 1 +V

F using p-type transistors (NC switches)

X1 X2

Xn

F using n-type transistors (NO switches) logic 0 General Structure

CMOS Circuit Design Example

Find a CMOS gate with the following function: F = X Z + Y Z = (X + Y)Z Beginning with F0, and using F
The switch model circuit in terms of NO switches:
X: X Y: Y Z: Z
F0 Circuit: F = X Y + Z

CMOS Circuit Design Example

The switch model circuit for F1 in terms of NC contacts is the dual of the switch model circuit for F0:

X : X Y: Y Z: Z
The function for this circuit is:

F1 Circuit: F = (X + Y) Z which is the correct F.

CMOS Circuit Design Example

Replacing the switch models with CMOS transistors; note input Z must be used.

CMOS Inverter
A 0 1 Y

VDD A Y

GND

CMOS Inverter
A 0 1 Y

VDD OFF
A=1 Y=0

ON
A Y

GND

CMOS Inverter
A 0 1 Y 1 0
A=0

VDD ON
Y=1

OFF
A Y

GND

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y

Y A B

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1

ON A=0 B=0

ON Y=1 OFF OFF

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1

OFF A=0 B=1

ON Y=1 OFF ON

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1

ON A=1 B=0

OFF Y=1 ON OFF

CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0

OFF A=1 B=1

OFF Y=0 ON ON

CMOS NOR Gate

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0

A B Y

3-input NAND Gate

Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
Y A B C

Inverter Cross-section
Typically use p-type substrate for nMOS transistor
Requires n-well for body of pMOS transistors A GNDSeveral alternatives: SOI, twin-tub, etc. V Y
DD

SiO2 n+ diffusion

n+

n+ p substrate

p+ n well

p+

p+ diffusion polysilicon metal1

nMOS transistor

pMOS transistor

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms A poor connection called Shottky Diode GND V Y Use heavily doped well and substrate contacts / taps n+ p+ n+ p+ p+ n+
DD

n well p substrate substrate tap well tap

Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line
A

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

Detailed Mask Views

Six masks
n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

 Start with blank wafer Build inverter from the bottom up First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate

Fabrication Steps

Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light

Photoresist SiO2

p substrate

Lithography
Expose photoresist through n-well mask Strip off exposed photoresist

Photoresist SiO2

p substrate

Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

Photoresist SiO2

p substrate

Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

SiO2

p substrate

n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si

Ion Implanatation
Blast wafer with beam of As ions n well Ions blocked by SiO2, only enter exposed Si
SiO2

Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

n well p substrate

Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
n well p substrate

Polysilicon Thin gate oxide

Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and nwell contact

n well p substrate

N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

n+ Diffusion

n well p substrate

N-diffusion
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n+

n+ n well p substrate

n+

N-diffusion
Strip off oxide to complete patterning step

n+

n+ n well p substrate

n+

P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Metallization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

Metal

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Twin tub Process

Process sequence
a. Tub formation b. Thin-Oxide construction c. Source & drain implantations d. Contact cut definition e. Metallization

Processing Steps:
Substrate Selection

 Anisotropic etch:

 From P- island for N-Device:

 From N-island for P-device:

 Growth & oxide through thermal oxidation:

 Deposit Doped Silicon:

 Etch polysilicon:

 N-Implantation for Source & Drain:

 P-Implantation:

 Grow phosphorus glass Etch glass to form contact cut Evaporating Alumini

Balanced performance of n and p devices can be constructed

SILICON ON INSULATOR
What is SOI? Characteristics of SOI Fabrication methods Basic categorization Electrical anomalies Advantages and Disadvantages

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What is SOI?
-SOI Silicon-onInsulator
-Si layer on top of an insulator layer to build active devices and circuits. -The insulator layer is usually made of SiO2

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Characteristics

Include: - High speed - Low power - High device density - Easier device isolation structure
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SOI Fabrication Processes

-SOS Silicon-on-Sapphire -SIMOX Separation by Implantation of Oxygen -ZMR Zone melting and recrystallization -BESOI Bond and Etchback SOI -Smart-cut SOI Technology

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Categorization
-Categorization based on the thickness of the silicon film. -The first is a partially-depleted device and the latter is a fullydepleted device.
-Each has its own advantages and disadvantages.

-PD device threshold voltage is insensitive to film thickness.

-FD device has reduced short channel and narrow channel effects.
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Electrical anomalies
Floating-body effect: -Usually seen in PartiallyDepleted devices. - As shown in figure, the MOS structure is accompanied by a parasitic bipolar device in parallel.
-The base of this device is floating.

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Electrical anomalies
Kink Effect: -Sudden discontinuity in drain current. -Seen when the device is biased in the saturation region. -The bipolar device is turned on. Solution: -Provide a body contact for the device. - Use FD devices.

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Electrical anomalies
Self-heating effect: Thermal insulation is provided by the oxide surface. Heat dissipation is not efficient. This happens only when there is logic switching in the device.

In fully-depleted devices, the threshold voltage is sensitive to the thickness of the silicon film. Manufacturing process is comparatively difficult.

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Advantages of SOI
Suitable for high-energy radiation environments.
Parasitic capacitances of SOI devices are much smaller.

No latch-up.

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Advantages
Easier device isolation
-

-High device density -Easier scale-down of threshold voltage.

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Uses in digital and analog circuits

A combination of FD and PD devices are used in digital circuitry.

Superior capabilities of SOI CMOS technology usage in memory cell implementation.

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Uses in digital and analog circuits

SOI technology is useful for implementing highspeed op-amps given its low Vt.
Higher transconductance (especially of FD) implies higher gain.

Lower power consumption compared to bulk devices at low current level.

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Disadvantages
Major bottleneck is high manufacturing costs of the wafer. Floating-body effects impede extensive usage of SOI. Device integration dopant reaction with the oxide surface. Electrical differences between and SOI nad bulk devices.
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Conclusion
Due to its characteristics, SOI is fast becoming a standard in IC fabrication.
Several companies have taken up SOI manufacturing.

High-volume production of SOI is yet to become common.

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Interconnect
(i).Metal Interconnect Polysilicon & diffusion (N+,P+)

Lay out Diagram:

 (ii).Poly Interconnect:

 (iii).Local Interconnect:

Circuit Elements:

Latchup problem:
Latchup : Shorting of VDD and Vss lines Chip breakdown Latchup Equivalent Circuit: Vertical : pnp p = source/drain of p device (Emitter) n = n-well (Base) p = p-substrate (Collector)

Lateral : npn n = source/drain of n device (Emitter) p= p-substrate (Base) n= n-well (Collector) Rsubstrate, Rwell Parasitic devices and resistors

 Latch up Problem:

 Equivalent Circuits:

 Characteristics curve:

THANK U