Stability of systems with DCDC converters

F.Faccio, S.Michelis, G.Blanchot, C.Fuentes, B.Allongue - CERN/PH/ESE Many thanks to: G.Spiazzi and S.Buso - Padova University, DEI/PEL S.Saggini - Udine University K.Klein and W.Karpinski - RWTH Aachen

Outline
DCDC converters compensation Effect of the load impedance Effect of the input lter impedance Case system study: CMS pixels phase 1 upgrade Conclusion

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Foreword
The generic title Stability of DCDC converters is conceptually wrong, but the correct one would have been a little elusive: System stability issues in the use of Point-of-Load Buck converters. The stability of the line conditioner converter (or Power Supply) will not be discussed
Example Distributed Power System
POL DCDC Line conditioner (or PS)

Anything

POL DCDC POL DCDC

The presentation contains simplications for the purpose of clarity. Simulation results are however accurate All simulations use behavioral model of AMIS4 DCDC ASIC, using the SIMPLIS simulator from Simetrix technologies Switching @ 2MHz Use inductance of 200nH Transfer functions corner frequency 120kHz
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General DCDC converter

Vsource

RLoad

PWM

Compensator

Sensor

Vref

T(s) = loop gain = product of all gains around forward and feedback paths of the loop

Vref

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General DCDC converter

Vsource

RLoad
Vsource

RLoad

PWM
PWM

Compensator
Compensator

Sensor
Sensor

Vref Vref

T(s) = loop gain = product of all gains around forward and feedback paths of the loop

Vref

Vref

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Design of compensator
RLoad PWM Compensator

Inappropriate PI compensator
Sensor Vref

Loop gain T(s)

magnitude dB phase margin (deg) Load current (A) V at load (V)

Vref

Time-domain load transient

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Vsource

RLoad

PWM

Compensator

Sensor

Design of compensator
RLoad PWM Compensator

Vref

Inappropriate PI compensator
Sensor Vref

Appropriate PID compensator

Vref

Loop gain T(s)

magnitude dB magnitude dB

Loop gain T(s)

Vref

Vref

phase margin (deg)

V at load (V)

Load current (A)

Load current (A)

V at load (V)

Time-domain load transient

Time-domain load transient

phase margin (deg)

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Outline
DCDC converters compensation Effect of the load impedance Effect of the input lter impedance Case system study: CMS pixels phase 1 upgrade Conclusion

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Load effect on converters loop gain

The addition of a generic load impedance ZL to the nominal RL modies the Loop Gain: T(s) -> T(s)
Zout DCDC

Vsource

RLoad Vsource1

DC Source

ZL

DCDC

L=12 nH R=8 mOhm

T(s)=
C=21 uF R=5 mOhm

R=30 mOhm L=6 nH

T(s)
C=6 uF R11 R=2.5 Ohm R=5 mOhm

(1+T(s))Zo/ZL + 1

PWM

Compensator

Sensor

Vref

Zin L
DCDC L=12 nH R=8 mOhm C=21 uF R=30 mOhm L=6 nH C=6 uF R=5 mOhm R=5 mOhm

If Zo/ZL << 1 then T(s) = T(s) and the stability of the converter is NOT affected by the addition of the output impedance. This translates in the commonly used stability criterium: Zo << ZL
Vref

NB: if the criterium is not satised, T(s) is modied but the converter could still be stable
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Vref

Vsource

RLoad Vsource1 DCDC L=12 nH R=8 mOhm C=21 uF R=30 mOhm L=6 nH C=6 uF R11 R=2.5 Ohm R=5 mOhm

Output lter
PWM Compensator Sensor Vref

R=5 mOhm

The output lter (pi) required to reduce conducted noise represents a load impedance different than the nominal. Its input impedance has to be compared with the output impedance of the converter
DCDC L=12 nH R=8 mOhm C=21 uF R=30 mOhm L=6 nH C=6 uF R=5 mOhm R=5 mOhm Vref

Zout DCDC ZL

Example for 2 different output lters (real conguration with ESRs, not exactly the schematic shown to the right) Filter2 input impedance

Vsource

RLoad Vsource1 DCDC L=12 nH R=8 mOhm C=21 uF R=30 mOhm L=6 nH C=6 uF

DC Source

R11 R=2.5 Ohm R=5 mOhm

R=5 mOhm

Filter1 input impedance

PWM

Compensator

Sensor Vref

Vref

DCDC

L=12 nH R=8 mOhm

C=21 uF

Z (dB)

Zin L

R=30 mOhm L=6 nH

R=5 mOhm

Converters output impedance R=5 mOhm

C=6 uF

The magnitude of the impedance is expressed in dB: IIZIIdB = 20 log10 (IIZII/1)

Vref

Crossover frequency of the converters TF PWG @ACES11 F.Faccio - CERN/PH-ESE

Output lter
The addition of ZL modies the loop gain T(s) of the converter In one of the example cases, this happens above the crossover frequency. In the other, below the crossover frequency (and this can introduce instabilities, which does not happen in the shown test case)
Example voltage variation from a load transient for the 2 lters. The response is different Filter1 Filter2

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Test case 1: DCDC on FE module

A sketch of a possible conguration with a DCDC on the FE module is studied Remember that a pi lter is placed in our DCDC prototypes at both input and output of the converter to decrease conducted noise
detector
DCDC with pi lter

us of WP2 (On-detector power distribution) Zout DCDC

, S.Michelis, G.Blanchot, C.Fuentes, B.Allongue ase in manpower as from Jan 1st withLC (pi) lterS.Orlandi (fellow) line parasitics departure of PCB
C=21 uF C=6 uF R11 R=2.5 Ohm R=5 mOhm

d Vsource1 DCDC L=12 nH R=8 mOhm R=30 mOhm L=6 nH

R=5 mOhm

1A load

Zin L
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Decoupling caps

hybrid

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Test case 1: DCDC on FE module

A sketch of a possible conguration with a DCDC on the FE module is studied Remember that a pi lter is placed in our DCDC prototypes at both input and output of the converter to decrease conducted noise
detector
DCDC with pi lter

hybrid

Load input impedance (@ input of LC lter)

us of WP2 (On-detector power distribution) Zout DCDC

, S.Michelis, G.Blanchot, C.Fuentes, B.Allongue ase in manpower as from Jan 1st withLC (pi) lterS.Orlandi (fellow) line parasitics departure of PCB
C=21 uF C=6 uF R11 R=2.5 Ohm R=5 mOhm

Z (dB)

d Vsource1 DCDC L=12 nH R=8 mOhm R=30 mOhm L=6 nH

DCDC output impedance

R=5 mOhm

1A load fc

Zin L
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Decoupling caps

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Test case 1: DCDC on FE module

Example load transients (1->1.3A). Voltage and current measured across the load resistor
RLoad Vsource1 DCDC L=12 nH R=8 mOhm C=21 uF R=30 mOhm L=6 nH C=6 uF R11 R=2.5 Ohm R=5 mOhm R=5 mOhm

Compensator

2 transients Sensor
Vref

Orbit-gap-like transients (3us gaps with 90us period)

V at load (V)

20mV

20mV

Vref

1.3A
I at load (A)

1.3A
I at load (A)

1A
Vref

1A

V at load (V)

11mV

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Test case 2: CMS pixel upgrade phase 1

DCDCs are sitting about 2m away from the modules Precise characterization of line impedances not yet available, but best current estimates have been used (thanks to K.Klein and W.Karpinski) Example computation for worst-case load transient: 2 modules of Layer1 (current from 1 to 2.8A in 100ns)

LC lter
Vsource1 DCDC L=12 nH R=8 mOhm C=21 uF

Section A PCB lines Section B PCB lines

L=6 nH R=15 mOhm L=36 nH C=1.6 nF R=5 mOhm R=45 mOhm

Twisted pair
L=450 nH R=170 mOhm

Layer1 module

Layer1 module

C=1 nF

C=6 uF

R=6.6 Ohm

C=6 uF

R=6.6 Ohm

R=1 mOhm

R=15 mOhm

R=170 mOhm

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Test case 2: CMS pixel upgrade phase 1

Simulation results for AC (impedance comparison) and load transients
Vdd @ DCDC output
Vsource1 DCDC R=5 mOhm

Zout DCDC
L=12 nH R=8 mOhm C=21 uF L=6 nH R=15 mOhm L=36 nH C=1.6 nF R=45 mOhm L=450 nH C=1 nF R=170 mOhm C=6 uF

module
R=6.6 Ohm C=6 uF R=6.6 Ohm

Transients 1A -> 2.8A ->1A in 1ns

R=1 mOhm R=15 mOhm R=170 mOhm

Zin L
Vdd @ DCDC output Load input impedance (@ input of LC lter) Vdd @ module

Z (dB)

DCDC output impedance

gnd @ module

Vdd-gnd @ module

fc

Current @ module

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Outline
DCDC converters compensation Effect of the load impedance Effect of the input lter impedance Case system study: CMS pixels phase 1 upgrade Conclusion

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Input lter effect on converters Loop Gain

So far the input voltage was provided by an ideal source Anything making the source non-ideal (R,L,C) can be seen as an input lter As before, there is a condition involving the impedances of the lter and DCDC converter for the loop gain T(s) NOT to be modied by the lter
Zout lter

Vsource

RLoad

DC Source

Input lter

PWM

Compensator

Sensor

Zin DCDC

Vref

For the buck converter, this condition can approximately be expressed as

Vref

Zout lter << Zin DCDC

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Typical input lter

The input pi lter is part of it, with the addition of L and R of the cables from the PowerSupply (in our conguration, very long cables) An additional important complication is the presence of an equivalent negative impedance at the input of the converter
DCDC is a constant power load. Ideally Pin=Pout=P=vi => v=P/i Therefore at the input 2 L=450 nH Rin=dv/di=-P/i =-v/i R=45 mOhm R=170 mOhm
C=1 nF C=6 uF R=6.6 Ohm C=6 uF

DC Source
Vsource1 DCDC

Input lter
L=12 nH R=8 mOhm C=21 uF L=6 nH R=15 mOhm L=36 nH C=1.6 nF R=5 mOhm

R=6.6 Ohm

i
NegR

R=1 mOhm

R=15 mOhm

R=170 mOhm

C=21 uF

L=12 nH R=8 mOhm

C=21 uF

R=5 mOhm

R=5 mOhm

Vsource1

long cable PWG @ACES11

pi lter

DCDC

The LC of the lter might lack damping because of the negative resistance. The C=21 uF L=12 nH L=6 nH L=36 nH R=8 mOhm R=15 input node might oscillatemOhm C=1.6 nF
R=5 mOhm

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Example input lter 1

Vsource1 L=12 nH R=8 mOhm C=21 uF L=6 nH DCDC R=5 mOhm

R=15 mOhm

L=36 nH C=1.6 nF

R=45 mOhm

L=450 nH C=1 nF

R=170 mOhm C=6 uF R=6.6 Ohm C=6 uF R=6.6 Ohm

Cable with high L and very small R (very little damping)

Input lter
R=20 mOhm L=30 uH C=21 uF L=12 nH R=8 mOhm C=21 uF

R=1 mOhm

R=15 mOhm

R=170 mOhm

Zout lter DCDC Load

Power Supply

Vline

R=5 mOhm

R=5 mOhm

Zin DCDC
DCDC input impedance 2 load transients (1A -> 2.8A -> 1A)

Vline

Z (dB)

Vout DCDC Filter output impedance

Power Supply current

T(s) of the DCDC not modied, but large LC peak

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Example input lter 2

Vsource1 L=12 nH R=8 mOhm C=21 uF L=6 nH DCDC R=5 mOhm

R=15 mOhm

L=36 nH C=1.6 nF

R=45 mOhm

L=450 nH C=1 nF

R=170 mOhm C=6 uF R=6.6 Ohm C=6 uF R=6.6 Ohm

Cable with high L and large R (much closer to real life)

Input lter Power Supply
R=500mOhm
R=20 mOhm

R=1 mOhm

R=15 mOhm

R=170 mOhm

Zout lter

L=16uH

L=30 uH

C=21 uF

L=12 nH R=8 mOhm

C=21 uF

Vline

R=5 mOhm

R=5 mOhm

DCDC

Load

Zin DCDC
2 load transients (1A -> 2.8A -> 1A) DCDC input impedance

Vline

Z (dB)

Filter output impedance

Filter output impedance for 6x pi lter capacitors

Power Supply current

T(s) of the DCDC not modied

Zout lter << Zin DCDC
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Outline
DCDC converters compensation Effect of the load impedance Effect of the input lter impedance Case system study: CMS pixels phase 1 upgrade Conclusion

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Case study: CMS pixels upgrade phase 1

The full distribution scheme (with ideal PS) is studied, using the best available estimates As case study, and to have the maximum current transient, a specic (unreal) conguration is chosen: 1 PS channel powering 6 DCDCs belonging to Layer1 (2 modules powered by each DCDC)
Vsource1 L=12 nH R=8 mOhm C=21 uF L=6 nH R=15 mOhm L=36 nH R=45 mOhm L=450 nH R=170 mOhm DCDC C=1.6 nF C=1 nF C=6 uF R=6.6 Ohm C=6 uF R=6.6 Ohm R=5 mOhm R=1 mOhm R=15 mOhm R=170 mOhm R=20 mOhm L=30 uH C=21 uF L=12 nH R=8 mOhm C=21 uF NegR R=5 mOhm R=5 mOhm R=250 mOhm Vsource2 L=8 uH C=21 uF C=21 uF L=12 nH R=8 mOhm C=21 uF DCDC R=5 mOhm mOhm R=5 R=5 mOhm R=5 mOhm L=12 nH R=8 mOhm C=21 uF L=492 nH R=416 mOhm C=12 uF R=3.3 Ohm

Vline

Load transients for each DCDC 1A -> 2.8A -> 1A

C=21 uF C=21 uF

L=12 nH R=8 mOhm

C=21 uF DCDC

L=12 nH R=8 mOhm

C=21 uF

L=492 nH

R=416 mOhm C=12 uF R=3.3 Ohm

R=5 mOhm R=5 mOhm

R=5 mOhm

R=5 mOhm

6 DCDCs

C=21 uF C=21 uF

L=12 nH R=8 mOhm

C=21 uF DCDC

L=12 nH R=8 mOhm

C=21 uF

L=492 nH

R=416 mOhm C=12 uF R=3.3 Ohm

R=5 mOhm R=5 mOhm

R=5 mOhm

R=5 mOhm

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Two load transients

Each module pair instantaneously (NOT in 100ns as in reality) changes current from 1A to 2.8A, then back

Current in the pair of modules DCDC n2 output V before lter

Voltage at the module (DCDC n2) DCDC n1 output V before lter

Voltage at the module (DCDC n1)

Vline
DCDC n1 input voltage (after lter)

Power Supply current

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Orbit-gap simulation
Current in each module pair drops to 1A (from 2.8A) for 3us every 89us, then goes back to 2.8A

Current in the pair of modules DCDC n2 output V before lter Voltage at the module (DCDC n2) DCDC n1 output V before lter

Voltage at the module (DCDC n1)

Vline
DCDC n1 input voltage (after lter) Power Supply current

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Power-on & power-off of full PS channel

Voltage ramp from the PS (rise & fall time 2ms) to turn-on and -off all 6 converters loaded with an equivalent 1A current

DCDC n1 output V before lter

Voltage at the module (DCDC n1)

Vline
DCDC n1 input voltage (after lter)

Current in the pair of modules

Power Supply current

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Voltage ripple on the line

In this simulation, all 6 DCDCs switch at 2MHz in phase (practically this might never happen) The peak-peak voltage ripple induced on the line (Vline) is limited well below 1mV (effect of the input pi lter: before the lter it is 30mV) At the module, this is of the order of 1uV

Current in the pair of modules

1uV

30mV

DCDC n1 output V before lter

Voltage at the module (DCDC n1)

30mV 135uV

Vline

DCDC n1 input voltage (after lter)

Power Supply current

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Outline
DCDC converters compensation Effect of the load impedance Effect of the input lter impedance Case system study: CMS pixels phase 1 upgrade Conclusion

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Conclusion
The stability of detector systems embedding POL DCDC buck converters has been studied The addition of real impedances at the output and input of the converter might inuence the gain loop of the converter, with consequences on the converters stability Due to the negative impedance of the DCDC, the lumped input LC lter might be undamped and oscillations might be observed In the explored range of parameters for input and output impedances, based on available estimates, no sign of instability or oscillation has been found The developed simulation tools, based on the characteristics of the ASMI4 POL buck, can be used to study specic systems during the development phase and help nding and xing possible problems

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