Lecture 6: Design Flow

CSCE 5730 Digital CMOS VLSI Design

Instructor: Saraju P. Mohanty, Ph. D.
NOTE: The figures, text etc included in slides are borrowed from various books websites authors pages and other books, websites, pages, sources for academic purpose only. The instructor does not claim any originality. y g y
CSCE 5730: Digital CMOS VLSI Design

Lecture Outline
Hierarchical Design Logic Design Circuit Design Physical Design

CSCE 5730: Digital CMOS VLSI Design

Hierarchical Design: Design Partitioning

How to design modern System-on-Chip (SOC)?
Many millions (soon billions!) of transistors Tens to hundreds of engineers

Approaches for larger system design:

Structured Design: Uses principles of Hierarchy, Regularity, Modularity, and Locality Design Partitioning: Design is partitioned to five interrelated tasks, such as architecture design, microarchitecture design logic design circuit design design, design, and physical design.

CSCE 5730: Digital CMOS VLSI Design

Design Partitioning : Structured Design

Hierarchy: Divide and Conquer
Recursively system into modules

Regularity
Reuse modules wherever possible Ex: Standard cell library

Modularity: well-formed interfaces

Allows modules to be treated as black boxes

Locality
Physical and temporal

CSCE 5730: Digital CMOS VLSI Design

Hierarchical Design: Flow

mips controller standard cell library alu fulladder or2 and2 mux4 mux2 tri
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alucontrol

datapath bitslice zipper

inv4x flop ramslice

nor2 inv nand2

Design Partitioning : Y-Chart

Architecture: Users perspective, what does it do?
Instruction set registers set, MIPS, x86, Alpha, PIC, ARM,

Microarchitecture:
Single cycle, multicycle, pipelined, superscalar?

Logic: how are functional blocks constructed

Ripple carry, carry look-ahead, carry select adders

Circuit: how are transistors used

Complementary CMOS, pass transistors, domino

Physical: chip layout

Datapaths, memories, random logic
CSCE 5730: Digital CMOS VLSI Design

Design Partitioning : Y-Chart

Explains each domain and transformation among domains. Design process proceeds from higher to lower levels of abstractions i.e. from outer to inner rings.
CSCE 5730: Digital CMOS VLSI Design

Hardware Description Language (HDL)

Hardware Description Languages
Widely used in logic design Verilog Very High Speed Integrated Circuit HDL (VHDL) Very-High-Speed-Integrated-Circuit

Describe hardware using code

Document logic functions Simulate logic before building Synthesize code into gates and layout
Requires a library of standard cells

CSCE 5730: Digital CMOS VLSI Design

HDLs: Verilog Example

module fulladder (input a, b, c, output s, cout); ( , , , ); sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule module carry (input a, b, c, output cout) t t t) assign cout = (a&b) | (a&c) | (b&c); endmodule

a b c a cout s fulladder cout s b c carry sum

CSCE 5730: Digital CMOS VLSI Design

Circuit Design
How should logic be implemented?
NANDs and NORs vs ANDs and ORs? vs. Fan-in and fan-out? How wide should transistors be?

These choices affect speed, area, power Logic synthesis makes these choices for you
Good enough for many applications Hand-crafted circuits are still better

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Carry Logic Example: Logic Level

assign cout = (a&b) | (a&c) | (b&c);
g1 a b g2 a c g3 b c z
Transistors? Gate Delays?
CSCE 5730: Digital CMOS VLSI Design

x g4 y cout

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Carry Logic Example: Transistor Level

assign cout = (a&b) | (a&c) | (b&c);

p p1 c c

p p2 p3 i3

b a a b

p p4 i4 p5 n5 i2 n4

cn

p6 cout n6

n3 i1 n1 b n2

Transistors? Gate Delays?

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Carry Logic Example: Gate-level Netlist

module carry (input a, b, c, output cout)
g1

wire x, y, z; and g1(x a b); g1(x, a, and g2(y, a, c); and g3(z b, c); g3(z, b or g4(cout, x, y, z); endmodule

a b g g2 a c g3 b c

x g g4 y z cout

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Carry Logic Example: Transistor-Level Netlist

module carry ( p (input a, b, c, output cout) , , , p ) wire i1, i2, i3, i4, cn; tranif1 n1(i1, 0, a); tranif1 n2(i1 0 b); n2(i1, 0, tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn i2, a); n5(cn, i2 tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); t if0 3( i3 ) tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn); endmodule

1 2 4 a p1 b p2 b p4 i4 c p3 i3 a p5 cn c n3 i1 a n5 i2 a n1 b n2 b n4

p6 cout n6

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Carry Logic Example: SPICE Netlist

.SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P W 1U L 0.18U AD 0.3P AS 0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W 2U L 0 18U AD 0 6P AS 1 P W=2U L=0.18U AD=0.6P AS=1 MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0 18U AD=0 3P AS=1P W 2U L 0.18U AD 0.3P AS 1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF .ENDS
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Physical Design
Floorplan : First step. Determines if design will fit in are budget budget. Standard cells : Layout is often generated using automatic place and route. Slice planning : Divide to slices. Slice plan makes S ce p a g de s ces S ce p a a es it is easy to calculate wire length, estimate area, a d e a ua e and evaluate wire congestion. e co ges o

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Layout Design Rules

Interface between designer and process engineer G id li Guidelines f constructing process masks for t ti k Unit dimension: Minimum line width scalable d i rules: l bd parameter l bl design l lambda t absolute dimensions (micron rules)

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Layout Design Rules

Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon

Normalize for feature size when describing design rules Express rules in terms of = f/2
e.g. = 60 nm in 120 nm process
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Layout Design Rules : Simplified Form

Metal and diffusion have minimum width and spacing of 4. Contacts are 2 x 2 and surrounded by 1 layer. Polysilicon width is 2 2. Polysilicon overlaps diffusion by 2 or 1 depending on situation situation. Polysilicon and contacts have spacing 3. n well surrounds PMOS transistors by 6 and n-well NMOS transistors 6.
NOTE: Do not have to remember, CAD softwares handle it automatically once DRC are set depending on the foundry chosen.
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Layout Design Rules : Simplified Form

Conservative rules to get you started

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Logic Gate Layout : Inverter

V DD
1 1 2

2 3 4

G ND

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CMOS Process Layers

Layer L Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color C l Yellow Green Green Red Blue Magenta Black Black Black Representation R t ti

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Layers in 0.25 m CMOS process

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Intra-Layer Design Rules

Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2
Metal2 3
CSCE 5730: Digital CMOS VLSI Design

Different Potential 9 Polysilicon 2 Metal1 M l1 2 3

4

Well

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Transistor Layout y
Tr Transistor

Polysilicon Well (n or p) Active Area (n+ or p+)

5

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Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact A i C Metal to Poly Contact 3 2 4

2 2

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Select Layer y
2 3 2 1 3 3 Select

Substrate

Well

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CMOS Inverter Layout

GND In VD D

Out (a) Layout

A p-substrate n+ (b) Cross-Section along A A Cross Section A-A

CSCE 5730: Digital CMOS VLSI Design

A n p+ Field Oxide

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Layout Editor

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Design Rule Checker

p y_ poly not_fet to all_diff minimum spacing = 0.14 um. p g

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Sticks Diagram
V DD In

3 Out
Dimensionless layout entities Only topology is important Final layout generated by compaction p og a co pact o program

1
GND
Stick diagram of inverter g

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Logic Gate Layout

Layout can be very time consuming
Design gates to fit together nicely Build a library of standard cells

St d d cell d i methodology Standard ll design th d l

VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

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MIPS: Block Diagram

PCWriteCond PCEn PCSource MemRead MemWrite MemtoReg IRWrite[3:0] Op [5 : 0] PCWrite Outputs ALUOp IorD ALUSrcB Control ALUSrcA RegWrite RegDst 0 M x 2

Instruction [5 : 0] Instruction [31:26] Address Add Memory MemData Write data Instruction [25 : 21] Instruction [20 : 16] Instruction [15 : 0] Instruction register Instruction [7 : 0] Memory data register 0 M Instruction u x [15 : 11] 1 0 M u x 1 Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 Write data A 0 M u x 1 0 1 M u 2 x 3

Shift left 2

Jump address

1 u

PC

0 M u x 1

B 1

Zero ALU ALU result

ALUOut

memwrite memread

ALU control ALUControl

Instruction [5 : 0]

controller

aluop[1:0]

alucontrol
fu unct[5:0]
alucontrol[2:0]

op[5:0]

zero

alusrca

alusrcb[1:0]

pcen

pcsource[1:0]

memtoreg m

re egdst

io ord

egwrite re

ir rwrite[3:0]

ph1 ph2 reset adr[7:0] writedata[7:0] memdata[7:0]

datapath

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MIPS: Floorplan
10 I/O pads

mips (4.6 M2) control t l 1500 x 400 (0.6 M2)

wiring channel: 30 tracks = 240 3500 0 1690 0 zipper 2700 x 250 datapath 2700 x 1050 (2.8 M2)

alucontrol 200 x 100 (20 k2) 10 I/O pads

10 I/O pads

5000 0

bitslice 2700 x 100 2700

3500

10 I/O pads

5000 000

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MIPS : Layout

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Area Estimation
Need area estimates to make floorplan
Compare t another bl k you already d i C to th block l d designed d Or estimate from transistor counts Budget room f l B d for large wiring tracks ii k Your mileage may vary!

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Design Verification
Fabrication is slow & expensive
MOSIS 0 6m: $1000 3 months 0.6m: $1000, State of art: $1M, 1 month
Specification = Architecture Design = Logic g Design = Circuit Design = Physical Design Function Timing Power Function Function Function

Debugging chips is very hard

Limited visibility into operation

Prove the design before building!

Logic simulation Ckt. simulation / formal verification Layout vs. schematic comparison Design & electrical rule checks g

Verification is > 50% of effort on most chips!

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