Professional Documents
Culture Documents
Course Objective
To introduce fundamentals of Computer Architecture To introduce the concepts of System Software. To introduce the concepts of Operating Systems. To introduce the concepts of Computer Networks.
References
Andrew S. Tanenbaum: Structured Computer Organization , PHI, 3rd edition, 1991. Silberschatz and Galvin: Operating System Concepts , 4th edition, Addison-Wesley Pub, 1995. Andrew S. Tanenbaum: Computer Networks, PHI, 1991. Alfred V.Aho, Ravi Sethi, Jeffrey D.Ullman: Compilers Principles, Techniques and Tools, Narosa Publishing House, 1986.
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Session Plan
Day 1 Create a background Main components of computer architecture Different addressing modes Day 2 Introduce System Software Introduce Operating Systems/Memory Management
Session Plan
Day 3 Introduce Process Management Introduce File Management Day 4 Introduce Device Management Introduce Computer Networks
Background
What is a Computer? Is an electronic device used to Store Retrieve and, Process data. To process data a set of instructions need to be given to the computer. What is a Program? Is a set of instructions.
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Computer Architecture
Is concerned with the structure and behavior of the computer as seen by the user/programmer. It includes attributes such as Instruction Formats Addressing Modes Instruction Sets I/O Mechanisms
Computer Architecture
Main components in a computer system Hardware Software Firmware
Central Processing Unit (CPU) Main Memory Input / Output devices Bus
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CPU (Processor)
What is it? Brain of the computer Function Fetch instructions from memory Examine Execute Consists of 3 functional units Control Unit (CU) ALU Registers
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CPU Functional Units Fetches Instructions from memory CPU Interprets the instructions Performs arithmetic operations
Control Unit
ALU
Examples
Registers
Program Counter (PC) Instruction Register (IR) Memory Address Register (MAR) Memory Buffer Register (MBR) Accumulator (A)
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Memory
MEMORY
Internal Memory
Main Memory
Cache Memory
Secondary Memory
RAM
ROM
Internal Cache
External Cache
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In the form of Registers Registers are small memory units internally available within the CPU. Volatile/Non volatile Memory
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Main Memory
y nl O d or y ea m R e M
Ra
do n
s ce c y
Me
or m
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CPU
Cache
Main Memory
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Floppy disk
Yes
Yes
1.44 MB
CD ROM
Yes
No
650700MB
CD Read/ Write
Yes
Yes
650-700 MB
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Primary Memory
Secondary Memory
40GB 80 GB
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Memory hierarchy
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Bus
Parallel wires that carry several bits at a time Carries instructions, data, addresses or commands Unidirectional or bi-directional Major Categories
Data bus Address bus Control bus
Bus width and Bus speed are the two major components for performance measure.
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Harvard Architecture
The Advantages of this architecture is the clear separation of the data region and the code region. Also the separate data and program busses are used, hence speeding up the process. Disadvantages could be the separate mechanisms to fetch data and the programs.
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The Advantages of this architecture is that it treats data and programs alike meaning the same mechanisms to fetch data and the programs. The disadvantage is the same bus used for both program as well the data leads to so called Von Neumann bottleneck.
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Fetch-decode-execute cycle
ADD R1,R2 CPU Control Unit 1A . . . . . . . . Memory
Instruction Decoder
Special Registers
5000
ALU
R1 GPR R3
R2 R4
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Fetch-decode-execute cycle
Fetch Phase Decode Phase Execute Phase
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Fetch phase
Contents of PC are transferred to MAR Main memory is accessed and current instruction is fetched into MBR Instruction is transferred from MBR to IR
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Decode phase
Opcode of the instruction is decoded Contents of PC are incremented by 1(in case of 1 byte instruction or equal to the no. of bytes of the instruction currently being executed.) Execution phase follows ( specific to the given instruction )
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Execute phase
Execute the instruction Store the results in the proper place (go to the fetch phase to begin executing the next instruction)
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Fetch-decode-execute cycle-Example 2
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Instruction categories
Arithmetic Instructions
Ex.: Add, Sub, Mul etc.
Logical instructions
Instructions doing comparison operations.
I/O instructions
Ex.: In, Out
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Central Processing Unit (CPU) Control Unit Arithmetic Logic Unit (ALU)
em
or
yt
R1 R3 MAR IR
R2 R4 MBR PC
Me m
M em
or y
REGISTERS
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I/O devices
Why needed? O/P Devices:
Monitor
Printer
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I/O devices
Input Devices:-
Mouse
Keyboard
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I/O devices
Input/Output Devices
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Addressing
A way of accessing memory locations which contain the data for processing Modes of addressing Implied Addressing Immediate Addressing Direct or Absolute Addressing Relative Addressing Indirect addressing
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Implied Addressing
Operands are specified implicitly in the definition of the instruction Instruction specifies a fixed and unvarying address Example:- DEC
(Decrement A register)
1. The CU decodes the instruction (fetch and decode phase) 2. The CU then fetches the contents of the register A 3. The value of the A will be transferred to the ALU 4. The ALU then decrements this value and updates the register A
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Immediate addressing
In it, data is a part of instruction itself. Example:- MOVE #100H, R1 Here the data 100h is moved to R1. The following steps are involved in the execution of this instruction. The CU decodes the instruction (fetch and decode phase) The data 100H available with the instruction is sent to Register R1. R1
Control Unit 2 1
MOVE
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#100H
R1
Control Unit
R1
3 30A4
75
MOVE
30A4H
R1
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Indirect Addressing
Problem of direct addressing :the change in the location of the program is associated with the change in all absolute memory references. Solution : is to represent the address of the data indirectly. There are two ways to do it: 1) Register Indirect Addressing : the address of the data is stored in a Register. 2) Memory Indirect Addressing : the address of the data is stored in another memory location
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Control Unit
R2
3
30A4 75
1 4
MOVE [R2] R1 R1
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48
4 +
ADDER (ALU)
3
3000
Base Register (BX)
3
3000
20A4
20A4 Index Register Ri
1
MOVE [BX]
50A4
75
[Ri]
R1
75 R1
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50
51
3
50000
Segment Register (SR)
4 3
1000
Base Register (BX)
+
ADDER (ALU)
3
100
Index Register Ri 1000 51000 100 51100
Segment2 (Data)
75
Segment3
0
MOVE [SR] [BX] [Ri] R1
75 R1
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Summary
Background Components of a computer system Von Neumann architecture Fetch Decode Execute Cycle Memory I/O devices Bus Addressing Modes
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Thank You!
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