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Agenda
Introduction Handling Module Compiler (MC) gates Handling Pipeline Re-timed gates Case study MC Generated and Pipeline Re-Timed Gates Multipliers Case study Multiplier Abort Case study Multiplier Non-equivalence Modeling Automatic port conversion Multiple driven net Disabled clock ports Black box Best Practices Conclusion
Introduction
System on Chips (SoCs) are becoming more complex to build; ASIC design methodologies are becoming more and more rigorous to build them. Golden RTL is taken through implementation flow synthesis, power optimization, Design For Test (DFT), Placement and Route (P&R),Engineering Change Orders (ECO). Add to these, design circuitry implemented using compilers.
Introduction
Logical equivalency checking between the golden RTL and final silicon-ready circuit is a challenging task. Challenges faced in the logical equivalency checking process and how to make things work with Encounter Conformal LEC. The examples and case studies explained are taken from Conexants SoC projects.
Solution:
-----------------------------------------------------------------------//add module attribute module_name -pipeline_retime -DFF2Buffer -revised //add pin constraints 1 pipeline_enable_input -both ------------------------------------------------------------------------
Multipliers
Steps taken for generic multiplier comparison:
Study of the multiplier circuit. Identify the number of inputs, the type of algorithm implemented and the type of multiplication signed or unsigned. Initial formal run is done with compare effort low. Design similarity is studied. Resource sharing, if any done is taken into consideration. If needed, use the key-point partitioning feature of LEC. Use Divide and Conquer approach.
Multiplier Abort
Problem: A multiplier with an 8-bit input and 9-bit input and 17-bit output. DesignWare (DW) multiplier component is instantiated for multiplier operation. Formal run took long runtime and ended identifying 17 flops as abort points. Comparison made simpler, one flop (Least Significant Bit) out of the 17 flops is chosen for comparison. Trial runs were done with compare effort low, medium and high. All resulted in abort points.
Conexant Systems, Inc.
Multiplier Abort
Solution: The key-point partitioning feature is tried along with the maximum compare effort option available with LEC as shown below:
--------------------------------------------------------------------------//add pin constraints 0 TC -golden //set compare option -partition flow //set compare effort super ---------------------------------------------------------------------------
Limitation: Equivalency checking of the above multiplier took 15days on a linux64 machine.
Multiplier Non-equivalence
A signed multiplication circuit is implemented in RTL without any DW component instantiation. Sign extension of the operand variables is done using signed function supported in verilog 2001.
Multiplier Non-equivalence
Formal run detects non-equivalent points. Diagnosis schematics show hundreds of corresponding and non-corresponding support points. Debugging can be very difficult with diagnosis schematics, in this kind of scenario.
Multiplier Non-equivalence
Solution:
Use Source Debug and Annotation feature. See the RTL source code and the gate level netlist with test pattern values annotated. Debugging is easier. By default the Source debugging feature is turned off.
-----------------------------------------------------------------set hdl diagnosis ON -------------------------------------------------------------------
Multiplier Non-equivalence
During diagnosis, Source Debug is available in Diagnosis Manager window
Multiplier Non-equivalence
Solution: Particular version of synthesis tool doesnt support signed construct. Issue fixed when the version of the synthesis tool is changed.
(or)
Turn on the port conversion feature here. When automatic port conversion is allowed, LEC modeled SignalA as inout port and formal run passes.
Track the disabled clock port and identify the reason for clock not reaching these flops. User can use the following command to report all the flops not considered for comparison:
----------------------------------------------------------report message compare -verbose -----------------------------------------------------------
Best Practices
In most cases, Built In Self Test (BIST) mode can also be compared as a part of normal functional circuit.
Conexant Systems, Inc.
Best Practices
Scan Mode signal need not be constrained unless there is a specific requirement. Report all the modeling messages Report not compared points. Avoid using add no-translate module and use dummy wrapper modules for black boxes.
Conclusion
Complexity of the SoCs is ever-increasing. Requires more complicated analysis and debugging. Matured tools providing these features are very less in the current market. Covered some of the critical equivalency checking exercises demanded by our SoCs designs and how LEC is used to solve all these challenges. With new technological advances in the silicon compilers, compiler generated gates are going to be the next big challenge in formal verification. Design and verification community expects the formal verification tools to stay focused and fine tune to support various upcoming features in synthesis process.
Conexant Systems, Inc.
Reference
1. 2. EncounterTM Conformal Equivalence Checking Reference Guide, Product version 5.0, November 2004. EncounterTM Conformal Equivalence Checking User Guide, Product version 5.0, November 2004.
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EncounterTM is the trademark of Cadence Design Systems, Inc. Module CompilerTM is the trademark of Synopsys,Inc. DesignWareTM is the trademark of Synopsys, Inc.