CERTIFICATE It is to certify that the project entitled AVR MICROCONTROLLER using Xilinx system generator, is a bonafide work carried

out by in partial fulfillment for award of degree of Bachelor of Engineering in Electronics and Communication Engineering, College of Engineering & Technology (Affiliated to JNTU, Hyderabad), during the period of their final year, II semester and this work has not been submitted elsewhere for the award of any other degree.

Acknowledgement
We would like to thank our beloved parents for their endless kind support both mentally, financially and for encouraging us, without which we would not be what we are today. At the outset we sincerely thank Mr. Director, for his kind cooperation and Encouragement for the successful completion of project work and providing the necessary facilities.

We are most obliged and grateful to our Principal, H.O.D ECE Dept, and internal guide, Associate Professor, ECE Dept, for giving us guidance in completing this project successfully.

We are grateful to, Project Guide, Hyderabad, for their sagacious guidance, scholarly advice and the inspiration offered in an amiable and pleasant manner in helping us completing this project successfully. Last but no the least, we are thankful to our friends and well wishers.

ABSTRACT:

Many electronic applications appear in our daily life environment. These electrical applications are composed of microcontroller (C) among other components. The C is the kernel of an electronic device. The selection of C is often a trade-off between performance, embedded memory size, cost, and stability. Through FPGA design methodology, electronic device's functional behaviours are quickly verified. Nowadays, many electronic prototypes or even the final products are partial or even fully FPGA/CPLD-based. Thus, the power consumption problem of such electronic devices can not be neglected. The FPGA used in this project is Vertex A3P250. The target C behaviour to be compared is AVR C. The goal of this project is to design a FPGA-based C compatible with AVR C and clock gating is applied to this C to reduce the power consumption. In this project power is measured using VCD file and is compared with the C with clock gating and a simple C(without clock gating).This project is organized as follows: section 2 is the basic FPGA-based IlC and PCB design, section 3 describes the design and validation flow, section 4 is the measurement results, and followed by conclusions.

TABLE OF CONTENTS

CHAPTER

TITLE ACKNOWLEDGEMENT ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS LIST OF APPENDICES

PAGE

CHAPTER 1

INTRODUCTION

1.1 1.2 1.3

Overview and Problem Statement Objectives Scope of Work

1.5

Thesis Outline

CHAPTER 2

BACKGROUND AND THEOR

CHAPTER 3 3.1 3.2 3.3 3.4

METHODOLOGY AND DESIGN TOOLS

Project Design and Implementation Flow Verilog HDL Xilinx ISE 12.1 FPGA Synthesis

CHAPTER 4

DESIGN AND IMPLEMENTATION ON FPGA WITH MATLAB USING XILINX SYSTEM GENERATOR BLOCK SET AND XILINX ISE DESIGN TOOLS

CHAPTER 6 CHAPTER 7

SIMULATION, VERIFICATION AND RESULTS ANALYSIS CONCLUSION AND FUTURE WORK

LIST OF REFERENCES

AVR Micro Controller

The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use onchip flash memory for program storage, as opposed to One-Time Programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.

The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan. The original AVR MCU was developed at a local ASIC house in Trondheim, Norway called Nordic VLSI at the time, now Nordic Semiconductor, where the two founders of Atmel Norway were working as students. It was known as a RISC (Micro RISC) and was available as silicon IP/building block from Nordic VLSI. When the technology was sold to Atmel from Nordic VLSI, the internal architecture was further developed by Alf and Vegard at Atmel Norway, a subsidiary of Atmel founded by the two architects. The designers worked closely with compiler writers at IAR Systems to ensure that the instruction set provided for more efficient compilation of high-level languages. Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to what the term "AVR" stands for.

Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers. Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pin out as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the RESET line was opposite (8051's having an active-high RESET, while the AVR has an active-low RESET), but other than that, the pin out was identical. - The AVR is a modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.

Thesis Outline

This thesis concentrates on the theory and design of AVR CONTROLLER architecture. This thesis is organized into 6 chapters.

Chapter 1 is an overview of the project, objectives, project scope, and thesis outline. Chapter 2 discusses the project background, literature survey and theory which includes

Chapter 3 elaborates the project methodology and the EDA (Electronic Design Automation) design tools. It discusses the project design and implementation flow and EDA tools used in working out this project.

Chapter 4 is the gives an overview design. This chapter includes the architecture of the AVR MICROCONTROLLER

Chapter 5 elaborates the simulation, results and analysis.

Finally, Chapter 6 concludes this project with conclusion, project limitations, recommendations and suggested future

Basic families AVRs are generally classified into five broad groups:

tinyAVR the ATtiny series

o o o

0.58 kB program memory 632-pin package Limited peripheral set

megaAVR the ATmega series

o o o

4256 kB program memory 28100-pin package Extended instruction set (Multiply instructions and instructions for handling larger program memories)

Extensive peripheral set

XMEGA the ATxmega series

o o o

16384 kB program memory 4464100-pin package (A4, A3, A1) Extended performance features, such as DMA, "Event System", and cryptography support.

Extensive peripheral set with DACs

Application specific AVR

o

megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.

FPSLIC (AVR with FPGA)

Features of ATMEGA16: o o High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture o 131 Powerful Instructions Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

16K Bytes of In-System Self-programmable Flash program memory 512 Bytes EEPROM 1K Byte Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85C/100 years at 25C(1) Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

Real Time Counter with Separate Oscillator Four PWM Channels 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator

Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby

I/O and Packages 32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

Operating Voltages 2.7 - 5.5V for ATmega16L 4.5 - 5.5V for ATmega16

Speed Grades

0 - 8 MHz for ATmega16L 0 - 16 MHz for ATmega16

Power Consumption @ 1 MHz, 3V, and 25C for ATmega16L Active: 1.1 mA Idle Mode: 0.35 mA Power-down Mode: < 1 a

Pin Configurations:

Overview:
The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram:

The AVR core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary scan,

On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmels high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Pin Descriptions: VCC: Digital supply voltage.
GND: Ground.

Port A (PA7.PA0): Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled

low, they will source current if the internal pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running. Port B (PB7.PB0): Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source Capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up Resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on Port C (PC7.PC0): Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Port C also serves the functions of the JTAG interface and other special features of the ATmega16 as listed on

Port D (PD7.PD0): Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16 as listed on RESET: Reset Input. Low levels on this pin for longer than the minimum pulse length will generatereset, even if the clock is not running. The minimum pulse length is given in Shorter pulses are not guaranteed to generate a reset. XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2: Output from the inverting Oscillator amplifier.

AVCC: AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to V CC through a low-pass filter.AREF AREF is the analog reference pin for the A/D Converter. AVR CPU Core Introduction: This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview:

In order to maximize performance and parallelism, the AVR uses a Harvard architecture with +separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File in one clock cycle. Six of the 32 registers can be used as three 16-bit

indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section. The ALU supports arithmetic and logic operations

between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction. ALU Arithmetic Logic Unit: The high-performance AVR ALU operates in direct connection with all the 32 general purpose Working registers. Within a single clock cycle, arithmetic operations between general purpose Registers or between a register and an immediate are executed. The ALU operations are divided into three main categories arithmetic, logical, and bit-functions. Some implementations of the Architecture also provide a powerful multiplier supporting both signed/unsigned multiplication And fractional format. See the Instruction Set section for a detailed description

Status Register: The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register SREG is defined as:

Bit 7 I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

ATmega16 Bit 6 T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the Instruction Set Description for detailed information. Bit 4 S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Twos Complement Overflow Flag V. See the Instruction Set Description for detailed information. Bit 3 V: Twos Complement Overflow Flag The Twos Complement Overflow Flag V supports twos complement arithmetics. See the Instruction Set Description for detailed information. Bit 2 N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 1 Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 0 C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. General Purpose Register File:

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input

POWER SUPPLY

There are many types of power supply. Most are designed to convert high voltage AC mains electricity to a suitable low voltage supply for electronic circuits and other devices. A power supply can be broken down into a series of blocks, each of which performs a particular function. For example a 5V regulated supply:

Each of the blocks is described in more detail below: Transformer - steps down high voltage AC mains to low voltage AC. Rectifier - converts AC to DC, but the DC output is varying. Smoothing - smoothes the DC from varying greatly to a small ripple. Regulator - eliminates ripple by setting DC output to a fixed voltage.

Power supplies made from these blocks are described below with a circuit diagram and a graph of their output: Transformer only Transformer + Rectifier Transformer + Rectifier + Smoothing Transformer + Rectifier + Smoothing + Regulator

Transformer only

The low voltage AC output is suitable for lamps, heaters and special AC motors. It is not suitable for electronic circuits unless they include a rectifier and a smoothing capacitor. Transformer + Rectifier

The varying DC output is suitable for lamps, heaters and standard motors. It is not suitable for electronic circuits unless they include a smoothing capacitor. Transformer + Rectifier + Smoothing

The smooth DC output has a small ripple. It is suitable for most electronic circuits. Transformer + Rectifier + Smoothing + Regulator

The regulated DC output is very smooth with no ripple. It is suitable for all electronic circuits.

Light Emitting Diodes

Light Emitting Diodes or LEDs, are among the most widely used of all the types of diodes available. They are the most visible type of diode that emits a fairly narrow bandwidth of either visible coloured light, invisible infra-red or laser type light when a forward current is passed through them. A "Light Emitting Diode" or LED as it is more commonly called, is basically just a specialized type of PN-junction diode, made from a

very thin layer of fairly heavily doped semiconductor material. When the diode is Forward Biased, electrons from the semiconductors conduction band combine with holes from the valence band, releasing sufficient energy to produce photons of light. Because of this thin layer a reasonable number of these photons can leave the junction and radiate away producing a coloured light output. Unlike normal diodes which are made for detection or power rectification, and which are generally made from either Germanium or Silicon semiconductor material, Light Emitting Diodes are made from compound type semiconductor materials such as Gallium Arsenide (GaAs), Gallium Phosphide (GaP), Gallium Arsenide Phosphide (GaAsP), Silicon Carbide (SiC) or Gallium Indium Nitride (GaInN). The exact choice of the semiconductor material used will determine the overall wavelength of the photon light emissions and therefore the resulting colour of the light emitted, as in the case of the visible light coloured LEDs, (RED, AMBER, GREEN etc). Typical LED Characteristics Semiconductor Material GaAs GaAsP GaAsP GaAsP:N GaP 550-570nm Green 3.5v

Wavelength

Colour

VF @ 20mA

850-940nm 630-660nm 605-620nm 585-595nm

Infra-Red Red Amber Yellow

1.2v 1.8v 2.0v 2.2v

SiC GaInN

430-505nm 450nm

Blue White

3.6v 4.0v

From the table above we can see that the main P-type dopant used in the manufacture of Light Emitting Diodes is Gallium (Ga, atomic number 31) and the main Ntype dopant used is Arsenic (As, atomic number 31) giving the resulting Gallium Arsenide

(GaAs) crystal structure, which has the characteristics of radiating significant amounts of infrared radiation from its junction when a forward current is flowing through it. By also adding Phosphorus (P, atomic number 15), as a third dopant the overall wavelength of the emitted radiation is reduced to give visible red light to the human eye. Further refinements in the doping process of the PN-junction have resulted in a range of colours available from red, orange and amber through to yellow, and the recently developed blue LED which is achieved by injecting nitrogen atoms into the crystal structure during the doping process. Light Emitting Diodes I-V Characteristics: Before a light emitting diode can "emit" any form of light it needs a current to flow through it, as it is a current dependant device. As the LED is to be connected in a forward bias condition across a power supply it should be Current Limited using a series resistor to protect it from excessive current flow. From the table above we can see that each LED has its own forward voltage drop across the PN-junction and this parameter which is determined by the semiconductor material used is the forward voltage drop for a given amount of forward conduction current, typically for a forward current of 20mA. In most cases LEDs are operated from a low voltage DC supply, with a series resistor to limit the forward current to a suitable value from say 5mA for a simple LED indicator to 30mA or more where a high brightness light output is needed.

LED Series Resistance:

The series resistor value RS is calculated by simply using Ohms Law, knowing the required forward current IF, the supply voltage VS and the expected forward voltage drop of the LED, VF at this current level as shown below:

LED Typical Applications: The following figure shows how to interface the LED to microcontroller. As you can see the Anode is connected through a resistor to Vcc and the Cathode is connected to the Microcontroller pin. So when the Port Pin is HIGH the LED is OFF and when the Port Pin is LOW the LED is turned ON.

Transformer

Definition: The transformer is a static electro-magnetic device that transforms one alternating voltage (current) into another voltage (current). However, power remains the some during the transformation. Transformers play a major role in the transmission and distribution of ac power. Principle: Transformer works on the principle of mutual induction. A transformer consists of laminated magnetic core forming the magnetic frame. Primary and secondary coils are wound upon the two cores of the magnetic frame, linked by the common magnetic flux. When an alternating voltage is applied across the primary coil, a current flows in the primary coil producing magnetic flux in the transformer core. This flux induces voltage in secondary coil.

Transformers are classified as: (a) Based on position of the windings with respect to core i.e. (1) (2) (b) Core type transformer Shell type transformer

Transformation ratio: (1) (2) Step up transformer Step down transformer

(a)

Core & shell types: Transformer is simplest electrical machine, which consists of windings on the laminated magnetic core. There are two possibilities of putting up the windings on the core.

(1) (2) (b)

Winding encircle the core in the case of core type transformer Cores encircle the windings on shell type transformer. Step up and Step down: In these Voltage transformation takes place according to whether the Primary is high voltage coil or a low voltage coil.

(1) (2)

Lower to higher-> Step up Higher to lower-> Step down

Bridge rectifiers

There are several ways of connecting diodes to make a rectifier to convert AC to DC. The bridge rectifier is one of them and it is available in special packages containing the four diodes required. Bridge rectifiers are rated by their maximum current and maximum reverse voltage. They have four leads or terminals: the two DC outputs are labelled + and -, the two AC inputs are labelled (3) .

The diagram shows the operation of a bridge rectifier as it converts AC to DC. Notice how alternate pairs of diodes conduct.

Various types of Bridge Rectifiers Note that some have a hole through their centre for attaching to a heat sink

GSM

The short message system (SMS) of a standard mobile phone can be used for much more than just exchanging cryptic message. This application finds a humble mobile working for controlling external equipments. The SMS service provides by the service providers are comparatively low cost. Hence the system is highly efficient and low-cost. Mobile phones have become a widespread means of communication. It becomes a part of everyday life with ever more people enjoying the service and extra freedom they provide. It works on the basis of Global System for Mobile Communication (GSM). A subscriber from any systems can access telecommunication services by using a Subscriber Identify Module (SIM) card in a handset suitable for the network on the visited system The Short Message Service allows text messages to be sent and received to and from mobile telephones. The text can comprise words or numbers or an alphanumeric combination. Because Simple person - to - person messaging is such an important component of total SMS traffic volumes, anything that simplifies message generation as well as extended utility of the SMS being sent is an important enabler of Short Message Service.

The main aim of this project is to control the car engine. We will connect Hardware kit to car engine. The hardware kit consists of microcontroller and GSM modem

A GSM modem is a specialized type of modem which accepts a SIM card, and operates over a subscription to a mobile operator, just like a mobile phone. From the mobile operator perspective, a GSM modem looks just like a mobile phone. When a GSM modem is connected to a computer, this allows the computer to use the GSM modem to communicate over the mobile network. While these GSM modems are most frequently used to provide mobile internet connectivity, many of them can also be used for sending and receiving SMS and MMS messages.

Now SMS Light can send and receive SMS and MMS Messages using a GSM modem:

A GSM modem can be a dedicated modem device with a serial, USB or Bluetooth connection, or it can be a mobile phone that provides GSM modem capabilities. For the purpose of this document, the term GSM modem is used as a generic term to refer to any modem that supports one or more of the protocols in the GSM evolutionary family, including the 2.5G technologies GPRS and EDGE, as well as the 3G technologies WCDMA, UMTS, HSDPA and HSUPA. A GSM modem exposes an interface that allows applications such as Now SMS to send and receive messages over the modem interface. The mobile operator charges for this message sending and receiving as if it was performed directly on a mobile

phone. To perform these tasks, a GSM modem must support an extended AT command set for sending/receiving SMS messages, as defined in the ETSI GSM 07.05 and 3GPP TS 27.005 specifications. GSM modems can be a quick and efficient way to get started with SMS, because a special subscription to an SMS service provider is not required. In most parts of the world, GSM modems are a cost effective solution for receiving SMS messages, because the sender is paying for the message delivery. A GSM modem can be a dedicated modem device with a serial, USB or Bluetooth connection, such as the Falcon Samba 75. (Other manufacturers of dedicated GSM modem devices include Wavecom, Multitech and iTegno. Weve also reviewed a number of modems on our technical support blog.) To begin, insert a GSM SIM card into the modem and connect it to an available USB port on your computer. A GSM modem could also be a standard GSM mobile phone with the appropriate cable and software driver to connect to a serial port or USB port on your computer. Any phone that supports the extended AT command set for sending/receiving SMS messages, as defined in ETSI GSM 07.05 and/or 3GPP TS 27.005, can be supported by the Now SMS & MMS Gateway. Note that not all mobile phones support this modem interface. Due to some compatibility issues that can exist with mobile phones, using a dedicated GSM modem is usually preferable to a GSM mobile phone. This is more of an issue with MMS messaging, where if you wish to be able to receive inbound MMS messages with the gateway, the modem interface on most GSM phones will only allow you to send MMS messages. This is because the mobile phone automatically processes received MMS message notifications without forwarding them via the modem interface. It should also be noted that not all phones support the modem interface for sending and receiving SMS messages. In particular, most smart phones, including Blackberries, iPhone, and Windows Mobile devices, do not support this GSM modem interface for sending and receiving SMS messages at all at all. Additionally, Nokia phones that use the S60 (Series 60) interface, which is Symbian based, only support sending SMS messages via the modem interface, and do not support receiving SMS via the modem interface.

The Future of GSM:

GSM together with other technologies is part of an evolution of wireless mobile telecommunication that includes High-Speed Circuit-Switched Data (HSCSD), General Packet Radio System (GPRS), Enhanced Data rate for GSM Evolution (EDGE), and Universal Mobile Telecommunications Service (UMTS). GSM Network Operators:

T-Mobile and Cingular operate GSM networks in the United States on the 1,900 MHz band. GSM networks in other countries operate at 900, 1,800, or 1,900 MHz .

GSM (Global System for Mobile Communications: Originally from Group Special Mobile) is the most popular standard for mobile telephony systems in the world. The GSM Association, its promoting industry trade organization of mobile phone carriers and manufacturers, estimates that 80% of the global mobile market uses the standard.[1] GSM is used by over 1.5 billion people[2] across more than 212 countries and territories.[3] This ubiquity means that subscribers can use their phones throughout the world, enabled by international roaming arrangements between mobile network operators. GSM differs from its predecessor technologies in that both signaling and speech channels are digital, and thus GSM is considered a second generation (2G) mobile phone system. This also facilitates the widespread implementation of data communication applications into the system. The GSM standard has been an advantage to both consumers, who may benefit from the ability to roam and switch carriers without replacing phones, and also to network operators, who can choose equipment from many GSM equipment vendors.[4] GSM also pioneered

low-cost implementation of the short message service (SMS), also called text messaging, which has since been supported on other mobile phone standards as well. The standard includes a worldwide emergency telephone number feature (112).[5] Newer versions of the standard were backward-compatible with the original GSM system. For example, Release '97 of the standard added packet data capabilities by means of General Packet Radio Service (GPRS). Release '99 introduced higher speed data transmission using Enhanced Data Rates for GSM Evolution (EDGE).

GSM carrier frequencies: GSM networks operate in a number of different carrier frequency ranges (separated into GSM frequency ranges for 2G and UMTS frequency bands for 3G), with most 2G GSM networks operating in the 900 MHz or 1800 MHz bands. Where these bands were already allocated, the 850 MHz and 1900 MHz bands were used instead (for example in Canada and the United States). In rare cases the 400 and 450 MHz frequency bands are assigned in some countries because they were previously used for first-generation systems. Most 3G networks in Europe operate in the 2100 MHz frequency band. Regardless of the frequency selected by an operator, it is divided into timeslots for individual phones to use. This allows eight full-rate or sixteen half-rate speech channels per radio frequency. These eight radio timeslots (or eight burst periods) are grouped into a TDMA frame. Half rate channels use alternate frames in the same timeslot. The channel data rate for all 8 channels is 270.833 Kbit/s, and the frame duration is 4.615 ms. The transmission power in the handset is limited to a maximum of 2 watts in GSM850/900 and 1 watt in GSM1800/1900.

Check if your GSM phone or modem supports SMS text mode: To check if your modem supports this text mode, you can try the following command: AT+CMGF=1 <ENTER> If the modem responds with "OK" this mode is supported. Please note that using this mode it is only possible to send simple text messages. It is not possible to send multipart, Unicode, data and other types of messages.

Setting up the modem If the modem contains a SIM card with is secured with a PIN code, we have to enter this pin code first: AT+CPIN="0000" <ENTER> (replace 0000 with your PIN code): Please not that in most cases you have only 3 attempts to set the correct PIN code. After setting the PIN code, wait some seconds before issuing the next command to give the modem some time to register with the GSM network. In order to send a SMS, the modem has to be put in SMS text mode first using the following command: AT+CMGF=1 <ENTER>

In text mode there are some additional parameters that can be set. Using the following command we can read the current values:
AT+CSMP? <ENTER> The modem wills response with a string like this: +CSMP: 1, 169, 0,0OK The first value is a combination of some option bits: bit 7 bit 6 bit 5 bit 3,4 bit 2 bit 0,1 RP UDHI SRR VPF RD MTI Reply path, not used in text mode User Data Header Information Set this bit to request a delivery report Validity Period, set b4=1 if a VP value is present Reject Duplicates, do not return a message ID when a message with the same destination and ID is still pending Message Type Indicatorb1=0 & b0=0 -> SMS-DELIVERb1=0 & b0=1 -> SMS-SUBMIT

Bit 0 of the message is always set when sending messages (SMS-SUBMIT). So the first value should be 1 or higher. The second parameter sets the Validity Period of the message. This value is encoded as follows: 0 - 143 144 - 167 (VP + 1) x 5 minutes 12 Hours + ((VP-143) x 30 minutes)

168 - 196 197 - 255

(VP-166) x 1 day (VP-192) x 1 week The third parameter contains the PID (Protocol Identifier). This parameter is only

used for advanced messaging. The fourth parameter contains the DCS (Data Coding Scheme). This parameter is used to select the character set/message type. When setting the DCS parameter to '0' standard 7 bit text is send. When setting this parameter to '16' the message is sent as a flash message. To send a message with a validity period of 1 day, the parameters have to be set like this: Bit 0 and 4 of the first field has to be set, so the first value will become 1 + 16 = 17. Send the following command to the modem to set this parameters: AT+CSMP=17, 167,0,16 <ENTER> If the modem responds with "OK" ,the modem is ready to send (flash) text messages with a validity period of 1 day. Sending the message To send the SMS message, type the following command: AT+CMGS="+31638740161" <ENTER>

Replace the above phone number with your own cell phone number. The modem will respond with:
>

You can now type the message text and send the message using the <CTRL>-<Z> key combination:
Hello World! <CTRL-Z>

After some seconds the modem will respond with the message ID of the message, indicating that the message was sent correctly:
+CMGS: 62

The message will arrive on the mobile phone shortly.

Sending an Unicode SMS message

Some modems also have the capability to send Unicode or UCS2 messages without encoding a PDU. You can send Unicode messages by only converting the Unicode data to a HEX string and send this string to the modem. To check whether your modem supports this mode, just type the following command: AT+CSCS=? This command displays the codepages supported by the modem. The modem will respond like this: +CSCS: ("GSM","PCCP437","CUSTOM","HEX") If this string contains "HEX" or "UCS2", Unicode seems to be supported. To specify that you will use an HEX string to send the message, set the codepage to "HEX" or "UCS2" depending on the modem response. In our example we will set the modem to "HEX: AT+CSCS="HEX" <ENTER>

Next, we have to specify the correct DCS (Data Coding Scheme) for Unicode messages, which is 0x08. We can set this value by changing the fourth parameter of the AT+CSMP command to '8': AT+CSMP=1,167,0,8 <ENTER> The modem is now ready to send messages as Unicode. Now is the time to send the actual message: AT+CMGS="+31638740161" <ENTER> Replace the above phone number with your own cell phone number. The modem will respond with: > The only thing you have to program by yourself, is a simple routine which converts the Unicode string to an hexadecimal string like this: Which is 'Hello' in Arabic will be converted like this: "06450631062D06280627" You can send this hexadecimal string to the modem: 06450631062D06280627 <CTRL-Z>

After some seconds the modem will respond with the message ID of the message, indicating that the message was sent correctly:

+CMGS: 63 The message will arrive on the mobile phone shortly.

Relay

RELAYS: Relays are used throughout the automobile. Relays which come in assorted sizes, ratings, and applications, are used as remote control switches. A typical vehicle can have 20 relays or more.

RELAY APPLICATIONS: Relays are remote control electrical switches that are controlled by another switch, such as a horn switch or a computer as in a power train control module. Relays allow a small current flow circuit to control a higher current circuit. Several designs of relays are in use today, 3- pin, 4-pin, 5-pin, and 6-pin, single switch or dual switches.

RELAY OPERATION:

When no voltage is applied to pin 1, there is no current flow through the coil. No current means no magnetic field is developed, and the switch is open. When voltage is supplied to pin 1, current flow though the coil creates the magnetic field needed to close the switch allowing continuity between pins 2 and 4.

ACTUAL RELAY DESIGN:

Current flows through the control coil, which is wrapped around an iron core. The iron core intensifies the magnetic field. The magnetic field attracts the upper contact AVR and pulls it down, closing the contacts and allowing power from the power source to go to the load

STANDARD MINI ISO RELAYS TYPES:

Below are two popular standard MINI ISO relay configurations. The size of a ISO Standard MINI relay is a 1" square cube. Both 4 and 5 pins designs are used. 4 PIN
MINI RELAY:

PRACTICAL TESTING:

Once the pins have been identified, energize the control circuit by supplying B+ to pin 1 and a ground to pin 3. A faint "click" will be heard; although this "click" means the switch has moved (closed), it does not mean the relay is good. The load circuit switch contacts could still be faulty (high resistance), and further testing is required. A common mistake technicians make is they hear a "click" and assume the relay is good. Take the extra step and verify operation.

OPERATIONAL CHECK WITH VOLTMETER:

A voltmeter can be substituted in place of a test light; however be aware if the contacts are partially burned, the voltmeter will show voltage indicating good contact even when bad. Remember high impedance digital voltmeters draw almost no current. Energize the relay (control side) by supplying B+ to pin 1 and a ground to pin 3. A click should be heard. With the relay still energized supply B+ to pin 2 of the load circuit. Connect the RED lead to pin 4 and the BLACK lead to ground. The voltmeter will indicate source voltage (12V). Deenergize (remove B+) the control circuit at pin 1; the voltmeter should now read "zero". Reenergize the relay and the voltmeter should return to 12 volts.

CAUTION:

Testing relays with built in clamping diodes require a special procedure. These relays are polarity sensitive; placing B+ to the wrong pin (backwards) while performing a practical test will forward bias the diode and damage the diode, thus destroying the protective quality of the diode.

OPERATIONAL CHECK FOR RELAY VOLTAGE SUPPRESSION DIODES:

An ANALOG OHMMETER must be used. This test cannot be performed with a digital meter. The analog meter sends out a higher voltage which is required to forward bias the diode. Place the ohmmeter across the control circuit and record reading. Reverse the leads and check the control circuit again. A functioning diode will be indicated by have two different readings. A faulty diode will have the same reading in both directions. Current from the ohmmeter flows through the control coil, in one direction. By reversing the leads, you send current in the opposite direction through the control coil. One of the two directions the diode will be forward biased(on), creating two paths for current thus lowering resistance. With the leads in the other direction, the diode in will be reversed biased (off) creating only one path, with higher resistance.

Relay:

SPDT Relay:

Reed Relay:

SERIAL COMMUNICATION

Computers transfer data in two ways: parallel and serial. In parallel data transfers, often 8 or more lines (wire conductors) are used to transfer data to a device that is only a few feet away. Examples of parallel transfers are printers and hard disk; each uses cables with many wire strips. Although in such cases a lot of data can be transferred in a short amount of time by using many wires in parallel, the distance cannot be great. To transfer to a device located at many meters away, the serial method is used. In serial communication, the data is sent one bit at a time, in contrast to parallel communication, in which the data is sent a byte or more at a time.

When a microprocessor communicates with the outside world, it provides the data in byte-sized chunks. In some cases, such as printers, the information is simply grabbed from the 8-bit data bus and presented to the 8-biut data bus of the printer. This can work only if the cable is not too long, since long cables diminish and even distort signals. Furthermore, an 8-bit data path is expensive. For these reasons, serial communication is used for transferring data between two systems located at distances of hundreds of feet to millions of miles apart. The fact that serial communication uses a single data line instead of the 8-bit data line of parallel communication not only makes it much cheaper but also enables two computers located in two different cities to communicate over the telephone. For serial data communication to work the byte of data must be converted to serial bits using a parallel-in-serial-out shift register; then it can be transmitted over a single data line. This also means that at the receiving end there must be a serial-in-parallel-out shift register to receive the serial data and pack them into a byte. Of course, if data is to be transferred on the telephone line, it must be converted from 0s and 1s to audio tones, which are sinusoidal-shaped signals. This conversion is performed by a peripheral device called a modem, which stands for modulator/demodulator. Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers a block of data at a time, while the asynchronous method transfers a single byte at a time. It is possible to write software to use either of these methods, but the programs can be tedious and long. For this reason, there are special IC chips made by many manufacturers for serial data communication. These chips are commonly referred to as UART (Universal Asynchronous Receiver and Transmitter) and USART (Universal Synchronous-Asynchronous Receiver and Transmitter). The 8051 microcontroller has a built-in UART. RS232 Standards To allow compatibility among data communication equipment made by various manufacturers, an interfacing standard called RS232 was set by the Electronics Industries Association (EIA) in 1960. Today, RS232 is the most widely used serial I/O interfacing standard. However, since the standard was set long before the advent of TTL logic family, its input and output voltage levels are not TTL compatible. In RS232, a 1 is represented by 3 to -25V, while a 0 bit is +3 to +25V, making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as

MAX232 to convert the TTL logic levels to the RS232 voltage levels, and vice versa. MAX232 IC chips are commonly referred to as line drivers. RS232 Pins The following table provides the pins and their labels for the RS232 cable, commonly referred to as the DB-25 connector. In labeling, DB-25P refers to the plug connector (male) and DB-25S is for the socket connector (female). PIN 1 2 3 4 5 6 7 8 9/10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DESCRIPTION Protective ground Transmitted data (TxD) Received data (RxD) Request to send (RTS) Clear to send (CTS) Data set ready (DSR) Signal ground (GND) Data carrier detect (DCD) Reserved for data testing Unassigned Secondary data carrier detect Secondary clear to send Secondary transmitted data Transmit signal element timing Secondary received data Receive signal element timing Unassigned Secondary request to send Data terminal ready (DTR) Signal quality detector Ring indicator Data signal rate select Transmit signal element timing Unassigned

Since not all the pins are used in PC cables, IBM introduced the DB-9 version of the serial I/O standard, which uses 9 pins only, as shown in the following table: PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION Data carrier detect (DCD) Received data (RxD) Transmitted data (TxD) Data terminal ready (DTR) Signal ground (GND) Data set ready (DSR) Request to send (RTS) Clear to send (CTS) Ring indicator (RI)

DB 9 Connector

The D-subminiature or D-sub is a common type of electrical connector used particularly in computers. At the time of introduction they were some of the smaller connectors used on computer systems.

A D-sub contains two or more parallel rows of pins or sockets usually surrounded by a D-shaped metal shield that provides mechanical support, some screening against electromagnetic interference, and ensures correct orientation. The part containing pin contacts is called the male connector or plug, while that containing socket contacts is called the female connector or socket. The socket's shield fits tightly inside the plug's shield. The shields are connected to the overall screens of the cables (when screened cables are used). This creates an electrically continuous screen covering the whole cable and connector system. D-subminiature connectors were invented by ITT Cannon, part of ITT Corporation, in 1952.[1] Cannon's part-numbering system uses a D as the prefix for the whole series, followed by a letter denoting the shell size (A=15 pin, B=25 pin, C=37 pin, D=50 pin, E=9 pin), followed by the actual number of pins, followed by the gender (P=plug, S=socket).[2] For example, DB25 denotes a D-sub with a 25 position shell size and a 25 position contact configuration. The contacts in these connectors are spaced approximately 0.109 inches (2.77 mm) apart with the rows spaced 0.112 inches (2.84 mm) apart.[3] (To be precise, the horizontal contact spacing is 326/3000 = 108/1000 = 0.1086 inch per row, with the second row offset by half that amount.) Cannon also produced "hybrid" D-subs with larger positions in place of some of the normal pin positions that could be used for either high-current, high-voltage, or co-axial inserts. The DB13W3 variant was commonly used for high-performance video connections; this variant provided 10 regular (#20) pins plus three coaxial contacts for the red, green, and blue video signals. Hybrid D-subs are currently being manufactured in a broad range of configurations by other companies, including Amphenol, Conec, Teledyne Reynolds, Assmann Electronics, Norcomp, Cinch, 3M, and Tyco. Variations include current ratings

up to 40A, operating voltages as high as 13,500V, and waterproof variants that are certified to IP67 standards. In the photograph below, the connector on the left is a 9-pin male (DE-9M) connector plug, and the one on the right is a 25-pin female (DB-25F) socket. The hexagonal pillars at either end of each connector have a threaded stud (not visible) that passes through flanges on the connector, fastening it to the metal panel. They also have a threaded hole that receives the jackscrews on the cable shell, to hold the plug and socket together. Because PCs first used DB25 connectors for their serial and parallel ports, when the PC serial port began to use 9-pin connectors, they were often called "DB9" instead of DE9, due to the lack of understanding that the "B" represented a shell size. It is now common to see DE9 connectors sold as "DB9" connectors. DB-9 is nearly always intended to be a 9 pin connector with an E size shell. The non-standard 23-pin D-sub connectors for external floppy drives and video output on most of the Amiga computers are usually referred to as DB23, even though their shell size is two pins smaller than ordinary DB sockets. There are now D-sub connectors which have the original shell sizes, but more pins, and the names follow the same pattern. For example, the DE15, usually found in VGA cables, has 15 pins, in three rows, in an E size shell. The pins are spaced 0.090 inch horizontally and 0.078 inch vertically.) The full list of connectors with this pin spacing is: DE15, DA26, DB44, DC62, and DD78. Alternatively, following the same confusion mentioned above in which all D-sub connectors are called "DB", these connectors are often called DB15HD, DB26HD, DB44HD, DB62HD, and DB78HD, where the "HD" stands for "high density". They all have 3 rows of pins, except the DD78, which has 4. A series of D-sub connectors with even denser pins is called "double density", and consists of DE19, DA31, DB52, DC79, and DD100. They have 4 rows of pins. There is yet another similar family of connectors that is easy to confuse with the Dsub family, but is not part of it. These connectors have names like "HD50" and "HD68", and have a D-shaped shell but the shell is about half the width of a DB25. They are common in SCSI attachments.

The suffixes M and F (male and female) are sometimes used instead of the original P and S (plug and socket). The original D-subminiature connectors are now defined by an international standard, DIN 41652. The United States military also specifies D-subminiature connectors using the MIL-DTL-24308 standard. Typical applications

Communications ports The widest application of D-subs is for RS-232 serial communications, though the standard did not make this connector mandatory. RS-232 devices originally used the DB25 25-pin D-sub, but for many applications the less common signals were omitted, allowing a DE9 9-pin D-sub to be used. The standard indicates a male connector for terminal equipment and a female connector for modems, but many variations exist. IBM PC compatible computers tend to have male connectors at the device, while modems have female connectors. Early Apple Macintosh models used DE9 connectors for RS-422 serial interfaces (which can operate as RS-232). Later Macintosh models used 8 pin miniature DIN connectors instead. On PCs, 25-pin and (beginning with the IBM-PC/AT) 9-pin plugs are used for the RS-232 serial ports; and 25-pin sockets are used for the parallel printer ports (instead of the Centronics socket found on the printer itself). 25-pin sockets on Macintosh computers are typically SCSI connectors (again in contrast to the Centronics C50 connector typically found on the peripheral), while older Sun hardware uses DD50 connectors for FastSCSI equipment.

Many uninterruptible power supply units have a DE9F connector on them, in order to signal to the attached computer via an RS-232 interface. Often these do not send data serially to the computer but instead use the handshaking control lines to indicate low battery, power failure or other conditions. Such usage is not standardized between manufacturers and may require special cables to be supplied.

MAX232

The MAX232 is an integrated circuit that converts signals from an RS-232 serial port to signals suitable for use in TTL compatible digital logic circuits. The MAX232 is a dual driver/receiver and typically converts the RX, TX, CTS and RTS signals. The drivers provide RS-232 voltage level outputs (approx. 7.5 V) from a single + 5 V supply via on-chip charge pumps and external capacitors. This makes it useful for implementing RS-232 in devices that otherwise do not need any voltages outside the 0 V to + 5 V range, as power supply design does not need to be made more complicated just for driving the RS-232 in this case. The receivers reduce RS-232 inputs (which may be as high as 25 V), to standard 5 V TTL levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of 0.5 V. The later MAX232A is backwards compatible with the original MAX232 but may operate at higher baud rates and can use smaller external capacitors 0.1F in place of the 1.0F capacitors used with the original device. The newer MAX3232 is also backwards compatible, but operates at a broader voltage range, from 3 to 5.5V. Pin Diagram of MAX232:

Typical Applications:

Voltage Levels It is helpful to understand what occurs to the voltage levels. When a MAX232 IC receives a TTL level to convert, it changes a TTL Logic 0 to between +3 and +15V, and changes TTL Logic 1 to between -3 to -15V, and vice versa for converting from RS232 to TTL. This can be confusing when you realize that the RS232 Data Transmission voltages at a certain logic state are opposite from the RS232 Control Line voltages at the same logic state. To clarify the matter, see the table below. RS232 Line Type & Logic Level Data Transmission (Rx/Tx) Logic 0 Data Transmission (Rx/Tx) Logic 1 Control Signals (RTS/CTS/DTR/DSR) Logic 0 RS232 Voltage +3V to +15V -3V to -15V -3V to -15V TTL Voltage to/from MAX232 0V 5V 5V

Control Signals (RTS/CTS/DTR/DSR) Logic 1

+3V to +15V

0V

AVR STUDIO
AVR Studio 4 is a professional Integrated Development Environment (IDE) for writing and debugging AVR applications in Windows 9x/NT/2000/XP environments. This tutorial assumes that you have installed AVR Studio 4 on your computer. If you do not have AVR Studio yet, you may obtain a copy of AVR Studio 4 from one of 3 places:

1. Atmel Corporation: http://www.atmel.com

2. AVR Freaks: http://www.avrfreaks.net 3. Borrow a CD from your instructor This will guide you through the steps required for: 1. Executing the AVR Studio 4 Integrated Development Environment (IDE), 2. Typing in a program, 3. Assembling the program, and 4. Simulating a program Step 1: Open AVR Studio 4 IDE. You should see the program banner shown below:

Figure : AVR Studio 4 Banner

Step 2: When IDE opens, you will see the programming and simulator environment as well as a dialog box (Figure 3) requesting information: are you starting a new project or opening a saved project?

Step 3: Click on the New Project button:

Step 4: In the next dialog box, choose the Atmel AVR Assembler as the project type:

Figure : Choose Atmel AVR Assembler

Step 5: Type in a project name and the initial file name:

Figure: Type Project and Initial File Names

Step 6: Click on the Next button

Step 7: Choose AVR Simulator for the Debug Platform and then scroll down the right window to choose the ATmega32 AVR processor. Select in the drop down list.

Figure : Choose Simulator and ATmega32

Step 8: Click on the Finish button. You should then see the IDE (you may have to maximize the editing window to see the same thing as shown in Figure 8):

Figure : AVR Studio 4 IDE

Step 9: Type in the program as shown in Figure 1. Note the color-coded text. This is done automatically by the IDE and helps you to make corrections as you go.

Step 10: When you have completed the program save it. It is also good practice to periodically save your program as you type. Step 11: Assemble your program. You may do this by selecting Build from the Build Menu or by striking the [F7] key:

Figure Program Assembled

Step 12: Continue assembling and correcting errors until the program assembles without error (Note the green dot in the lower window and the comment that states: Assembly complete, 0 Errors, 0 warnings) you are ready to simulate. Step 13: Simulate the program. To start the simulator you may choose Start Debugging from The Debug Menu or you may click on the arrow button as shown below:

Code

CHAPTER METHODOLOGY AND DESIGN TOOLS

This chapter discusses methodology and design tools that used to develop and implement this project. Contents of this chapter include design methodology flow, Verilog HDL and EDA tools such as XILINX 12.1 ISE, FPGA synthesis, XILINX SYSTEM GENERATOR.

Xilinx ISE Overview The Integrated Software Environment (ISE) is the Xilinx design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator manages and processes your design through the following steps in the ISE design flow. A simplified version of design flow is given in the flowing diagram.

Figure 3.5: FPGA Design Flow

Design Entry There are different techniques for design entry. Schematic based, Hardware Description Language and combination of both etc. Selection of a method depends on the design and designer. If the designer wants to deal more with Hardware, then Schematic entry is the better choice. When the design is complex or the designer thinks the design in an algorithmic way then HDL is the better choice. Language based entry is faster but lag in performance and density. HDLs represent a level of abstraction that can isolate the designers from the details of the hardware implementation. Schematic based entry gives designers much more visibility into the hardware. It is the better choice for those who are hardware oriented. Another method but rarely used is statemachines. It is the better choice for the designers who think the design as a series of states. But the tools for state machine entry are limited. In this documentation we are going to deal with the HDL based design entry.

Synthesis The process which translates VHDL or Verilog code into a device netlist format. i.e a complete circuit with logical elements (gates, flip flops, etc) for the design.If the design contains more than one sub designs, ex. to implement a processor, we need a CPU as one design element and RAM as another and so on, then the synthesis process generates netlist for each design element Synthesis process will check code syntax and analyze the hierarchy of the design which ensures that the design is optimized for the design architecture, the designer has selected. The resulting netlist(s) is saved to an NGC( Native Generic Circuit) file (for Xilinx Synthesis Technology (XST)).

Implementation This process consists a sequence of three steps 1. Translate 2. Map 3. Place and Route Translate process combines all the input netlists and constraints to a logic design file. This information is saved as a NGD (Native Generic Database) file. This can be done using NGD Build program. Here, defining constraints is nothing but, assigning the ports in the design to the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying time requirements of the design. This information is stored in a file named UCF (User Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.

Map process divides the whole circuit with logical elements into sub blocks such that they can be fit into the FPGA logic blocks. That means map process fits the logic defined by the NGD file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input Output Blocks (IOB)) and generates an NCD (Native Circuit Description) file which physically represents the design mapped to the components of FPGA. MAP program is used for this purpose.

Place and Route PAR program is used for this process. The place and route process places the sub blocks from the map process into logic blocks according to the constraints and connects the logic blocks. Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the time but it may effect some other constraint. So trade off between all the constraints is taken account by the place and route process

The PAR tool takes the mapped NCD file as input and produces a completely routed NCD file as output. Output NCD file consists the routing information.

Device Programming Now the design must be loaded on the FPGA. But the design must be converted to a format so that the FPGA can accept it. BITGEN program deals with the conversion. The routed NCD file is then given to the BITGEN program to generate a bit stream (a .BIT file) which can be used to configure the target FPGA device. This can be done using a cable. Selection of cable depends on the design.

Design Verification Verification can be done at different stages of the process steps. Behavioral Simulation (RTL Simulation) This is first of all simulation steps; those are encountered throughout the hierarchy of the design flow. This simulation is performed before synthesis process to verify RTL (behavioral) code and to confirm that the design is functioning as intended. Behavioral simulation can be performed on either VHDL or Verilog designs. In this process, signals and variables are observed, procedures and functions are traced and breakpoints are set. This is a very fast simulation and so allows the designer to change the HDL code if the required functionality is not met with in a short time period. Since the design is not yet synthesized to gate level, timing and resource usage properties are still unknown. Functional simulation (Post Translate Simulation) Functional simulation gives

information about the logic operation of the circuit. Designer can verify the functionality of the design using this process after the Translate process. If the functionality is not as expected, then the designer has to made changes in the code and again follow the design flow steps.
Static Timing Analysis This can be done after MAP or PAR processes Post MAP timing report lists signal path delays of the design derived from the design logic. Post Place and Route timing report incorporates timing delay information to provide a comprehensive timing summary of the design.

3.4 Hardware Design Using System Generator

System Generator is a system-level modeling tool that facilitates FPGA hardware design. It extends Simulink in many ways to provide a modeling environment that is well suited to hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through low-level abstractions, allowing the construction of highly efficient FPGA designs.

A Brief Introduction to FPGAs A field programmable gate array (FPGA) is a general-purpose integrated circuit that is programmed by the designer rather than the device manufacturer. Unlike an application-specific integrated circuit (ASIC), which can perform a similar function in an electronic system, an FPGA can be reprogrammed, even after it has been deployed into a system. An FPGA is programmed by downloading a configuration program called a bitstream into static onchip random-access memory. Much like the object code for a microprocessor, this bitstream is the product of compilation tools that translate the high-level abstractions produced by a designer into something equivalent but low-level and executable. Xilinx System Generator pioneered the idea of compiling an FPGA program from a high-level Simulink model.

An FPGA provides you with a two-dimensional array of configurable resources that can implement a wide range of arithmetic and logic functions. These resources include dedicated DSP blocks, multipliers, dual port memories, lookup tables (LUTs), registers, tristate buffers, multiplexers, and digital clock managers. In addition, Xilinx FPGAs contain sophisticated I/O mechanisms that can handle a wide range of bandwidth and voltage requirements. The Virtex-4 and Virtex-II Pro family FPGAs include embedded microcontrollers (IBM PowerPC 405), and multi-gigabit serial transceivers. The compute and I/O resources are linked under the control of the bitstream by a programmable interconnect architecture that allows them to be wired together into systems. FPGAs are high performance data processing devices. DSP performance is derived from the FPGAs ability to construct highly parallel architectures for processing data. In contrast with a microprocessor or DSP processor, where performance is tied to the clock rate at which the processor can run, FPGA performance is tied to the amount of parallelism that can be brought to bear in the algorithms that make up a signal processing system. A combination of increasingly high system clock rates (current system frequencies of 100-200 MHz are common today) and a highlydistributed memory architecture gives the system designer an ability to exploit parallelism in DSP (and other) applications that operate on data streams. For example, the raw memory bandwidth of a large FPGA running at a clock rate of 150 MHz can be hundreds of terabytes per second. There are many DSP applications (e.g., digital up/down converters) that can be implemented only in custom integrated circuits (ICs) or in an FPGA; a von Neumann processor lacks both the compute capability and the memory bandwidth required. Advantages of using an FPGA include significantly lower non-recurring engineering costs than those associated with a custom IC (FPGAs are commercial off-the-shelf devices), shorter time to market, and the configurability of an FPGA, which allows a design to be modified, even after

deployment in an end application. When working in System Generator, it is important to keep in mind that an FPGA has many degrees of freedom in implementing signal processing functions. You have, for example, the freedom to define data path widths throughout your system and to employ many individual data processors (e.g., multiply-accumulate engines), depending on system requirements. System Generator provides abstractions that allow you to design for an FPGA largely by thinking about the algorithm you want to implement. However, the more you know about the underlying FPGA, the more likely you are to exploit the unique capabilities an FPGA provides in achieving high performance. The remainder of this topic is a brief introduction to some of the logic resources available in the FPGA, so that you gain some appreciation for the abstractions provided in System Generator.

The figure above shows a physical view of a Virtex-4 FPGA. To a signal DSP engineer, an FPGA can be thought of as a 2-D array of logic slices striped with columns of hard macro blocks (block memory and arithmetic blocks) suitable for implementing DSP functions, embedded within a configurable interconnect mesh. In a Virtex-4 FPGA, the DSP blocks (shown in the next figure) can run in excess of 450 MHz, and are pitch-matched to dual port memory blocks (BRAMs) whose ports can be configured to a wide range of word sizes (18 Kb total per BRAM). The Virtex-4 SX55 device contains 512 such DSP blocks and BRAMs. In System Generator, you can access all of these resources through arithmetic and logic abstractions to build very high performance digital filters, FFTs, and other arithmetic and signal processing functions.

While the multiply-accumulate function supported by a Virtex-4 DSP block is familiar to a DSP engineer, it is instructive to take a closer look at the Virtex family logic slice (shown below), which is the fundamental unit of the logic fabric array.

Each logic slice contains two 4-input lookup tables (LUTs), two configurable D-flip flops, multiplexers, dedicated carry logic, and gates used for creating slice-based multipliers. Each LUT can implement an arbitrary 4-input Boolean function. Coupled with dedicated logic for implementing fast carry circuits, the LUTs can also be used to build fast adder/subtractors and multipliers of essentially any word size. In addition to implementing Boolean functions, each LUT

can also be configured as a 16x1 bit RAM or as a shift register (SRL16). An SRL16 shift register is a synchronously clocked 16x1 bit delay line with a dynamically addressable tap point. In System Generator, these different memory options are represented with higher-level abstractions. Instead of providing a D-flip flop primitive, System Generator provides a register of arbitrary size. There are two blocks that provide abstractions of arbitrary width, arbitrary depth delay lines that map directly onto the SRL16 configuration. The delay block can be used for pipeline balancing, and can also be used as storage for time division multiplexed (TDM) data streams. The addressable shift register (ASR) block, with a function depicted in the figure below, provides an arbitrary width, arbitrary depth tapped delay line. This block is of particular interest to the DSP engineer, since it can be used to implement tapped delay lines as well as sweeping through TDM data streams.

Although random access memories can be constructed either out of the BRAM or LUT (RAM16x1) primitives, doing so can require considerable care to ensure most efficient mappings, and considerable clerical attention to detail to correctly assemble the primitives into larger structures. System Generator removes the need for such tasks. System Generator extends Simulink to enable hardware design, providing high-level abstractions that can be automatically compiled into an FPGA. Although the arithmetic abstractions are suitable to Simulink (discrete time and space dynamical system simulation), System Generator also provides access to features in the underlying FPGA. The more you know about a hardware realization (e.g., how to exploit parallelism and pipelining), the better the implementation youll obtain. Using IP cores makes it possible to have efficient FPGA designs that including complex functions like FFTs. System Generator also makes it possible to refine a model to more accurately fit the application. Scattered throughout the System Generator documentation are notes that explain ways in which system parameters can be used to exploit hardware capabilities.

System Generator does not replace hardware description language (HDL)-based design, but does make it possible to focus your attention only on the critical parts. By analogy, most DSP programmers do not program exclusively in assembler; they start in a higher level language like C, and write assembly code only where it is required to meet performance requirements. A good rule of thumb is this: in the parts of the design where you must manage internal hardware clocks (e.g., using the DDR or phased clocking), you should implement using HDL. The less critical portions of the design can be implemented in System Generator, and then the HDL and System Generator portions can be connected. Usually, most portions of a signal processing system do not need this level of control, except at external interfaces.

INTRODUCTION TO VHDL

This tutorial gives a brief overview of the VHDL language and is mainly intended as a companion for the Digital Design Laboratory. This writing aims to give the reader a quick introduction to VHDL and to give a complete or in-depth discussion of VHDL. For a more detailed treatment, please consult any of the many good books on this topic. Several of these books are listed in the reference list.

1. Introduction

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. In the mid-1980s the U.S. Department of Defense and the IEEE sponsored the development of this hardware description language with the goal to develop very high-speed integrated circuit. It has become now one of industrys standard languages used to describe digital systems. The other widely used hardware description language is Verilog. Both are powerful languages that allow you to describe and simulate complex digital systems. A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This tutorial deals with VHDL, as described by the IEEE standard 1076-1993.

Although these languages look similar as conventional programming languages, there are some important differences. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different components.

2. Levels of representation and abstraction

A digital system can be represented at different levels of abstraction [1]. This keeps the description and design of complex systems manageable. Figure 1 shows different levels of abstraction.

Figure 1: Levels of abstraction: Behavioral, Structural and Physical The highest level of abstraction is the behavioral level that describes a system in terms of what it does (or how it behaves) rather than in terms of its components and interconnection between them. A behavioral description specifies the relationship between the input and output signals. This could be a Boolean expression or a more abstract description such as the Register Transfer or Algorithmic level. As an example, let us consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used whenever the car key is inserted in the ignition lock At the behavioral level this could be expressed as,

Warning = Ignition_on AND ( Door_open OR Seatbelt_off)

The structural level, on the other hand, describes a system as a collection of gates and components that are interconnected to perform a desired function. A structural description could be compared to a schematic of interconnected logic gates. It is a representation that is usually closer to the physical realization of a system. For the example above, the structural representation is shown in Figure 2 below.

Figure 2: Structural representation of a buzzer circuit.

VHDL allows one to describe a digital system at the structural or the behavioral level. The behavioral level can be further divided into two kinds of styles: Data flow and Algorithmic. The dataflow representation describes how data moves through the system. This is typically done in terms of data flow between registers (Register Transfer level). The data flow model makes use of concurrent statements that are executed in parallel as soon as data arrives at the input. On the other hand, sequential statements are executed in the sequence that they are specified. VHDL allows both concurrent and sequential signal assignments that will determine the manner in which they are executed. Examples of both representations will be given later.

3. Basic Structure of a VHDL file

A digital system in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity declaration and an architecture body. One can consider the entity declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in Figure 3 below. In a typical design there will be many such entities connected together to perform the desired function.

Figure 3: A VHDL entity consisting of an interface (entity declaration) and a body (architectural description).VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords and user-defined identifiers are case insensitive. Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and extra spaces. VHDL is a strongly typed language which implies that one has always to declare the type of every object that can have a value, such as signals, constants and variables.

Entity Declaration:

The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows,

entity NAME_OF_ENTITY is [ generic generic_declarations);] port (signal_names: mode type; signal_names: mode type; : signal_names: mode type); end [NAME_OF_ENTITY] ;

An entity always starts with the keyword entity, followed by its name and the keyword is. Next are the port declarations using the keyword port. An entity declaration always ends with the keyword end, optionally [] followed by the name of the entity.

The NAME_OF_ENTITY is a user-selected identifier signal_names consists of a comma separated list of one or more user-selected

identifiers that specify external interface signals. o o mode: is one of the reserved words to indicate the signal direction: o o in indicates that the signal is an input out indicates that the signal is an output of the entity whose value can

only be read by other entities that use it. o o buffer indicates that the signal is an output of the entity whose value can

be read inside the entitys architecture o o inout the signal can be an input or an output.

type: a built-in or user-defined signal type. Examples of types are bit, bit_vector,

Boolean, character, std_logic, and std_ulogic. o o o o o o bit can have the value 0 and 1 bit_vector is a vector of bit values (e.g. bit_vector (0 to 7) std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9

values to indicate the value and strength of a signal. Std_ulogic and std_logic are preferred over the bit or bit_vector types. o o o o o o o o o o boolean can have the value TRUE and FALSE integer can have a range of integer values real can have a range of real values character any printing character time to indicate time

generic: generic declarations are optional and determine the local constants used

for timing and sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a generic follows,

generic (constant_name: type [:=value] ; constant_name: type [:=value] ;

: constant_name: type [:=value] );

For the example of Figure 2 above, the entity declaration looks as follows.

-- comments: example of the buzzer circuit of fig. 2 entity BUZZER is port (DOOR, IGNITION, SBELT: in std_logic; WARNING: out std_logic); end BUZZER;

The entity is called BUZZER and has three input ports, DOOR, IGNITION and SBELT and one output port, WARNING. Notice the use and placement of semicolons! The name BUZZER is an identifier. Inputs are denoted by the keyword in, and outputs by the keyword out. Since VHDL is a strongly typed language, each port has a defined type. In this case, we specified the std_logic type. This is the preferred type of digital signals. In contrast to the bit type that can only have the values 1 and 0, the std_logic and std_ulogic types can have nine values. This is important to describe a digital system accurately including the binary values 0 and 1, as well as the unknown value X, the uninitialized value U, - for dont care, Z for high impedance, and several symbols to indicate the signal strength (e.g. L for weak 0, H for weak 1, W for weak unknown - see section on Enumerated Types). The std_logic type is defined in the std_logic_1164 package of the IEEE library. The type defines the set of values an object can have. This has the advantage that it helps with the creation of models and helps reduce errors. For instance, if one tries to assign an illegal value to an object, the compiler will flag the error.

A few other examples of entity declarations follow

Four-to-one multiplexer of which each input is an 8-bit word.

entity mux4_to_1 is port (I0,I1,I2,I3: in std_logic_vector(7 downto 0); SEL: in std_logic_vector (1 downto 0); OUT1: out std_logic_vector(7 downto 0)); end mux4_to_1;

An example of the entity declaration of a D flip-flop with set and reset inputs is

entity dff_sr is port (D,CLK,S,R: in std_logic; Q,Qnot: out std_logic); end dff_sr;

a.

b. Architecture body

The architecture body specifies how the circuit operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above.

The architecture body looks as follows,

architecture architecture_name of NAME_OF_ENTITY is -- Declarations

-- components declarations -- signal declarations -- constant declarations -- function declarations -- procedure declarations -- type declarations

begin -- Statements

end architecture_name;

Behavioral model
The architecture body for the example of Figure 2, described at the behavioral level, is given below,

architecture behavioral of BUZZER is begin WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION); end behavioral;

The header line of the architecture body defines the architecture name, e.g. behavioral, and associates it with the entity, BUZZER. The architecture name can be any legal identifier. The main body of the architecture starts with the keyword begin and gives the Boolean expression of the function. We will see later that a behavioral model can be described in several other ways. The <= symbol represents an assignment operator and assigns the value of the expression on the right to the signal on the left. The architecture body ends with an end keyword followed by the architecture name.

A few other examples follow. The behavioral description of a two-input AND gate is shown below.

entity AND2 is port (in1, in2: in std_logic; out1: out std_logic); end AND2;

architecture behavioral_2 of AND2 is begin out1 <= in1 and in2; end behavioral_2;

An example of a two-input XNOR gate is shown below.

entity XNOR2 is port (A, B: in std_logic; Z: out std_logic); end XNOR2;

architecture behavioral_xnor of XNOR2 is -- signal declaration (of internal signals X, Y) signal X, Y: std_logic; begin X <= A and B; Y <= (not A) and (not B); Z <= X or Y; End behavioral_xnor;

The statements in the body of the architecture make use of logic operators. Logic operators that are allowed are: and, or, nand, nor, xor, xnor and not. In addition, other types of operators including relational, shift, arithmetic are allowed as well (see section on Operators). For more information on behavioral modeling see section on Behavioral Modeling. Concurrency It is worth pointing out that the signal assignments in the above examples are concurrent statements. This implies that the statements are executed when one or more of the signals on the right hand side change their value (i.e. an event occurs on one of the signals). For instance, when the input A changes, the internal signals X and Y change values that in turn causes the last statement to update the output Z. There may be a propagation delay associated with this change. Digital systems are basically datadriven and an event which occurs on one signal will lead to an event on another signal, etc. The execution of the statements is determined by the flow of signal values. As a result, the order in which these statements are given does not matter (i.e., moving the statement for the output Z ahead of that for X and Y does not change the outcome). This is in contrast to conventional, software programs that execute the statements in a sequential or procedural manner.

Structural description
The circuit of Figure 2 can also be described using a structural model that specifies what gates are used and how they are interconnected. The following example illustrates it.

architecture structural of BUZZER is -- Declarations component AND2 port (in1, in2: in std_logic; out1: out std_logic); end component; component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component; component NOT1 port (in1: in std_logic; out1: out std_logic); end component; -- declaration of signals used to interconnect gates signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic; begin -- Component instantiations statements U0: NOT1 port map (DOOR, DOOR_NOT); U1: NOT1 port map (SBELT, SBELT_NOT); U2: AND2 port map (IGNITION, DOOR_NOT, B1); U3: AND2 port map (IGNITION, SBELT_NOT, B2); U4: OR2 port map (B1, B2, WARNING);

end structural;

Following the header is the declarative part that gives the components (gates) that are going to be used in the description of the circuits. In our example, we use a two- input AND gate, two-input OR gate and an inverter. These gates have to be defined first, i.e. they will need an entity declaration and architecture body (as shown in the previous example). These can be stored in one of the packages one refers to in the header of the file (see Library and Packages below). The declarations for the components give the inputs (e.g. in1, in2) and the output (e.g. out1). Next, one has to define internal nets (signal names). In our example these signals are called DOOR_NOT, SBELT_NOT, B1, B2 (see Figure 2). Notice that one always has to declare the type of the signal.

The statements after the begin keyword gives the instantiations of the components and describes how these are interconnected. A component instantiation statement creates a new level of hierarchy. Each line starts with an instance name (e.g. U0) followed by a colon and a component name and the keyword port map. This keyword defines how the components are connected. In the example above, this is done through positional association: DOOR corresponds to the input, in1 of the NOT1 gate and DOOR_NOT to the output. Similarly, for the AND2 gate where the first two signals (IGNITION and DOOR_NOT) correspond to the inputs in1 and in2, respectively, and the signal B1 to the output out1. An alternative way is to use explicit association between the ports, as shown below.

label: component-name port map (port1=>signal1, port2=> signal2, port3=>signaln);

U0: NOT1 port map (in1 => DOOR, out1 => DOOR_NOT); U1: NOT1 port map (in1 => SBELT, out1 => SBELT_NOT); U2: AND2 port map (in1 => IGNITION, in2 => DOOR_NOT, out1 => B1); U3: AND2 port map (in1 => IGNITION, in2 => SBELT_NOT, B2); U4: OR2 port map (in1 => B1, in2 => B2, out1 => WARNING);

Notice that the order in which these statements are written has no bearing on the execution since these statements are concurrent and therefore executed in parallel. Indeed, the schematic that is described by these statements is the same independent of the order of the statements.

Structural modeling of design lends itself to hierarchical design, in which one can define components of units that are used over and over again. Once these components are defined they can be used as blocks, cells or macros in a higher level entity. This can significantly reduce the complexity of large designs. Hierarchical design approaches are always preferred over flat designs. We will illustrate the use of a hierarchical design approach for a 4-bit adder, shown in Figure 4 below. Each full adder can be described by the Boolean expressions for the sum and carry out signals,

sum = (A B) C carry = AB + C(A B)

Figure 4: Schematic of a 4-bit adder consisting of full adder modules.

In the VHDL file, we have defined a component for the full adder first. We used several instantiations of the full adder to build the structure of the 4-bit adder. We have included the library and use clause as well as the entity declarations.

Four Bit Adder Illustrating a hierarchical VHDL model -- Example of a four bit adder library use ieee;

ieee.std_logic_1164.all;

-- definition of a full adder entity FULLADDER is port (a, b, c: in std_logic; sum, carry: out std_logic); end FULLADDER; architecture fulladder_behav of FULLADDER is begin sum <= (a xor b) xor c ; carry <= (a and b) or (c and (a xor b)); end fulladder_behav;

-- 4-bit adder library use ieee;

ieee.std_logic_1164.all;

entity FOURBITADD is port (a, b: in std_logic_vector(3 downto 0); Cin : in std_logic; sum: out std_logic_vector (3 downto 0); Cout, V: out std_logic);

end FOURBITADD;

architecture fouradder_structure of FOURBITADD is signal c: std_logic_vector (4 downto 0); component FULLADDER port(a, b, c: in std_logic; sum, carry: out std_logic); end component; begin FA0: FULLADDER port map (a(0), b(0), Cin, sum(0), c(1)); FA1: FULLADDER port map (a(1), b(1), C(1), sum(1), c(2)); FA2: FULLADDER port map (a(2), b(2), C(2), sum(2), c(3)); FA3: FULLADDER port map (a(3), b(3), C(3), sum(3), c(4)); V <= c(3) xor c(4); Cout <= c(4); end fouradder_structure;

Notice that the same input names a and b for the ports of the full adder and the 4-bit adder were used. This does not pose a problem in VHDL since they refer to different levels. However, for readability, it may be easier to use different names. We needed to define the internal signals c(4:0) to indicate the nets that connect the output carry to the input carry of the next full adder. For the first input we used

the input signal Cin. For the last carry we defined c(4) as an internal signal since the last carry is needed as the input to the xor gate. We could not use the output signal Cout since VHDL does not allow the use of outputs as internal signals! For this reason we had to define the internal carry c(4) and assign c(4) to the output carry signal Cout.

See also the section on Structural Modeling.

b.

c.

Library and Packages: library and use keywords

A library can be considered as a place where the compiler stores information about a design project. A VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions that can be shared among different VHDL models.

We mentioned earlier that std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order to use the std_logic one needs to specify the library and package. This is done at the beginning of the VHDL file using the library and the use keywords as follows:

library ieee; use ieee.std_logic_1164.all; The .all extension indicates to use all of the ieee.std_logic_1164 package.

The Xilinx Foundation Express comes with several packages.

ieee Library:

std_logic_1164 package: defines the standard datatypes

std_logic_arith package: provides arithmetic, conversion and comparison functions for the

signed, unsigned, integer, std_ulogic, std_logic and std_logic_vector types std_logic_unsigned std_logic_misc package: defines supplemental types, subtypes, constants and functions for

the std_logic_1164 package.

To use any of these one must include the library and use clause: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

In addition, the synopsis library has the attributes package:

library SYNOPSYS; use SYNOPSYS.attributes.all;

One can add other libraries and packages. The syntax to declare a package is as follows:

-- Package declaration package name_of_package is package declarations end package name_of_package; -- Package body declarations package body name_of_package is package body declarations

end package body name_of_package;

For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc. components need to be defined before one can use them. This can be done in a package, e.g. basic_func for each of these components, as follows:

-- Package declaration library ieee; use ieee.std_logic_1164.all; package basic_func is -- AND2 declaration component AND2 generic (DELAY: time :=5ns); port (in1, in2: in std_logic; out1: out std_logic); end component; -- OR2 declaration component OR2 generic (DELAY: time :=5ns); port (in1, in2: in std_logic; out1: out std_logic); end component; end package basic_func;

-- Package body declarations library ieee; use ieee.std_logic_1164.all;

package body basic_func is -- 2 input AND gate entity AND2 is generic (DELAY: time); port (in1, in2: in std_logic; out1: out std_logic); end AND2; architecture model_conc of AND2 is begin out1 <= in1 and in2 after DELAY; end model_conc; -- 2 input OR gate entity OR2 is generic (DELAY: time); port (in1, in2: in std_logic; out1: out std_logic); end OR2; architecture model_conc2 of AND2 is begin out1 <= in1 or in2 after DELAY; end model_conc2; end package body basic_func;

Notice that we included a delay of 5 ns. However, it should be noticed that delay specifications are ignored by the Foundation synthesis tool. We made use of the predefined type std_logic that is declared in the package std_logic_1164. We have included the library and use clause for this package. This package needs to be compiled and placed in a library. Lets call this library my_func. To use the components of this package one has to declare it using the library and use clause:

library ieee, my_func; use ieee.std_logic_1164.all, my_func.basic_func.all;

One can concatenate a series of names separated by periods to select a package. The library and use statements are connected to the subsequent entity statement. The library and use statements have to be repeated for each entity declaration.

One has to include the library and use clause for each entity as shown for the example of the four-bit adder above.

4. Lexical Elements of VHDL

a.

a.

Identifiers

Identifiers are user-defined words used to name objects in VHDL models. We have seen examples of identifiers for input and output signals as well as the name of a design entity and architecture body. When choosing an identifier one needs to follow these basic rules:

May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the

underscore (_) character object) An identifier can be of any length. The first character must be a letter and the last one cannot be an underscore. An identifier cannot include two consecutive underscores. An identifier is case insensitive (ex. And2 and AND2 or and2 refer to the same

Examples of valid identifiers are: X10, x_10, My_gate1. Some invalid identifiers are: _X10, my_gate@input, gate-input.

The above identifiers are called basic identifiers. The rules for these basic identifiers are often too restrictive to indicate signals. For example, if one wants to indicate an active low signal such as an active low RESET, one cannot call it /RESET. In order to overcome these limitations, there are a set of extended identifier rules which allow identifiers with any sequence of characters.

An extended identifier is enclosed by the backslash, \, character. An extended identifier is case sensitive. An extended identifier is different from reserved words (keywords) or any basic

identifier (e.g. the identifier \identity\ is allowed) Inside the two backslashes one can use any character in any order, except that a

backslash as part of an extended identifier must be indicated by an additional backslash. As an example, to use the identifier BUS:\data, one writes: \BUS:\data\ Extended identifiers are allowed in the VHDL-93 version but not in VHDL-87

Some examples of legal identifiers are:

Input, \Input\, \input#1\, \Rst\\as\

b.

b. Keywords (Reserved words)

Certain identifiers are used by the system as keywords for special use such as specific constructs. These keywords cannot be used as identifiers for signals or objects we define. We have seen several of these reserved words already such as in, out, or, and, port, map, end, etc. Keywords are often printed in boldface, as is done in this tutorial. For a list of all the keywords click on complete keyword list. Extended identifiers can make use of keywords since these are considered different words (e.g. the extended identifier \end\ is allowed.

c.

c.

Numbers

The default number representation is the decimal system. VHDL allows integer literals and real literals. Integer literals consist of whole numbers without a decimal point, while real literals always include a decimal point. Exponential notation is allowed using the letter E or e. For integer literals the exponent must always be positive. Examples are:

Integer literals: 12

10 256E3 12e+6

Real literals: 1.2 256.24 3.14E-2

The number 12 is a combination of a negation operator and an integer literal.

To express a number in a base different from the base 10, one uses the following convention: base#number#. A few examples follow.

Base 2: 2#10010# (representing the decimal number 18) Base 16: 16#12# Base 8: 8#22#

Base 2: 2#11101# (representing the decimal number 29) Base 16: 16#1D# Base 8: 8#35#

To make the readability of large numbers easier, one can insert underscores in the numbers as long as the underscore is not used at the beginning or the end.

2#1001_1101_1100_0010# 215_123

d.

d. Characters, Strings and Bit Strings

To use a character literal in a VHDL code, one puts it in a single quotation mark, as shown in the examples below:

a, B, ,

On the other hand, a string of characters are placed in double quotation marks as shown in the following examples:

This is a string, To use a double quotation mark inside a string, use two double quotation marks This is a String. Any printing character can be included inside a string. A bit-string represents a sequence of bit values. In order to indicate that this is a bit string, one places the B in front of the string: B1001. One can also use strings in the hexagonal or octal base by using the X or O specifiers, respectively. Some examples are:

Binary: B1100_1001, b1001011 Hexagonal: XC9, X4b Octal: O311, o113

Notice that in the hexadecimal system, each digit represents exactly 4 bits. As a result, the number b1001011 is not the same as X4b since the former has only 7 bits while the latter represents a sequence 8 bits. For the same reason, O113 (represents 9 bits) is not the same sequence as X4b (represents 8 bits).

5. Data Objects: Signals, Variables and Constants

A data object is created by an object declaration and has a value and type associated with it. An object can be a Constant, Variable, Signal or a File. Up to now we have seen signals that were used as input or output ports or internal nets. Signals can be considered wires in a schematic that can have a current value and future values, and that are a function of the signal assignment statements. On the other hand, Variables and Constants are used to model the behavior of a circuit and are used in processes, procedures and functions, similarly as they would be in a programming language. Following is a brief discussion of each class of objects.

Constant
A constant can have a single value of a given type and cannot be changed during the simulation. A constant is declared as follows,

constant list_of_name_of_constant: type [ := initial value] ; where the initial value is optional. Constants can be declared at the start of an architecture and can then be used anywhere within the architecture. Constants declared within a process can only be used inside that specific process.

constant constant constant constant

RISE_FALL_TME: time := 2 ns; DELAY1: time := 4 ns; RISE_TIME, FALL_TIME: time:= 1 ns; DATA_BUS: integer:= 16;

Variable
A variable can have a single value, as with a constant, but a variable can be updated using a variable assignment statement. The variable is updated without any delay as soon as the statement is executed. Variables must be declared inside a process (and are local to the process). The variable declaration is as follows:

variable list_of_variable_names: type [ := initial value] ; A few examples follow:

variable CNTR_BIT: bit :=0; variable VAR1: boolean :=FALSE; variable SUM: integer range 0 to 256 :=16; variable STS_BIT: bit_vector (7 downto 0);

The variable SUM, in the example above, is an integer that has a range from 0 to 256 with initial value of 16 at the start of the simulation. The fourth example defines a bit vector or 8 elements: STS_BIT(7), STS_BIT(6), STS_BIT(0).

A variable can be updated using a variable assignment statement such as

Variable_name := expression;

As soon as the expression is executed, the variable is updated without any delay.

Signal
Signals are declared outside the process using the following statement:

signal list_of_signal_names: type [ := initial value] ;

signal SUM, CARRY: std_logic; signal CLOCK: bit;

signal TRIGGER: integer :=0; signal DATA_BUS: bit_vector (0 to 7); signal VALUE: integer range 0 to 100;

Signals are updated when their signal assignment statement is executed, after a certain delay, as illustrated below,

SUM <= (A xor B) after 2 ns;

If no delay is specified, the signal will be updated after a delta delay. One can also specify multiple waveforms using multiple events as illustrated below,

signal wavefrm : std_logic; wavefrm <= 0, 1 after 5ns, 0 after 10ns, 1 after 20 ns;

It is important to understand the difference between variables and signals, particularly how it relates to when their value changes. A variable changes instantaneously when the variable assignment is executed. On the other hand, a signal changes a delay after the assignment expression is evaluated. If no delay is specified, the signal will change after a delta delay. This has important consequences for the updated values of variables and signals. Lets compare the two files in which a process is used to calculate the signal RESULT [7].

Example of a process using Variables

architecture VAR of EXAMPLE is signal TRIGGER, RESULT: integer := 0;

begin process variable variable1: integer :=1; variable variable2: integer :=2; variable variable3: integer :=3; begin wait on TRIGGER; variable1 := variable2; variable2 := variable1 + variable3; variable3 := variable2; RESULT <= variable1 + variable2 + variable3; end process; end VAR

Example of a process using Signals

architecture SIGN of EXAMPLE is signal TRIGGER, RESULT: integer := 0; signal signal1: integer :=1; signal signal2: integer :=2; signal signal3: integer :=3; begin process begin

wait on TRIGGER; signal1 <= signal2; signal2 <= signal1 + signal3; signal3 <= signal2; RESULT <= signal1 + signal2 + signal3;

end process; end SIGN;

In the first case, the variables variable1, variable2 and variable3 are computed sequentially and their values updated instantaneously after the TRIGGER signal arrives. Next, the RESULT, which is a signal, is computed using the new values of the variables and updated a time delta after TRIGGER arrives. This results in the following values (after a time TRIGGER): variable1 = 2, variable2 = 5 (=2+3), variable3= 5. Since RESULT is a signal it will be computed at the time TRIGGER and updated at the time TRIGGER + Delta. Its value will be RESULT=12. On the other hand, in the second example, the signals will be computed at the time TRIGGER. All of these signals are computed at the same time, using the old values of signal1, 2 and 3. All the signals will be updated at Delta time after the TRIGGER has arrived. Thus the signals will have these values: signal1= 2, signal2= 4 (=1+3), signal3=2 and RESULT=6.

6. Data types
Each data object has a type associated with it. The type defines the set of values that the object can have and the set of operations that are allowed on it. The notion of type is key to VHDL since it is a strongly typed language that requires each object to be of a certain type. In general one is not allowed to assign a value of one type to an object of another data type (e.g. assigning an integer to a bit type is not allowed). There are four classes of data types: scalar, composite, access and file types. The scalar types represent a single value and are ordered so that relational operations can be performed on them. The scalar type includes integer, real, and enumerated types of Boolean and Character. Examples of these will be given further on.

a. Data Types defined in the Standard Package VHDL has several predefined types in the standard package as shown in the table below. To use this package one has to include the following clause:

library std, work; use std.standard.all;

2.13 TEST BENCH GENERATION:

A test bench supplies the signals and dumps the outputs to simulate a VHDL design (module(s)). It invokes the design under test, generates the simulation input vectors, and implements the system tasks to view/format the results of the simulation. It is never synthesized so it can use all VHDL commands.

2.14 SYNTHESIS:

Verification and Synthesis can be done by means of softwares . As of 2007, the major commercial EDA vendors (Cadence, Mentor, Synopsys, Xilinx) have publicly pledged support for Systemverilog. Because Systemverilog embodies a large number of new language constructs and concepts, Systemverilog support varies by application, and from vendor to vendor.

In design synthesis, i.e. transformation of a hardware-design description into a gate-net list, Systemverilog is in its infancy. ASIC synthesis engineers who have worked with tools from all vendors regard only one tool, Synopsys Design Compiler, as sufficiently mature for Systemverilog front-end RTL-design. Other vendors have begun supporting Systemverilog for FPGA and ASIC synthesis, but none can match Synopsys's offering. Most design teams will not consider migrating to Systemverilog RTL-design until the entire (or most of) front-end tool suite (linters, formal verification, automated test structure generators) are similarly upgraded. In design verification, Systemverilog is widely used in HDL simulation, both at

block-design and (SoC) system-level. The 'big 3' EDA vendors (Cadence, Mentor,

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Synopsys) implement enough of the Systemverilog LRM in order for engineering teams to increase the level of abstraction over pure VHDL/Verilog environments. Although no vendor's product can yet claim support for the entire Systemverilog LRM, verification teams generally agree with the EDA-industrys claim that Systemverilog is ready for mainstream use. However, outside of ASIC simulation/verification, Systemverilog has yet to see widespread use. At $50,000 USD f or a single si mu l at i o n license, full Systemverilog capability is out of reach for the large number of small FPGA and startup projects. For those individuals willing to make do with limited Systemverilog capability, Aldec and Mentor offer affordably priced simulators to cater to the FPGA market.

Architecture of SD adders BINARY MULTIPLIER:

A Binary multiplier is an electronic hardware device used in digital electronics or a computer or other electronic device to perform rapid multiplication of two numbers in binary representation. It is built using binary adders. The rules for binary multiplication can be stated as follows If the multiplier digit is a 1, the multiplicand is simply copied down and represents the product. If the multiplier digit is a 0 the product is also 0. For designing a multiplier circuit we should have circuitry to provide or do the following three things: it should be capable identifying whether a bit is 0 or 1. It should be capable of shifting left partial products. It should be able to add all the partial products to give the products as sum of partial products. It should examine the sign bits. If they are alike, the sign of the product will be a positive, if the sign bits are opposite product will be negative. The sign bit of the product stored with above criteria should be displayed along with the product. From the above discussion we observe that it is not necessary to wait until all the partial products have been formed before summing them. In fact the addition of partial product can be carried out as soon as the partial product is formed.

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MULTIPLY ACCUMULATE CIRCUITS:

Multiplication followed by accumulation is a operation in many digital systems , particularly those highly interconnected like digital filters,neural networks, data quantisers, etc. One typical MAC(multiplyaccumulate) architecture is illustrated in figure. It consists of multiplying 2 values, then adding the result to the previously accumulated value, which must then be restored in the registers for future accumulations. Another feature of MAC circuit is that it must check for overflow, which might happen when the number of MAC operation is large . This design can be done using component because we have already design each of the units shown in figure. However since it is relatively simple circuit, it can also be designed directly. In any case the MAC circuit, as a whole, can be used as a component in application like digital filters and neural networks

ARCHITECTURE OF A RADIX 2^n MULTIPLIER:

The architecture of a radix 2^n multiplier is given in the Figure. This block diagram shows the multiplication of two numbers with four digits each. These numbers are denoted as V and U while the digit size was chosen as four bits. The reason for this will become apparent in the following sections. Each circle in the figure corresponds to a radix cell which is the heart of the design. Every radix cell has four digit inputs and

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two digit outputs. The input digits are also fed through the corresponding cells.The dots in the figure represent latches for pipelining. Every dot consists of four latches. The ellipses represent adders which are included to calculate the higher order bits. They do not fit the regularity of the design as they are used to terminate the design at the boundary. The outputs are again in terms of four bit digits and are shown by Ws. The 1s denote the clock period at which the data appear.

BOOTH MULTIPLIER:
The decision to use a Radix-4 modified Booth algorithm rather than Radix-2 Booth algorithm is that in Radix-4, the number of partial products is reduced to n/2. Though Wallace Tree structure multipliers

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could be used but in this format, the multiplier array becomes very large and requires large numbers of logic gates and interconnecting wires which makes the chip design large and slows down the operating speed.

Booth Multiplication Booth Multiplication Algorithm for radix 2:

Booth algorithm gives a procedure for multiplying binary integers in signed 2s complement representation. I will illustrate the booth algorithm with the following example: : Making the Booth table. From the two numbers, pick the number with the smallest difference between a series of consecutive numbers, and make it a multiplier. i.e., 0010 -- From 0 to 0 no change, 0 to 1 one change, 1 to 0 another change ,so there are two changes on this one 1100 -- From 1 to 1 no change, 1 to 0 one change, 0 to 0 no change, so there is only one change on this one. Therefore, multiplication of 2 x ( 4), where 2 Let Y = 0010 (multiplicand) Take the 2s complement of Y and call it Y Y = 1110 III. Load the X value in the table. IV. Load 0 for X-1 value it should be the previous first least significant bit of X V. Load 0 in U and V rows which will have the product of X and Y at the end of operation. VI. Make four rows for each cycle; this is because we are multiplying four bits numbers.

Booth Algorithm:
Booth algorithm requires examination of the multiplier bits, and shifting of the partial product. Prior to the shifting, the multiplicand may be added to partial product, subtracted from the partial product, or left

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unchanged according to the following rules: Look at the first least significant bits of the multiplier X, and the previous least significant bits of the multiplier X - 1. I 0 0 Shift only

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Booth multiplication algorithm for radix 4:

One of the solutions of realizing high speed multipliers is to enhance parallelism which helps to decrease the number of subsequent calculation stages. The original version of the Booth algorithm (Radix-2) had two drawbacks. They are: (i) The number of addsubtract operations and the number of shift operations becomes variable and becomes inconvenient in designing parallel multipliers. (ii) The algorithm becomes inefficient when there are isolated 1s. These problems are overcome by using modified Radix4 Booth algorithm which scan strings of three bits with the algorithm given below: 1) Extend the sign bit 1 position if necessary to ensure that n is even. 2) Append a 0 to the right of the LSB of the multiplier. 3) According to the value of each vector , each Partial Product will he 0, +y , -y, +2y or -2y. The negative values of y are made by taking the 2s complement and in this paper Carry-look-ahead (CLA) fast adders are used. The multiplication of y is done by shifting y by one bit to the left. Thus, in any case, in designing a n-bit parallel multipliers, only n/2 partial products are generated.

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SIMUTATION WAVE FORMS WITH EXPLANATION& SCHEMATICS:

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CONCLUSION

The project has been successfully designed and tested. It has been developed by integrating features of all the hardware components used. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. Secondly, using highly advanced ICs and with the help of growing technology the project has been successfully implemented. Finally we conclude that VLSI SYSTEM DESIGNING is an emerging field and there is a huge scope for research and development

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BIBLIOGRAPHY

References on the Web: www.national.com www.atmel.com www.microsoftsearch.com www.geocities.com www.alldatasheets.com www.AVR.com www.AVRfreaks.net www.AVRdesign.com www.microcontrollershop.com www.ultrasonicdirectory.com AVR Micro Controller Steven F. Barrett, Daniel J.Pack

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