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HW/SW Codesign w/ FPGAs

EDK

ECE 495/595

EDK The EDK tutorials provided by Srikanth show a path to completion for HelloWorld and a pushbutton, interrupt-driven custom peripherial application. These lecture slides provide a broader view of EDK to help you understand what is going on under the hood, and to understand the simplications that EDK provides. Ive drawn these notes partially from: http://www.xilinx.com/ise/embedded/edk92i_docs/edk_ctt.pdf EDK builds on top of ISE. XPS is used primarily for embedded processor hardware system development. Conguration of the microprocessor, peripherals, and the interconnection of these components (using the PLB) takes place in XPS. BSB is a wizard that quickly and efciently establishes a working design, which you can then customize.

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs XPS

EDK

ECE 495/595

Once a project is created The Project tab in the Project Information Area lists the les that were created. MHS, MSS, UCF, iMPACT command les, Implementation Option les, Bitgen Option les.

The Applications tab lists all software applications option settings, header les and source les -- you create and add a software application project. The xparameters.h le contains the system address map and is an integral part of the Board Support Package (BSP).

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs XPS

EDK

ECE 495/595

The IP Catalog tab lists all EDK IP cores and any custom IP cores you created. Right-click to add IP to the project, or view the data sheet.

Added Multi-channel memory controller

In System Assembly View, you can view and congure system block elements. Bus Interfaces shows PLB bus connection architecture -- hollow dot means unconnected. Ports gives a listing of the VHDL ports dened for the IP. Addresses gives the base address and size parameters associated with the IPs memory and/or ports. ECE UNM 3 (3/3/10)

HW/SW Codesign w/ FPGAs XPS

EDK

ECE 495/595

Right clicking and choosing Congure IP provides a GUI interface to the IPs conguration parameters.

The VHDL parameter name, e.g., C_BAUDRATE, is given when the mouse is placed over the parameter.

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs XPS

EDK

ECE 495/595

Directories created: _ _xps/ Contains intermediate les generated by XPS and other tools for internal project management. You will not use this directory. data/ Contains the user constraints le (UCF). etc/ Contains les that capture the options used to run various tools. pcores/ Used for including custom hardware peripherals. Files created: system.xmp This is the top-level project design le -- graphically displayed in XPS. system.mhs The system microprocessor hardware specication, or MHS le, captures textually the system elements, their parameters, and connectivity. system.mss The system microprocessor software specication, or MSS le. ECE UNM 5 (3/3/10)

HW/SW Codesign w/ FPGAs

EDK

ECE 495/595

Create and Import Peripheral (CIP) Wizard The PLB bus is a complicated structure because it must support many types of peripherials, each potentially operating in different modes, e.g., as master or slave. The wizard allows you to create four types of PLB v4.6 peripherals using predened IP interface (IPIF) libraries. PLB v4.6 Slave for single data beat transfer PLB v4.6 Slave for burst data transfer PLB v4.6 Master for single data beat transfer PLB v4.6 Master for burst data transfer The documents in $XILINX_EDK/doc/usenglish/, e.g., mg_ug.pdf and sp026.pdf have additional information on the PLB v4.6 interface. Once you have run the CIP wizard, EDK generates a PLB peripheral. EDK uses a PLB slave and burst peripheral to implement common functionality among various processor peripherals.

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs

EDK

ECE 495/595

Create and Import Peripheral (CIP) Wizard The PLB slave and burst peripherals are highly parameterizable interfaces. They give you a set of simplied bus protocols in the form of IP Interconnect (IPIC), which is easier to work with than working with the PLB bus protocols. The Slave Attachment implements the protocol and timing translation between the PLB Bus and the IPIC. PLBV46 Slave Burst SPBL_Clk SPBL_Rst PLB Bus Slave Attachment Address Cnt/BE Generation Address Decode Write Buf FIFO IPIC User IP IP Status Reply Design Rd/Wr Qualiers CS Bus Burst Read CE Bus Write CE Bus Write Data Bus Read Data Bus

PLB Requests and Qualiers Slave Reply

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs

EDK

ECE 495/595

Create and Import Peripheral (CIP) Wizard The CIP wizard created two template les: pcores/switch_debouncer_v1_00_a/hdl/vhdl/switch_debouncer.vhd pcores/switch_debouncer_v1_00_a/hdl/vhdl/user_logic.vhd The user_logic le makes the connection to the PLB v4.6 bus via the PLB slave/burst cores congured in switch_debouncer.vhd The user_logic le is equivalent to the User IP Design block above, while the switch_debouncer is equivalent to the PLBV46 Slave Burst block. User Peripheral IPIF switch_debouncer.vhd Slave Attach Master Attach Interrupt Ctrl Addr Decode MUX Write FIFO Read FIFO DMA user_logic.vhd PLBv46 Bus ECE UNM IPIC
Custom Functionality

(3/3/10)

HW/SW Codesign w/ FPGAs

EDK

ECE 495/595

Create and Import Peripheral (CIP) Wizard The templates represent CoreConnect-compliant structures. Therefore, you do not need to add any additional logic to these les. Most times you will want to add logic, as you did in EDK tutorial 2, in which case you need to re-run the CIP wizard to import your changes. This re-generates the EDK interface les (.mpd and .pao les).

ECE UNM

(3/3/10)

HW/SW Codesign w/ FPGAs Processor Local Bus (PLB)

EDK

ECE 495/595

ECE UNM

10

(3/3/10)

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