comp_config::= component ID [is]

for all | LABELID : COMPID [generic ( {ID : TYPEID [:= expr];} );]
(use entity [LIBID.]ENTITYID [( ARCHID )] [port ({ID : in | out | inout TYPEID [:= expr];});
[[generic map ( {GENID => expr ,} )] end component [COMPID];
port map ({PORTID => SIGID | expr ,})]; [impure] function ID
[for ARCHID [( {[constant | variable | signal] ID :
[{block_config | comp_config}]
VHDL QUICK end for;]
in | out | inout TYPEID [:= expr];})]
return TYPEID [is
end for;) |
REFERENCE CARD (use configuration [LIBID.]CONFID
begin
{sequential_statement}
[[generic map ({GENID => expr ,})]
REVISION 1.1 port map ({PORTID => SIGID | expr,})];)
end [function] ID];
end for; procedure ID[({[constant | variable | signal] ID :
() Grouping [] Optional in | out | inout TYPEID [:= expr];})]
{} Repeated | Alternative 2. DECLARATIONS [is begin
bold As is CAPS User Identifier [{sequential_statement}]
italic VHDL-1993 end [procedure] ID];
2.1. TYPE DECLARATIONS
for LABELID | others | all : COMPID use
1. LIBRARY UNITS type ID is ( {ID,} ); (entity [LIBID.]ENTITYID [( ARCHID )]) |
type ID is range number downto | to number; (configuration [LIBID.]CONFID)
[{use_clause}] [[generic map ( {GENID => expr,} )]
entity ID is type ID is array ( {range | TYPEID ,})
port map ( {PORTID => SIGID | expr,} )];
[generic ({ID : TYPEID [:= expr];});] of TYPEID | SUBTYPID;
[port ({ID : in | out | inout TYPEID [:= expr];});] type ID is record 3. EXPRESSIONS
[{declaration}] {ID : TYPEID;}
[begin end record; expression ::=
{parallel_statement}] type ID is access TYPEID; (relation and relation) |
end [entity] ENTITYID; (relation or relation) |
type ID is file of TYPEID; (relation xor relation)
[{use_clause}]
architecture ID of ENTITYID is subtype ID is SCALARTYPID range range; relation ::= shexpr [relop shexpr]
[{declaration}] subtype ID is ARRAYTYPID( {range,}) shexpr ::= sexpr [shop sexpr]
begin subtype ID is RESOLVFCTID TYPEID;
[{parallel_statement}] sexpr ::= [+|-] term {addop term}
end [architecture] ARCHID; range ::= term ::= factor {mulop factor}
(integer | ENUMID to | downto
[{use_clause}] integer | ENUMID) | (OBJID’[reverse_]range) | factor ::=
package ID is (TYPEID range <>) (prim [** prim]) | (abs prim) | (not prim)
[{declaration}] prim ::=
end [package] PACKID; 2.2. OTHER DECLARATIONS literal | OBJID | OBJID’ATTRID | OBJID({expr,})
[{use_clause}] constant ID : TYPEID := expr; | OBJID(range) | ({[choice [{| choice}] =>] expr,})
package body ID is | FCTID({[PARID =>] expr,}) | TYPEID’(expr) |
[{declaration}] [shared] variable ID : TYPEID [:= expr]; TYPEID(expr) | new TYPEID[‘(expr)] | ( expr )
end [package body] PACKID; signal ID : TYPEID [:= expr]; choice ::= sexpr | range | RECFID | others
[{use_clause}] file ID : TYPEID (is in | out string;) |
configuration ID of ENTITYID is (open read_mode | write_mode 3.1. OPERATORS, INCREASING PRECEDENCE
for ARCHID | append_mode is string;) logop and | or | xor
[{block_config | comp_config}] relop = | /= | < | <= | > | =>
alias ID : TYPEID is OBJID;
end for; shop sll | srl | sla | sra | rol | ror
end [configuration] CONFID; attribute ID : TYPEID;
addop +|-|&
use_clause::= attribute ATTRID of OBJID | others | all : class mulop * | / | mod | rem
library ID; is expr; miscop ** | abs | not
[{use LIBID.PKGID.all;}] class ::=
block_config::= entity | architecture | configuration |
for LABELID procedure | function | package | type |
[{block_config | comp_config}] subtype | constant | signal | variable | © 1995 Qualis Design Corporation. Permission to
end for; component | label reproduce and distribute strictly verbatim copies of this
document in whole is hereby granted.
See reverse side for additional information.
© 1995 Qualis Design Corporation © 1995 Qualis Design Corporation
4. SEQUENTIAL STATEMENTS [LABEL:] [postponed] assert expr SIGID’transaction[(expr)]
[report string] [severity note | warning | Toggles if signal active
wait [on {SIGID,}] [until expr] [for time]; error | failure]; SIGID’event Event on signal ?
assert expr [LABEL:] [postponed] SIGID <= SIGID’active Activity on signal ?
[report string] [severity note | warning | [transport] | [reject TIME inertial] SIGID’last_event Time since last event
error | failure]; [{{expr [after time]} | unaffected when expr SIGID’last_active Time since last active
else}] {expr [after time]} | unaffected; SIGID’last_value Value before last event
report string SIGID’driving Active driver predicate
[severity note | warning | error | [LABEL:] [postponed] with expr select SIGID’driving_value Value of driver
failure]; SIGID <= [transport] | [reject TIME inertial] OBJID’simple_name Name of object
SIGID <= [transport] | [reject TIME inertial] {{expr [after time]} | OBJID’instance_name Pathname of object
{expr [after time]}; unaffected when choice [{| choice}]}; OBJID’path_name Pathname to object
VARID := expr; LABEL: COMPID
[[generic map ( {GENID => expr,} )] 7. PREDEFINED TYPES
PROCEDUREID[({[PARID =>] expr,})]; port map ( {PORTID => SIGID,} )];
[LABEL:] if expr then BOOLEAN True or false
LABEL: entity [LIBID.]ENTITYID [(ARCHID)]
{sequential_statement} INTEGER 32 or 64 bits
[[generic map ( {GENID => expr,} )]
[{elsif expr then NATURAL Integers >= 0
port map ( {PORTID => SIGID,} )];
{sequential_statement}}] POSITIVE Integers > 0
[else LABEL: configuration [LIBID.]CONFID REAL Floating-point
{sequential_statement}] [[generic map ( {GENID => expr,} )] BIT ‘0’, ‘1’
end if [LABEL]; port map ( {PORTID => SIGID,} )]; BIT_VECTOR(NATURAL) Array of bits
LABEL: if expr generate CHARACTER 7-bit ASCII
[LABEL:] case expr is
[{parallel_statement}] STRING(POSITIVE) Array of characters
{when choice [{| choice}] =>
end generate [LABEL]; TIME hr, min, sec, ms,
{sequential_statement}}
us, ns, ps, fs
end case [LABEL]; LABEL: for ID in range generate DELAY_LENGTH Time => 0
[LABEL:] [while expr] loop [{parallel_statement}]
{sequential_statement} end generate [LABEL]; 8. PREDEFINED FUNCTIONS
end loop [LABEL];
6. PREDEFINED ATTRIBUTES NOW Returns current simulation time
[LABEL:] for ID in range loop
DEALLOCATE(ACCESSTYPOBJ)
{sequential_statement} TYPID’base Base type Deallocate dynamic object
end loop [LABEL]; TYPID’left Left bound value FILE_OPEN([status], FILEID, string, mode)
next [LOOPLBL] [when expr]; TYPID’right Right-bound value Open file
TYPID’high Upper-bound value FILE_CLOSE(FILEID) Close file
exit [LOOPLBL] [when expr];
TYPID’low Lower-bound value
return [expression]; TYPID’pos(expr) Position within type
TYPID’val(expr) Value at position
9. LEXICAL ELEMENTS
null;
TYPID’succ(expr) Next value in order Identifier ::= letter { [underline] alphanumeric }
5. PARALLEL STATEMENTS TYPID’prec(expr) Previous value in order
decimal literal ::= integer [. integer] [E[+|-] integer]
TYPID’leftof(expr) Value to the left in order
[LABEL:] block [is] TYPID’rightof(expr) Value to the right in order based literal ::=
[generic ( {ID : TYPEID;} ); TYPID’ascending Ascending type predicate integer # hexint [. hexint] # [E[+|-] integer]
[generic map ( {GENID => expr,} );]] TYPID’image(expr) String image of value bit string literal ::=B|O|X “ hexint “
[port ( {ID : in | out | inout TYPEID } ); TYPID’value(string) Value of string image
[port map ( {PORTID => SIGID | expr,} )];] comment ::= -- comment text
ARYID’left[(expr)] Left-bound of [nth] index
[{declaration}] ARYID’right[(expr)] Right-bound of [nth] index
begin ARYID’high[(expr)] Upper-bound of [nth] index
[{parallel_statement}] ARYID’low[(expr)] Lower-bound of [nth] index
end block [LABEL]; © 1995 Qualis Design Corporation. Permission to
ARYID’range[(expr)] ‘left down/to ‘right
reproduce and distribute strictly verbatim copies of this
[LABEL:] [postponed] process [( {SIGID,} )] ARYID’reverse_range[(expr)] ‘right down/to ‘left
document in whole is hereby granted.
[{declaration}] ARYID’length[(expr)] Length of [nth] dimension
begin ARYID’ascending[(expr)] ‘right >= ‘left ? Qualis Design Corporation
[{sequential_statement}] SIGID’delayed[(expr)] Delayed copy of signal Beaverton, OR USA
end [postponed] process [LABEL]; SIGID’stable[(expr)] Signals event on signal Phone: +1-503-531-0377 FAX: +1-503-629-5525
SIGID’quiet[(expr)] Signals activity on signal E-mail: info@qualis.com
[LBL:] [postponed] PROCID({[PARID =>] expr,});
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© 1995 Qualis Design Corporation © 1995 Qualis Design Corporation