Abstract The neuromorphic paradigm is attractive for

nanoscale computation because of its massive parallelism,

potential scalability, and inherent defect-, fault-, and failure-
tolerance. We show how to implement timing-based learning
laws, such as spike-timing-dependent plasticity (STDP), in
simple, memristive nanodevices, such as those constructed from
certain metal oxides. Such nano-scale ~synapses can be
combined with CMOS ~neurons to create neuromorphic
hardware several orders of magnitude denser than is possible in
conventional CMOS. The key ideas are: (1) to factor out two
synaptic state variables to pre- and post-synaptic neurons; and
(2) to separate computational communication from learning by
time-division multiplexing of pulse-width-modulated signals
through synapses. This approach offers the advantages of: better
control over power dissipation; fewer constraints on the design of
memristive materials used for nanoscale synapses; greater
freedom in learning algorithms since the synaptic learning
dynamics can be dynamically turned on or off (e.g. by attentional
priming mechanisms communicated extra-synaptically); greater
control over the precise form and timing of the STDP equations;
the ability to implement a variety of other learning laws besides
STDP; better circuit diversity since the approach allows different
learning laws to be implemented in different areas of a single
chip using the same memristive material for all synapses.
Index 1erms- adaptive systems, analog memories, learning
systems, neural network hardware, nonlinear circuits
I. INTRODUCTION
Nano-scale device 'crumminess (deIects, Iaults, Iailures,
variability, driIt.) creates substantial scalability and
robustness challenges Ior logic chips at the trillion gate level
and beyond. Several researchers have proposed deIect-Iinding
and compilation to handle deIects |1-5|, and encoded circuits
to detect and/or correct Iault- and Iailure-induced errors at
runtime |6-8|, but it is not clear that such strategies can ever
be economical Ior mass-produced parts. Much oI the
diIIiculty comes Irom the inherent Iragility oI Boolean logic.
Although reasonably eIIicient error-detecting encoding
schemes are known Ior special cases (e.g. group operations
|9|), it appears that general Boolean logic cannot be eIIiciently
protected |10, 11|.
Adaptive, neuromorphic circuits potentially side-step many
oI the robustness issues since, in principle anyway, deIects
can be completely ignored (the system will be trained around
them), Iaults will not signiIicantly perturb the computation,
and runtime Iailures will selI-heal through ongoing
organizational processes. They also have the potential Ior
creating autonomous, intelligent machines that can adaptively
interact with uncertain and changing environments, abilities
that have eluded digital computers. Although there are many
stumbling blocks to achieving that vision, a primary problem
has been the lack oI a small, cheap circuit that can emulate the
essential properties oI a synapse. Brains require synapses, and
lots oI them (an estimated 10
14
in the human brain), but only
about 1/10000 as many neurons, so synapse circuit design
dominates the implementation problem. Memristive
nanodevices may Iill the role oI a solid-state analog oI
biological synapses; they are about three orders oI magnitude
smaller than a prominent CMOS design |12|, opening the
possibility oI economical, neuromorphic computers.
In this paper we show how to implement a neuromorphic
learning law known as spike-timing-dependent plasticitv
(STDP) |13| in memristive nanodevices |14-16|. A
straightIorward implementation oI STDP requires three
dynamical state variables, which could be diIIicult to engineer
in nano-scale devices, but some Iactoring and redistribution oI
the dynamics allows an implementation with nanodevices
dominated by only a single state variable. This reduces the
complexity oI materials design, provides a mechanism Ior
modulating learning, reduces power consumption, and allows
Ior more Ilexibility in learning algorithms.
To place this in context, Fig. 1 sketches a hybrid nano /
CMOS neuromorphic architecture we are developing to
emulate cortical structures. Neurons (gray boxes) are
implemented in conventional CMOS; axons and dendrites
(blue) in multiple layers oI nanowires imprinted on top oI the
silicon |5|; and synapses (yellow) in memristive (dynamical)
junctions Iormed between selected adjacent layers oI
imprinted nanowires. CMOS neurons connect to the
nanowires through metallic 'pins (black disks) on the top
surIace oI the silicon. Nano 'vias (blue cylinders) allow
neurons to connect to nanowires at several levels. Neurons in
diIIerent cortical layers are represented by diIIerent shades oI
gray; we thus emulate the cortical layering oI neurons by
Greg S. Snider
InIormation and Quantum Systems Laboratory
Hewlett-Packard Laboratories
Palo Alto, CA USA
snider.greghp.com
Spike-Timing-Dependent Learning in
Memristive Nanodevices
85
978-1-4244-2553-2/08/$20.00 c 2008 IEEE
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interleaving the layers in CMOS. Interconnections between
and within cortical layers are implemented with multiple
levels oI imprinted nanowires. Nanowires are rotated slightly
relative to neuron edges to allow long distance connections.
Synaptic nanodevices are created wherever orthogonal
nanowires, separated by memristive material, cross each other.
II. MEMRISTIVE NANODEVICES
A memristive device is a two-terminal electrical component
that is primarily resistive in nature, but whose conductance
(which is generally nonlinear in voltage) can be dynamically
altered by the application oI voltage across or current through
the device. Some metal oxides have been shown to possess
memristive behavior |16, 17|. Here we will consider a two-
terminal, time-invariant, voltage-controlled memristive device
which, by deIinition |14|, obeys equations oI the Iorm:
where w is one or more physical state variables, i is current
through the device, and v is the voltage drop across the device.
The Iunction g represents the device's conductance. Such
devices typically show hysteresis and multi-state behavior
when driven by complex waveIorms (Fig. 2) and their
voltage-current plots always pass through the origin; such
behavior, particularly hysteresis, has been widely reported in
nano-scale devices.
A memristive device is thus an analog memory, where the
analog value is stored in internal state variables, w, and read
out by interrogating the device's conductance, g. The
diIIerential equation (1) describing the dynamical behavior oI
such devices is oIten extremely nonlinear in voltage, with
negligible conductance changes occurring at low voltages, and
very rapid conductance changes occurring at larger voltages.
This can be seen in the curves on the right side oI Iigure 2:
voltages below about 1 volt induce no observable change,
while above 1 volt, device conductance changes rapidly. That
property is exploited here.
v v w g i
v w f
dt
dw
) , (
) , (

(1)
(2)
Figure 1. Nano / CMOS architecture Ior laminar, cortical circuits (leIt). Neurons are implemented in CMOS (gray), axons and
dendrites in nanowires (blue). Synapses are implemented at the junctions oI crossing wires separated by memristive material
(yellow). Top view (right) shows how slight rotation oI nanowires allows neurons to communicate via synapses to a neighborhood
oI other neurons. The small size oI memristive nanodevices allows Ior a large ratio oI synapses to neurons necessary Ior
neuromorphic computation; densities greater than 10
10
devices / cm
2
have already been achieved.
-4.00E-05
-3.00E-05
-2.00E-05
-1.00E-05
0.00E+00
1.00E-05
2.00E-05
3.00E-05
4.00E-05
5.00E-05
6.00E-05
-2.00E+00 -1.50E+00 -1.00E+00 -5.00E-01 0.00E+00 5.00E-01 1.00E+00 1.50E+00 2.00E+00
4-wirevoItage
c
u
r
r
e
n
t
Figure 2. Dynamical behavior oI nanojunctions Irom experiments.
Current-voltage curves are numbered sequentially and oIIset vertically
Ior clarity. Positive voltage sweeps (1 through 5) are hysteresis loops oI
increasing conductivity; negative voltage sweeps (6, 7, 8) are hysteresis
loops oI decreasing conductivity. Data courtesy oI Duncan Stewart.
memristive
junction
nanowire
nanowire
8
1
2
3
1
5
Z
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III. SPIKE-TIMING-DEPENDENT PLASTICITY
Spike-timing-dependent plasticity (STDP) is a learning
mechanism postulated to exist, with some experimental
conIirmation, in some synapses oI mammalian brains |13|.
STDP causes synaptic eIIicacy or 'weight to be slightly
altered as a Iunction oI the relative spike times oI pre-synaptic
('pre) and post-synaptic ('post) neurons: iI 'pre preceeds
'post, the synapse undergoes long-term potentiation
(increase in eIIicacy) abbreviated as 'LTP, while 'pre
Iollowing 'post induces long-term depression (decrease in
eIIicacy) or 'LTD. The degree oI change in eIIicacy in either
case is a Iunction oI the elapsed time between the 'pre and
'post spikes, with larger changes induced by shorter time
intervals. Figure 3 shows experimental evidence Ior STDP,
and a representative mathematical model.
Note that the curves Ior potentiation and depression can be
approximated by decaying exponential Iunctions, although the
Iunctions are generally asymmetric, with depression oIten
(though not always) associated with a longer exponential time
constant.
IV. IMPLEMENTING STDP
Communication between CMOS neurons is done through
nano-scale synapses using time-division multiplexing
('TDM), creating multiple logical communication channels
('timeslots) between the presynaptic neuron ('pre) and
postsynaptic neuron ('post). In this initial description we`ll
consider Iive timeslots or channels (and later discuss reducing
this): one timeslot Ior computational communication
('COMM) Irom pre to post; two timeslots Ior communication
oI LTP timing inIormation Irom pre to post; and two timeslots
Ior communicating LTD timing inIormation Irom post to pre.
InIormation in the timing timeslots is encoded using pulse-
width modulation ('PWM). The COMM timeslot is
unidirectional, with inIormation Ilowing Irom pre to post, but
alternatively one could make the timeslot bidirectional. It is
also possible to add a second unidirectional COMM timeslot
to allow communication Irom post to pre.
When a neuron 'spikes, two timing circuits within the
neuron are initialized, one Ior LTD timing and one Ior LTP
timing. These timing circuits implement the exponential decay
curves characteristic oI STDP models such as those shown in
Figure 3. The states oI the timing circuits in a given neuron
are communicated via synapses (using PWM within
appropriate timeslots) to the other neurons connected to it: the
LTP timing state is sent Iorward through synapses connected
to the neuron output, and the LTD timing state is sent
backward through synapses connected the neuron inputs. A
neuron`s spike interacts with the received LTP and LTD
signals to induce desired changes (learning) in the
conductances oI all connected synapses.
We`ll now describe the mechanisms in more detail. Fig. 4
shows schematic symbols Ior neurons and synapses which
will be used in the rest oI the paper.
For simplicity, neurons are assumed to have an excitatory
and an inhibitory input and a single output. The synapse is a
two-terminal, memristive device. The 'bar on the leIt side oI
the symbol denotes that the device is 'polarized, meaning
that the sign oI the voltage drop across the device determines
whether the conductance oI the device is increased or
decreased according to equation (1). We adopt the convention
that voltage drops across the device are measured with respect
to the right terminal oI the device, opposite the 'bar, so that a
positive voltage drop corresponds to the bar having a more
positive voltage than the other terminal, and a negative
voltage drop corresponds to the bar having a more negative
voltage. We also assume that positive voltage drops induce
increases in device conductance, while negative voltage drops
induce decreases in device conductance.
Fig. 5 shows an example neuromorphic network with six
neurons and nine synapses. A neuron input is a 'virtual
ground that sums all input currents Ilowing into it. A neuron
Figure 3. Spike-timing-dependent plasticity. The horizontal axis
represents the diIIerence between 'post and 'pre spike times. The
vertical axis represents the change in synaptic eIIicacy. Experimental data
points (diamonds) and STDP Iunctions Iit to the data (curves). Depression
oI synaptic eIIicacy, LTD, (leIt curve) occurs when the 'pre spike
Iollows the 'post spike; potentiation, LTP, (right curve) occurs when
'post Iollows 'pre. Data Irom Bi and Poo (2001).
0 -10 -80 10 80
0
-10
10
80
L
syrapl|c
ell|cacy
'posl sp||e l|re - 'pre sp||e l|re
(rsec)
Figure 4. Schematic symbols Ior neurons and synapses.
exc|lalory |rpul
|rr|o|lalory |rpul
Neuror
3yrapse
oulpul
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output is nominally at zero volts, but occasionally 'spikes
with a non-zero voltage, causing a voltage drop across all
synapses driven by that output. The total current received by a
neuron input depends on the conductances, g, and the voltage
drops across the synapses connected to that input, as
determined by Ohm`s law. II we represent the voltages driven
by the pre neurons by the vector v, the input currents to the
post neurons by the vector c, and the conductances oI the
synapses by the matrix G, the above Iully-connected, bipartite
network implements the mathematical operation c Gv. This
operation is a Iundamental mechanism used by this class oI
networks Ior implementing part oI the network`s computation.
Fig. 6 shows a representative curve Ior the diIIerential
equation (1) Ior one value oI conductance, g, in a memristive
device. The curve is 'sinh-like, meaning that it can be
approximated by an equation oI the Iorm dg/dt A sinh (B v).
Note that small voltages induce very little change in device
conductance, while larger voltages induce much greater
changesthe diIIerence between the rate oI change Ior a
voltage, V, and a second voltage, 2 V, can be several orders oI
magnitude. Also note that positive voltages induce positive
changes, while negative voltages induce negative changes.
Memristive devices have maximum and minimum
conductances, and this curve Ilattens out as those extrema are
approached.
The knee oI the curve, labeled 'threshold, is a subjectively
deIined point where the curve appears to begin a rapid change
in slope. Strictly speaking, this is not a true threshold, but it is
a convenient reIerence point oIten used in nonlinear
electronics (Ior example, silicon diodes are oIten said to have
a 'threshold oI about 0.7 volts). As is apparent in Fig. 6, the
memristive devices we are considering have both positive and
negative thresholds.
Fig. 7 shows time-division multiplexing (TDM) oI signals
through synapses. Signaling through synapses is done by
multiplexing logical channels in time. The logical channels are
called 'timeslots and indexed starting Irom 0. Voltage signals
transmitted within a timeslot are always sub-threshold to
minimize conductance changes due to the signaling. In Fig. 7,
Iive timeslots are used. Timeslots are grouped in time to Iorm
Irames as shown. Timeslot 0, also called 'COMM, is used
Ior communication oI spikes Irom pre to post in order to
compute inner products or matrix products as described
previously. Timeslots 1 and 2, called 'LTP and 'LTP-, are
used to communicate LTP timing inIormation Irom pre to post
using pulse-width modulation (PWM) encoding. The LTP
and LTP- pulses have opposite polarity and approximately
equal durations within a Irame: this is done to minimize the
small conductance changes induced by the signalsin eIIect,
the LTP and LTP- pulses 'cancel each other out. Timeslots
3 and 4, called 'LTD and 'LTD-, are used to communicate
LTD timing inIormation Irom post to pre using PWM; they
also have opposite polarity and approximately equal duration
in order to cancel each other out.
The LTP- and LTD- timeslots are unidirectional, always
transmitting to a virtual ground at the destination neuron. The
LTP and LTD timeslots normally transmit to a virtual
ground, but when the destination neuron spikes, they transmit
a voltage oI opposite polarity, causing a super-threshold
voltage drop across the synapse. As we shall see later, this is
the principle mechanism Ior learning.
Fig. 8 shows pulse-width modulation (PWM) within a
timeslot. The bottom curve shows a decaying voltage in time.
The top Iigure shows how that curve is sampled and encoded
using PWM within a time-division multiplexed (TDM)
Iramework. The three consecutive sampled points oI the curve
'lrresro|d
Figure 6. . A representative curve Ior the diIIerential equation (1) Ior one
value oI conductance, g, in a memristive device.
v
dg
dl
(g, v)
Figure 5. A simple neuromorphic network.
Figure 7. Time-division multiplexing (TDM) oI signals through synapses.
lrare 0 lrare 1 lrare 2
l|re
l|re
l|res|ols
Frare
l|res|ol 0 l|res|ol 1
C0VV LTP LTP- LT0 LT0-
3erl oy 'pre reuror 3erl oy 'posl reuror
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are sent in timeslot 1 oI three consecutive Irames; the
amplitude oI the each sampled point is translated to a
proportional pulse width. All pulses within a timeslot have the
same, sub-threshold amplitude. Note that the pulses can be
signiIicantly narrower than the duration oI the timeslot in
which they are transmitted, even Ior the case oI a maximal
amplitude signal value.
Fig. 9 shows transmission oI LTD and LTP timing curves
through synapses. This Iigure shows the simultaneous
transmission oI an LTP signal Irom pre to post, and an LTD
signal Irom post to pre, through a synapse over three Irames.
Ideally these signals would not perturb synapse
conductanceimpossible to obtain Ior realistic Iorms oI
equation 1but we can come very close by doing the
Iollowing: (1) restricting pulse amplitudes to be sub-threshold,
thereby minimizing conductance changes (see Figure 6); (2)
Iollowing each LTP (LTD) pulse by an equal-width,
opposite polarity LTP- (LTD-) pulse to roughly cancel out any
small changes induced by the Iirst pulse. This will still leave a
very small jitter or 'noise in synapse conductance, but this
can be handled by higher-level network processes.
Fig. 10 shows another, slightly more abstract, view oI LTP
and LTD signal transmission. Whenever a neuron spikes, it
begins transmitting a decaying LTP signal on its output and a
decaying LTD signal on its input. Eventually both signals
decay to zero, so that a neuron that has been inactive Ior
awhile transmits no LTP or LTD signals at all. II a neuron
spikes beIore either or both signals have Iully decayed to zero,
the signals are reset to their initial signal values just as though
they had already gone to zero.
Note that neurons spike only within a Irame, and a spike
logically lasts Ior the entire Irame.
Fig. 11 shows how post spiking aIter pre spiking induces
LTP. The LTP signal sent by a pre neuron is normally
received by a 'virtual ground in the receiving timeslot oI the
post neuron. But when the post neuron spikes within a Irame,
the post LTP timeslot in that Irame is driven by a wide
negative pulse that combines to Iorm a super-threshold
voltage drop across the synapse oI duration equal to the width
on the LTP pulse in that timeslot. This induces an increase in
conductance, or LTP, that is approximately proportional to the
width oI the LTP signal pulse. This captures the essence oI
STDP: the amount oI synaptic conductance change is an
exponentially decreasing Iunction oI the time diIIerence
between the pre and post spike times. In this case, LTP occurs
when the post pulse Iollows the pre pulse, with a smaller
increase as the time interval between the pulses increases.
Figure 9. Transmission oI LTD and LTP timing curves through synapses.
arp||lude
LTP
LTP l|r|rg
l|res|ol:
l|re
LTP-
LT0
LT0-
LT0 l|r|rg
LT0
LTP
Figure 11. Post spiking aIter pre spiking induces LTP.
pre LTP
s|gra|
posl sp||e
vo|lage
across
syrapse
l|re
LTP
'lrresro|d
Figure 8. Pulse-width modulation (PWM) within a timeslot.
lrare
arp||lude
0 1 2 3 1 0 1 2 3 1 0 2 1
PwV s|gra| |r l|res|ol 1
l|re
s|gna| oelore
moou|ar|on
l|res|ol:
Figure 10. Another, slightly more abstract, view oI LTP and LTD signal
transmission.
'pre reuror 'posl reuror
lrarsr|ls LTP lrarsr|ls LT0
pre
sp||e
l|re
posl
sp||e
l|re
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Fig. 12 shows how pre spiking aIter post spiking induces
LTD. The LTD signal sent by a post neuron is normally
received by a 'virtual ground in the receiving timeslot oI the
pre neuron. But when the pre neuron spikes within a Irame,
the pre LTD timeslot in that Irame is driven by a wide
negative pulse that combines to Iorm a super-threshold
voltage drop across the synapse oI duration equal to the width
on the LTD pulse in that timeslot. This induces a decrease in
conductance, or LTD, that is approximately proportional to
the width oI the LTD signal pulse. Again, this captures the
essence oI STDP: the amount oI synaptic conductance change
is an exponentially decreasing Iunction oI the time diIIerence
between the pre and post spike times. In this case, LTD occurs
when the pre pulse Iollows the post pulse, with a smaller
increase as the time interval between the pulses increases.
Fig. 13 shows a block diagram oI a neuron. Global timing
signals are made available to all neurons since TDM requires
synchronization oI timeslots and Irames. It is estimated that
global timeslot clocking will be quite slow compared to digital
systems, perhaps on the order to 10 to 50 kHz, so that power
consumption due to CV
2
I losses in a clock distribution
network will be small (probably less than 1 W Ior a 2cm X
2cm CMOS chip). A designer is Iree to implement whatever
neuron processing they desire, so that is not described Iurther
(this paper deals only with communication and learning, and
is orthogonal to neuron algorithms). The LTD and LTP timing
circuits are triggered whenever the neuron processing module
indicates that the neuron has spikedthey initialize to
appropriate voltages which decay exponentially to implement
the STDP timing curves. The LTD and LTP circuits are also
responsible Ior PWM oI their timing signals. The input and
output TDM modules interIace to the neuron`s input and
output ports, sending and receiving inIormation in timeslots,
relaying computational communication to and Irom the neuron
processing module, and relaying LTP and LTD timing curves
out oI the neuron.
Fig. 14 shows block diagrams oI the output TDM and LTP
timing circuits. When a neuron spikes, the TDM multiplexer
circuit drives that spike (which we`ll assume to be a positive
pulse) in timeslot 0 on the output. The spike also closes a
switch which charges a capacitor, C
P
, to an initial value V
P
.
The switch is then opened and the capacitor slowly discharged
(with an exponential decay) through resistor R
P
. The product
oI C
P
and R
P
determines the time constant oI the decay and the
LTP timing curve. The voltage on the capacitor also drives a
PWM circuit which encodes that voltage as a pulse width.
That pulse, and its negative version, are driven in timeslots 1
(LTP) and 2 (LTP-) oI the output pad, respectively.
Normally timeslots 3 (LTD) and 4 (LTD-) are inputs
which the TDM connects to a (possibly virtual) ground. But
when the neuron spikes, a negative version oI the spike is sent
out on timeslot 3 (LTD) oI the output, potentially causing
LTD on the synapses connected to this neuron. This
mechanism is described in Figure 12.
Fig. 15 shows block diagrams oI the input TDM and LTD
timing circuits. When a neuron spikes, the spike closes a
switch which charges a capacitor, C
D
, to an initial value V
D
.
The switch is then opened and the capacitor slowly discharged
(with an exponential decay) through resistor R
D
. The product
oI C
D
and R
D
determines the time constant oI the decay and
the LTD timing curve. The voltage on the capacitor also
drives a PWM circuit which encodes that voltage as a pulse
width. That pulse, and its negative version, are driven in
timeslots 3 (LTD) and 4 (LTD-) oI the input pad,
respectively. Timeslot 2 (LTP-) is driven with a ground to
terminate the incoming LTP- signal; timeslot 1 (LTP) is
normally driven with a virtual ground Ior the incoming LTP
signal, but is driven with a negative pulse when the neuron
spikes in order to implement LTP as described in Figure 11.
Figure 12. Pre spiking aIter post spiking induces LTD.
posl LT0
s|gra|
pre sp||e
vo|lage
across
syrapse
l|re
LT0
'lrresro|d
Figure 13. Block diagram oI a neuron.
0|ooa| l|r|rg s|gra|s
(lrare, l|res|ol)
reuror
process|rg
|rpul
T0V
oulpul
T0V
LT0
l|r|rg
LTP
l|r|rg
sp|ke
|rr|o|lory |r
exc|lalory |r
oul
Figure 14. Output TDM and LTP Timing circuits.
vp
Cp Rp
PwV
T0V
VuX
lrare, l|res|ol
sp||e lror
reuror process|rg
reuror
oul
0
1
2
3
1
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Incoming timeslots 0 and 1 contain weighted input pulses
(sub-threshold) which are extracted and sent to the neuron
processing module.
Fig. 16 shows a possible implementation Ior a neuron input.
A virtual ground terminates an incoming timeslot 0 (through a
switch in the TDM circuitry), sums all input currents, and
converts the sum to a voltage suitable Ior Iurther processing.
V. RELATED WORK
In conventional CMOS, an STDP synapse can be
implemented using capacitors to hold three state variables: an
LTD capacitor to implement the exponential time decay oI the
LTD curve, an LTP capacitor Ior the LTP curve, and a
conductance capacitor (plus, perhaps, a Ilip-Ilop or SRAM
cell Ior the case oI binary synapses) to hold the synaptic
communication eIIicacy. A small number oI transistors and
resistors then complete the circuit, e.g. see |18|. The resulting
synapse can easily be 10 microns on a side or larger |12|
limiting the number oI synapses per chip to a number too
small to be oI much commercial interest Ior general
applications.
An early proposal to exploit the nonlinear dynamics oI
memristive nanodevices to implement a learning law was
made in |19|. In that approach, bipolar spikes driven Irom
both the 'pre and 'post neurons would cause LTP when the
spikes aligned to create a super-threshold voltage drop across
the device; LTD was implemented by spikes Irom the 'post
neurons.
Likharev`s group at Stonybrook |20, 21| has worked Ior
several years on neuromorphic architectures using stochastic,
bistable nanodevices Ior synapses.
VI. CURRENT STATUS
Our group has been Iabricating crossbars oI memristive
nanodevices Ior several years (Fig. 17). Last year we
successIully imprinted single nanowires onto a CMOS chip,
achieving good electrical contact. We have just received Iirst
silicon to test imprinting oI larger crossbars (a Iew thousand
nanodevices) on CMOS and plan to implement the circuits
described here in the coming months.
VII. DISCUSSION
This design has some advantages worth noting:
x Better control over power dissipation. The approach in
this paper allows the designer to make trade-oIIs between
power dissipation and learning speed by suitable design
oI the pulse width modulators. Narrower pulses will slow
learning, but also reduce power.
x Fewer constraints on the design of memristive materials
used for nanoscale svnapses. The designer is not
constrained to low-conductance memristive materials in
order to keep power dissipation under control.
x Greater freedom in learning algorithm. Synaptic learning
can be dynamically turned on or oII (e.g. by attentional
priming mechanisms communicated extra-synaptically).
Since the STDP dynamics are spread over the 'pre and
'post neurons along with the memristive device itselI, an
electronic implementation can have greater control over
learning than is, perhaps, available to biology. This opens
the possibility oI new learning algorithms.
x Greater control over the precise form and timing of the
STDP equations. Since the STDP equations are
implemented in CMOS rather than in the memristive
material, a designer has much greater control over them.
Figure 15. Input TDM and LTD Timing circuits.
0
1
2
3
1
T0V
derux
0
1
2
3
1
T0V
rux
0
1
2
3
1
T0V
derux
PwV
exc|le |r
C0 R0
v0
|rr|o|l |r
lo reuror process|rg
lo reuror process|rg
sp||e lror
reuror process|rg
Figure 16. Neuron input.
lo reuror
process|rg

- lror |rpul
T0V
surr|rg
arp||l|er
v|rlua|
grourd
Figure 17. Crossbar oI memristive nanodevices Iabricated at HP Labs
using nanoimprint lithography.
2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008) 91
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x The abilitv to implement a wide varietv of other learning
laws besides STDP. The approach described here is Iairly
general and can implement such laws as instar, outstar,
Oja`s rule, etc. simply by modiIying the CMOS neuron
design.
x Better circuit diversitv since the approach allows diIIerent
learning laws to be implemented in diIIerent areas oI a
single neuromorphic chip using the same memristive
material Ior all synapses.
There are a number oI simpliIications one might make. For
example, the LTD- and LTP- timeslots could be eliminated iI
it were determined that the signaling induced 'noise in the
synaptic eIIicacy was acceptable without them. Similarly, the
COMM timeslot could be split into COMM and COMM-
timeslots to Iurther reduce such noise iI necessary. One could
even eliminate the COMM timeslot altogether, and simply use
the LTD and LTP channels Ior communication as well as
learning, reducing the number oI timeslots to two.
We should note that STDP alone may not be suIIicient to
implement stable learning; more complex synaptic dynamics
and additional state variables may be required |22, 23|. By
Iactoring out the two STDP timing variables to pre and post
neurons, we might ease the problem oI creating additional
state variables in the memristive material, e.g. by adding
additional dopants.
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92 2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008)
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