ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Graphene Nanoelectronics
Chun-Yung Sung IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, U.S.A.

Graphene, a two-dimensional (2D) material with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power applications. [1-3] Ultra-thin body enables the ultimately scaleddown device feasibility. (Fig. 1) Here we report the graphene nanoelectronics progress in synthesizing wafer-scale monolayer-controlled graphene and fabricating high-speed graphene FETs (GFET) with the highest value reported cut-off frequency (fT) approaching 100 GHz. Epitaxial growth is investigated to produce wafer-scale, high-quality graphene. [4-5] IBM has implemented a decomposition-based technique with in-situ monolayer control capability using a high temperature UHV growth chamber, equipped with low-energy electron diffraction microscopy (LEEM). (Fig. 2) The in-situ LEEM provides real-time electron reflection images from the graphene surface, allowing graphene formation via Si desorption from the SiC surface at elevated temperature to be studied and controlled. The system is capable of monolayer thickness precision and 5nm lateral resolution enabling graphene synthesis optimization. [5] A sequence of morphological transformations takes place on the SiC surface cleaned by exposure to Si at 900C. Upon further heating (1300oC), the graphene nucleates at SiC surface steps. (Fig. 3) However, graphene epitaxial growth on SiC usually suffers from the presence of thermal etch pits, rough morphology and small graphene domain sizes. We discover raising phase transition temperatures over wide ranges (250oC) by establishing thermodynamic equilibrium between SiC and external Si (disilane) vapor pressure (10-7 Torr), dramatically improves graphene surface morphology (Fig. 4), eliminates thermal pitting and achieves large atomically smooth terraces other than the intrinsic miscut steps, allowing growth of 3 thick (1-2 layers) graphene uniformly across 2 SiC wafers with only monolayer variation, as confirmed by electron diffraction, Raman spectroscopy and AFM. (Fig. 5) It is an important advance in SiC-based large scale graphene epitaxy. Single-layer exfoliated GFETs are fabricated to study intrinsic transport properties. The adhesive noncovalent interfacial layer NO2-TMA or polymer, which was deposited onto the chemically inert graphene surface prior to forming uniform ALD Al2O3 gate oxide (10nm) and Pd/Au top-gate, helps to minimize mobility degradation by the suppression of extrinsic surface phonons and screening of charged impurities. Being able to preserve GFET mobility is a significant improvement for advancing graphene device technology. (Fig. 6) [7] Despite the small on/off ratio (~10), GFETs are ambipolar devices where the conductance minimum is denoted as the Dirac point. GFETs exhibit linear ID-VD without current saturation due to the zero-bandgap. Bandgaps can be introduced by the single-layer graphene nanoribbon (GNR) fabrication or by applying an electric field perpendicular to the plane of a double-gated bilayer grapheme. (Fig. 7, 8) [7-10] The gm rises linearly with increasing VD which indicates that the GFET cut-off frequency can be described as fT=gm/(2 C) like conventional MOSFETs. The de-embedded current gain h21 follows an ideal -20dB/dec slope, validating the devices FET behavior. Because of device operating in the triode regime, the maximum fT increases as gate length decreases with a 1/LG2 dependence, rather than the conventional 1/LG scaling. (Fig. 9) [11-12] A 350-nm-gate exfloited GFET yields the highest cut-off frequency value reported (approaching 100 GHz) for any graphene devices to date (Fig. 10 a).Devices on high quality epitaxially-grown graphene (1-2 layers) also exhibit the room temperature Hall mobilities up to 1450 (gated) and 1575 (ungated) cm2 V-1s-1 and the record high epitaxial GFET fT = 24GHz with LG=500nm. (Fig. 10b) IBM has demonstrated GFET performance well above Si MOSFET fT-Lg trend shown in 2008 International Roadmap for Semiconductors (ITRS). [13]
Refererence: [1] M. Y. O. Han, et al., Phys. Rev. Lett., vol. 98, p. 206805, 2007. [2] C. Doan, et al., IEEE Journal of Solid-State Circuits, vol. 40, pp. 144-155, Jan. 2005. [3] Y. Zheng, et al., " Nature, vol. 438, p. 201,2005. [4]. C. Berger, et al., J.Phys. Chem B, vol. 108, p. 19912, 2004. [5]. J. Hannon, et al., Phys. Rev. Lett., vol. 96, p. 246103, 2006. [6] Z. Chen, et al., Physica E, vol., 2007. [7] D. Farmer, et al., Nano Letters, vol. 6, p. 699, 2006. [8] D. Singh, et al., Electronics Letters, vol. 41,pp. 280-282, March 3 2005. [9] E. McCann et al., PRB 74,161403R (2004). [10] Ohta et al, Science 313, 591 (2006). [11] I. Meric et al., IEDM Digest 4796738 (2008). [12] Y.-M. Lin et al., Nano. Lett. 9, 422 (2009). [13] http://www.itrs.net/Links/2008ITRS/Home2008.htm

ISDRS 2009 http://www.ece.umd.edu/ISDRS2009

978-1-4244-6031-1/09/$26.00 2009 IEEE

ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Graphene,1200 C

T3
Si Si C Si

C
600nm

Increasing T

T2

Si

Buffer Graphene,1075 C 1/3 Layer Extra Si,1050 C

SiC Si Desorption
Graphene Contact

T1

Graphene on SiC

Prep. Chamber and LEEM

Disordered Si-Rich,950 C

Two Layers of Extra Si, 850

CMOS like Processes

Graphene Device

Fig.1. Graphene, atomic sheet planar form of graphitic carbon, is promising for high performance nanoelectronics for many attractive physical properties and CMOS process compatibility [1-3].

Growth Chamber
Fig.2. Monolayer in-situ controlled graphene epitaxial chamber equipped with low energy electron diffraction microscopy [4-5].

Fig.3. LEEM images of graphene formations on SiC. Graphene (bright) nucleates at surface steps. Upon further heating (1300oC), one atomic layer graphene grows to >300 nm wide strips of nearly arbitrary length [5].

ALD Oxide

o v ap

rp

re s

e sur

S iC S i/

1-2 layers 1 1-2 layers 1-2 layers 1-2 layers 100 m 0 1-2 layers

Interfacial Layer Graphene Substrate

Before Gate Processes After Gate Processes

v ap

re or p

eS s ur

i/Si

Fig.4. Graphene surface morphology is dramatically improved by raising phase transition temperatures to establish thermodynamic equilibrium between SiC and external Si pressure.

Fig.6. The adhesive noncovalent interfacial layer was deposited onto graphene prior to Fig.5. Large atomically smooth 3 thick (1-2 forming uniform ALD gate oxide to preserve layers) graphene is uniformly grown across 2 mobility by suppressing surface phonons and SiC wafers with only monolayer variation. screening charged impurities. [7]

40
Confinement

fT
fT(GHz)
g

ky

En

2000(meV) W (nm)

ffT(GHz) T [GHz]

kx

gm 2 Cg

Conductance(mS)

30 20 10 0

1/L2 1/L2

fT gm

Field-Induced Gap
k
g g

100

200

300

400

500

meV ~ 13.9 V Vg

gm (mS/mm)

Fig.7. Bandgaps are introduced by single-layer graphene nanoribbons (GNRs) or by applying an electric field perpendicular to the plane of double-gated bilayer graphene [6,9-10].
Field-effect Mobility

VTG (V) LLG(nm) G [nm] Fig.9. The gm rising linearly with VD indicates fT= gm /(2 C) like conventional MOSFETs. Because GFET operates in the triode regime, the maximum fT increases as gate length decreases with a 1/LG2 dependence rather than the conventional 1/LG scaling. [11-12]

(a)
|h21|

(b)

120.0 100.0 80.0 60.0 40.0 20.0 -3 -2 -1 0

Vd=1.3 V

Conductance [uS]

14 12 10 8 6 4 2 -20

|h21|

e n

C Vg

10 Vds = 2.0V Vds = 1.0V

Top gate voltage, Vg (V)

16 GHz 24 GHz

Room Temperature

-10

0 Vg [V]

10

20

1 0.1

10

Fig.8. Mobility >2000 cm2/Vs is achieved from an exfloited single-layer GNR device with width ~30nm and length ~820 nm [12].

Frequency (GHz) Frequency (GHz) Fig.10. (a) The de-embedded current gain h21 follows an ideal -20dB/dec slope, validating FET characteristics. A 350-nm-gate exfloited graphene FET yields the highest fT (approaching 100GHz) reported to date. (b) An epitaxially-grown G FET (1-2 layers, LG=500nm) achieves the record high fT =24GHz. [11-12]

ISDRS 2009 http://www.ece.umd.edu/ISDRS2009