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by Gregory L. Moss
Schematic capture of maxplus2 functions Drawing signal buses Sequential circuit simulation Schematic capture of megafunctions Simulation of state machines Measuring time intervals in simulations Clock frequency divider
A bus must be labeled if it is split or merged. A bus does not have to be labeled if there are no individual signals broken out of the bus. A bus label has a group name that consists of the bus identifier followed by the numerical signal range in brackets, such as Q[3..0]. The signal range indicates the labels for the individual signals going into or coming out of the bus. The range of numbers also will indicate the width of the bus (i.e., number of signals contained in the bus). The individual signal lines going into or coming out of a bus must also be identified with the desired individual signal name, such as Q[3] or Q[2], etc. To label buses and signal lines, click the left mouse button while pointing at the line and then type the desired Bus or Node Name. Input and output ports that are connected to a labeled bus should have a PIN_NAME that is the same as the bus label. Buses and Nodes may be labeled with names that are different than the pinstub labels inside the symbols they are connected to. Connections between signals in a bus and a group pinstub are made in the order specified by the range order inside the respective brackets. Buses can also be merged into (or split from) larger buses. Symbols for logic blocks that are defined with group inputs or group outputs will be drawn with ports represented as buses. Be very careful in labeling buses or signal lines. Any Node or Bus with the same name will be connected (shorted) together.
Gates
LPM_AND, LPM_INV, LPM_OR, LPM_XOR LPM_CONSTANT LPM_DECODE LPM_MUX
Storage
LPM_FF LPM_LATCH LPM_SHIFTREG
To enter a megafunction module into a BDF file, double-click the MegaWizard Plug-In Manager in the Tasks Pane.
Open the appropriate megafunction category folder from the list on the left & select the desired megafunction. The example below is an adder/subtractor megafunction from the Arithmetic folder. The correct device family should be identified. Choose an output file type (any HDL can be used). Type a unique filename for this output file. Click Next to continue with the setup for this megafunction. The details will depend on the function type.
The final MegaWizard dialog page is the Summary. Make sure the Quartus II symbol file is checked. Click Finish.
When finished defining the megafunction, double-click in the Block Editor drawing window to open the Symbol dialog. Open the Project folder and select the file for this megafunction. Click OK & place symbol in the drawing.
You must let Quartus know that this megafunction design file should be included in the current project. Double-click the Add/Remove Files in Project task in the Task Pane.
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Click the Add All button to add megafunction design files that are located in the current project folder. or Click the Browse button to locate the megafunction design file from other project folders. Select the desired megafunction design file and click the Open button to return with the File name to the Settings dialog. Click the Add button. Click OK when all other design files have been added to the project. Add All Browse
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modulus
=
=
freqclock_in freqclock_out
50MHz 10kHz = 5000
Thus, we will need a mod-5000 counter to obtain the desired output frequency. Next determine the number of counter bits necessary to create a mod-5000 counter. The simplest count sequence for the mod-5000 would be 0 to 4999 so the largest binary number is 1001110000111 (or 138716). This indicates that we will need a 13-bit counter for our frequency divider. The most significant counter bit q[12] will produce one waveform cycle for every 5000 input clock cycles. The frequency of q[12] will be 1/5000 of the frequency of the input clock signal. Use the Quartus MegaWizard to create the desired counter. Choose lpm_counter from the arithmetic library folder. The output file type does not matter for this application so we will arbitrarily use AHDL. Continue through the wizard parameter settings dialogs until you reach Finish & generate the Block Symbol File (bsf). Place the lpm_counter symbol and complete the wiring as shown below. Add the lpm_counter design file to the current project (Add/Remove Files in Project task). If we connect the 50 MHz signal to clock, then clkout should be 10 kHz. If we create a symbol for this block, we can add this design file to other projects.
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