Design Considerations for High Resolution Pipeline ADCs in Digital CMOS Technology

Jorge Guilherme
jorge@gcsi.ist.utl.pt

P. Figueiredo
pmff@chipidea.com

Joo Vital
joao@gcsi.ist.utl.pt

P. Azevedo
pazevedo@chipidea.com

G. Minderico
minderic@chipidea.com

A. Leal
aleal@chipidea.com

Jos Franca
franca@gcsi.ist.utl.pt

IST Center for Microsystems Integrated Circuits and Systems Group INSTITUTO SUPERIOR TECNICO Av. Rovisco Pais 1, 1096 Lisboa Codex, PORTUGAL
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CHIPIDEA Microelectrnica Edificio Inovao IV Sala 733 2780-920 PORTO SALVO - PORTUGAL

ESD-MSD Cluster, Malta 3 September 2001

Outline
Introduction Pipeline overall noise contributions Trade offs between noise and power in single stage amplifiers Trade offs between noise and power in two stage amplifiers Optimization of the compensation capacitor Pipeline example architecture Conclusions
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Block diagram of an N-bit and Ni-stage pipeline ADC

Digital Output Digital Correction

Registers Analog SHA input Stage 1 Stage i Stage n

G residue amplifier Ni- bit ADC Ni- bit DAC G=2 Ni

Noise contribution of each stage

Vni =
2 Vno , S & H

2 Vno , MDAC1

1 G12

2 Vno , MDAC 2 2 1 G12 G 2

The main noise contribution comes from the input stages

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Noise budget relation:

Quantization noise Thermal noise KT/C
2 Nq =

1 12 2 2 N

Quantization noise > Thermal noise

Quantization noise < Thermal noise

Excessive power dissipation, no advantage

Loss of resolution

Best trade off Quantization noise Thermal noise but Difficult to achieve
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Simplified noise model of the MDAC

Ron Vin 1 C DAC 1 CL Cf

Cp Ron Vref 2 Gm

Noise bandwith of the amplifier

MDAC output noise

KT 2 2 Vno, MDAC = 2 + 4 KTRON Beq + Vnamp Gi 2 C DAC

Beq =

gm gm = 2 2C eq 4C eq
C L (C DAC + C P ) Cf

C eq = C DAC + C L + C P +

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The amplifier has one of the most important noise contributions

Low noise amplifiers topologies should be chosen

Two stage telescopic cascode amplifier

Load vdd Bias

The telescopic cascode yields the lowest noise since only two transistors contribute to the total noise
gm Load 2 KT 1 + gm difpair = 3C C

M3 Cc

M4 Cc

VnTelescopic

M1

M2

diffpair Bias gnd

The noise can be controlled by Cc and gm of transistors Cascode compensation achives higher GBW for the same power as Miller compensation
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Residue amplification phase

Single stage amplifier
Cf C DAC

A0

CL Cp Gm
f BW GBW

Number of time constants for a first order system

N = ln(2B )
CMOS transcondutance relation

Vout

gm 2 = I B VOVD

Close loop dominant pole

BW = GBW = C (C + C P ) 2 CL + CDAC + CP + L DAC CF gm

C eq = C DAC + C L + C P +
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C L (C DAC + C P ) Cf

ln(2 B )VOVD C eq IB A TSR Fs

IB doubles for each increasing bit !
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Residue amplification phase

Two stage amplifier
Cf C

DAC Cc CL Cp Gm Output stage Vout Gm load

CL influences the phase margin of the amplifier

The GBW depends on Cc

GBW = gm 2C C

BW = 2CC

gm Cf CDAC + C f + CP

CC C f ln(2 B )VOVD IB A C DAC + C f + C P TSR Fs

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IF !
Noise of the amplifier

2 Vnamp

KT CDAC

C DAC =

CC 2 1 + gm Load gm difpair 3

For typical designs gmload < gmDiffpair CDAC 0.75 Cc

Leads to a higher output pole since Cc is higher than CDAC

In the order of 2-3 times

Poleoutput

gmLoad CL

Helps improving stability

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A two stage amplifier has at least 4 legs The gm of the output needs be higher than the input by 2-3 times, due to stability For the same overdrive voltage the output current will be 2-3 times the input current

Pstage 8VDD I B
Pstage CC C f ln(2 B )VOVD 8VDD A C DAC + C f + C P TSR Fs

Assuming equal noise contributions for the S/H and MDAC

C C f = DAC 2 Ni
CC = 8 KT

1 + gmLoad gmdifpair

12 2Vref 2 N 2 1

Cc will be the starting point of the design optimization

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Is the fraction of quantization noise attributed to the S/H and first MDAC

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High resolution ADCs optimization

First stages will be noise limited if

Stage gain precision not limitted by matching Use of analog or digital calibration techniques

Remaining stages will be matching limited and area dictates the power dissipation Total power dissipation will be a trade off between the noise and matching First stages should use large resolution 4-5 bits Final solution obtained by a optimization program

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Architecture for 15bit@10MS/s ADC

Frontend Vref Generation Backend Vref Generation

SAR Vbg

CAL-DAC
Vrefbp Vrefbn Vrefp

Backend inputrange calibration Vrefp Vrefn amp. o ffset calibration

Vbg

SAR

CAL-DAC

17R 3R 3R 17R

17R

Vrefn

Inp S/H Inn

3R 3R
Unity c urrentsource matrix

Switches
15b Out

Comparator

17R Backend
1.5 b/stage pipeline ADC

FLASH
6b

DAC

Clk

DAC full-scale current generation

Iref Digital Error Correction Logic

10b

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Noise contribution of the Front-end Pipeline Blocks

2 Csh 1 Vin 1 Csh 2 1'

Input sampling capacitors S/H amplifier

Flash

DAC

Residue amplifier Resistors

DAC

Vndac =

16 K T Id Fn R 3 Vod

The resistors and the DAC inject large noise! The DAC noise current is proportional to gm
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2 K T Vnamp = 3 Cc

1+

Vdsat1 Vdsat 7 f
Fn =

Kelvin 1998

Vr = 4 K T Fn R

Fo = 70 MHz 2

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SNR system calculation

2 1 Vref 2 2 SNR = 10 log Vref 2 2 K T 2.Vr 2 + 2.Vnamp 2 2 2 2 12.2 2 N + C + 4 Vnamp + 2.Vr + 2.Vndac + 32

= 78dB

Noise distribution by block Quantization KT/C Resistors DAC Amplifiers 26% 17% 20% 16% 21%

Trade off between power, noise and resolution obtained by program

C = 10 pF Cc = 10 pF Idac = 1mA Rstring = 1000 ohm

Noise Bandwidth of a 2 pole system = 0.7854 Fo helps reducing the noise from the DAC and resistors
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SNR system simulation

Noise from the DAC

Simulated noise
2 Vref 1 2 2 SNR = 10. log 10 2 = 78.6dB Vref 2.K .T 2 12 2 2 N + Cs + SimulatedNoise

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Main schematic of the amplifiers used in the S/H and residue amplifiers
vdd

The amplifiers where designed based on the noise allowed to it dependent on Cc A telescopic cascode compensation topology was chosen to minimize power From Cc and GBW we obtained the gm and current of the input diferential pair
GBW = gm 2C C
M9

Bias M7 M11 M5 I M6 I M10 M3 Cc OutP VinN M4 Cc OutN M8 M12

VinP

M1

M2

Bias M14 gnd

M13

M15

gm1 gm3.gm9 C 2.Cc.s 2 2 C 2.CT H ( s) = gm3.(CL + Cc ) .gm1.Cc 2 gm3.gm9.Cc .gm1.gm3.gm9 s3 + s + s + 2 2 CT C 2.CT C 2.CT 2

2 K T Vnamp = 3 Cc

1+

Vdsat1 Vdsat 7 f

CT = C1.CL + C1.Cc + CL.Cc

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Front-end Amplifiers
ph2

17R 3R

17R

ph1 Vin ph1

C
ph1a A1

3R
A2

Vo1 3R

Vo2 3R

A3

Vo3

C
ph2

17R

17R

Effect of Resistor L variation

Resistor model
R R R R

Cascade of 3 amplifiers close loop pole

CL

0.833

i 3

Rsquare=8*8um^2

n2 R C 2

Resistor area (matching) limits the settling Need of gain calibartion ESD-MSD Cluster, Malta 3 September 2001 17

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Calibration network
Calibration Operation
Comp

The first stage needs calibration of the gain

Block diagram of the calibration network

Calib Clock

end Calibration Control

control start

control

SAR l

end

start

SAR 2

end

Data Residue amplifier Backend Vref VCM

control

Data

Comparator

out

Calibration DAC 1
Io

Calibration DAC 2
Io

Offset Voltage of the Residue Amplifier

Backend Vref Voltage

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Current Steering DAC

Current steering DAC requirements: random errors Current source sizing: std dev(I/I) = 0.027% for 13 bit linearity Vod = 0.76V ==> total current source DAC transistor area = 0.817 mm2 Hierarchical symmetrical switching scheme used to compensate systematic errors
Yie ld fo r 6 b it D AC with 1 5 , 1 4 a n d 1 3 b it p re c is io n vs . re la tive a c c u ra c y 100 90 80 70 60 Yield [%] 50 40 30 20 10 0 0 0.01 0.02 0.03 0 .0 4 0.0 5 0.0 6 S td . d e v. U n ity C u rre n t S o u rc e [% ] 0.0 7 0.0 8

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Chip Layout

Summary
Resolution Conversion rate Power consumption Power supply Input range SNDR ENB Chip area Core area Process technology 15 bit 10Ms/s 320 mW 2.7-3.3V 1.1V 78.6 dB 12.7 bit 3.23 mm*4.75 mm 2.8 mm * 4.3 mm 0.35 m CMOS single poly 5-metal

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Conclusions
Identification of the main noise contribution to high resolution pipeline ADCs. Some trade offs between noise and power were discussed for single stage and two stage amplifiers. Noise limited stages can be optimized by chosing suitable compensation capacitor as starting point of design. An example of a pipeline 15 bit architecture was discussed

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