8085 MICROPROCESSOR

The 8085 p is package in a 40-pin, dual in line package. Power is supplied by as single 5V power supply connected across Vcc and Vss, +ve at Vcc and ground at Vss.

disadvantages of a decrease in speed and an increase in control and circuit complexity. At the beginning of each machine cycle, three control signals, IO/M, S1 and S0 are generated to identify the type of machine cycle , as shown in Table 1. Table 1 MC IO M S1 S0 R / W R IN A T D OF 0 1 1 0 1 1 MR 0 1 0 0 1 1 MW 0 0 1 1 0 1 IOR 1 1 0 0 1 1 IO 1 0 1 1 0 1 W Under normal circumstances, each of the above machine cycle, with the exception of the opcode fetch, requires three (internal) clock cycles, also called T States. An Opcodefetch machine cycle is essentially a special memory read machine cycle that has additional T States for the decoding and, sometimes, execution of an instruction. The number of T States ranges from one to three depending on the instruction. Figure 3 shows the timing diagram of an opcode-fetch machine cycle for the STA instruction. During T1: (a) The IO/M is made low to designate that the machine cycle requires a memory reference, as opposed to an I/O reference (b) The high order 8 bits (PCh) of the PC are placed onto A15 - A8 and remains these throughout the first three stated (c) The low order bits (PCl) of PC are placed onto AD7 - AD0 (d) ALE is pulsed causing PCl to be latched at the trailing edge and so become available on AD7 - AD0 (not shown) During T2: (a) The p relinquishes control of the AD lines as indicated by the dashed lines (b) RD is made low to enable the memory module for a read operation The memory module has until almost the end of T3 to place opcode on to AD7 - AD0. Near end of T3, RD is made high which results in the transfer of the opcode into the IR and terminates the read operation. During T4 the

The synchronization of the p operations is based on the frequency of the internal clock. The frequency of this clock is determined by a frequency-selective circuit connected across X1 and X2 inputs. This circuit can be an RC, LC, or a crystal. Alternatively, an external clock source can be connected to X1 only. In either case, an internal T flip flop energized from X1 input halves the frequency to make the internal clock frequency one half the frequency of the external clock or frequency selective circuit. Therefore, an 8085 p operated with a 6MHz crystal will have an internal clock or frequency of 3MHz and a period of approximately 333 ns. The minimum driving frequency limit depends on the version of the 8085: either 8085 A or 8085A-2. The 8085 p uses timemultiplexed data bus i.e. AD7 - AD0 are used sometimes as 8-bit data bus and sometimes as low-order 8-bits of the address bus multiplexing the data bus has the advantage of lowering the pin count, but has the

instruction is decoded to determine whether additional T States are required. For the realization of the 8-bit p with an 8085 p, some external circuiting is required as illustrated in Figure 2. The external circuiting consists simply of an 8 bit latch which is essentially a set of eight trailingedge triggered D flip flops. For a memory write operation (i.e. a memory write machine cycle) the p places the appropriate 16-bit memory address into the address bus, the 8-bit data on the data b us, and then places the appropriate signals on the control bus. For the 8085 these control signals are low for IO/M an WR, and high for RD. The AD lines have to be time multiplexed and this requires the following steps: 1- The high-order 8 bits of the 16 bit address are placed onto AD15 AD8 and the low order 8 bits on to AD7 - AD0. 2- The ALE signal is pulsed which causes the low-order 8 bits of the address to be latched at the trailing edge of this pulse. Consequently the 16-bit address is now available on the 16-bit address bus. 3- With the low-order 8 bits of the address saved in the 8-bit latch, the AD7 - AD0 lines are now free to be used as the data bus. Therefore the up will place the data to be transferred onto the data bus. 4- At this point the signal IO/M and WR should be low and RD should be high. The AD lines are similarly time-multiplexed for a memory read operation, such as opcodefetch or a memory read machine cycle. The following steps are required 1. The high-order 8 bits of the address are placed onto A15-A8 and the low-order 8 bits onto AD1-AD0. 2. The signal ALE is pulsed which causes the low-order 8 bits of the address to be latched at the trailing edge of this pulse. 3. With the low-order 8 bits of the address saved, the AD7-AD0 lines are now free to be used as the database 4. IO/M and RD are low and WR should be high 5. After an appropriate delay, the data (or opcode) is available on the data bus. 6. The control unit then places the data (or opcode) into the appropriate register.

Instruction cycle, machine cycles and T states An instruction cycle is defined to be all the machine operations that are required to fetch, decode and execute an instruction. An instruction cycle consists of a sequence of machine cycles. A machine cycle corresponds to a single machine operation on the external busses. For the instructions of the 8085 up, an instruction cycle is divided into one to five machine cycles, each of which is one of the following seven types. Opcode Fetch (OF) Memory read (MR) Memory write (MW) I/O read (IOR) Interrupt Acknowledge (INA) Bus idle (BI) Figure 4 shows a memory read machine cycle and Figure 5 shows a timing diagram for a memory write cycle. The only differences are that the address placed onto the address bus is not always the contents of the PC and the destination of the data transfer is not the IR but a general purpose of special register. Likewise a memory write machine cycle is similar to a memory read machine cycle. The only difference are that for a memory write machine cycle, the signal WR instead of RD is made low, and the transfer of data on the AD lines is in the opposite direction. Figure 6 shows a memory read machine cycle with a TWAIT state inserted. A TWAIT state is used to stretch a machine to accommodate slow memory modules that cannot return the data within the time required by the 8085 up. As shown in Figure 6, during T2 the up examines the value of the READY signal is an input signal from the slow memory module being read from. If READY is high, the up proceeds to T3, otherwise a TWAIT state is inserted indicating that the memory is not ready. Additional TWAIT states can be added indefinitely until READY becomes high. When READY signal goes high, the up will exit TWAIT and enter T3 to complete the machine cycle. TWAIT states can also be inserted for the opcode-fetch and memory write machine cycles.