Implementation of 8 Bit Alu in Fpga: EX - NO. 1 DATE: 11-2-2010

1 EX.NO.
1 DATE: 11-2-2010 AIM: To develop the source code for ALU by using verilog and VHDL and obtain the simulation, synthesize, place and route and implementation in FPGA.
IMPLEMENTATION OF 8 BIT ALU IN FPGA
TOOLS REQUIRED: Xilinx-7.1 Software package ModelSim XE II 5.7g FPGA kit-Sparta-3 Power cord
LOGICAL DIAGRAM:
VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66
2 TRUTH TABLE: S.No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Operation y<=a y<=a+1 y<=a-1 y<=b y<=b+1 y<=b-1 y<=a+b y<=a+b+cin y<=NOT a y<=NOT b y<=a AND b y<=a OR b y<=a NAND b y<=a NOR b y<=a XOR b y<=a XNOR b Function Transfer a Increment a Decrement a Transfer a Increment b Decrement b Add a and b Add a & b with carry Complement a Complement b AND OR NAND NOR XOR XNOR Logical Arithmetic Unit
PROCEDURE:
Step1: Start the Xilinx ISE 7.1i by using icon in desktop Step 2: Double click it to get project navigator
Step 3: File New project
Step4: Enter the project name and project location and then click next
Step5: Select the Device and other category and click next twice and finish
Step6: Double click on create new source
Step7: Select VHDL or Verilog module and give the filename click next and define ports click next and finish
Step 8: Write the source code in VHDL or Verilog in editor and save the code
Step9: To run check syntax Process WindowSynthesize double click check syntax and rectify the errors, if present
Step10: Simulate it by using model sim by double click on launch model sim simulator
Step 11: Give the input to the signal by editforcevaluegive the logical value and run in the wave-default window
6 Step12: To obtain the RTL schematic and Technological schematic in process windowView RTL schematic and Technological schematic
Step 13: SYNTHESIS REPORT & RTL SCHEMATIC Process window Synthesis - XST Double click View Synthesis Report Process window Synthesis - XST Double click RTL Schematic Process window Synthesis - XST Double click View Technology Schematic
Synthesis your design, from the source window select, Synthesis/ implementation from the window Now double click the Synthesis XST After the HDL synthesis phase of the synthesis process, you can display a schematic representation of your synthesized source file. This schematic shows a representation of the pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates double click View RTL Schematic
Double click the schematic to internal view Double click outside the schematic to move one-level back
7 This schematic shows a representation of the design in terms of logic elements optimized to the target device. For example, in terms of LUTs(Look Up Table), carry logic, I/O buffers, and other technology-specific components Double click View Technology Schematic Double click the schematic to inner view Double click the LUT to inner view. This is Gate Level view of LUT, if you want see Truth Table and K-Map for your design just click the respective tabs. After finishing the synthesis, you can view number of Slices, LUT (Look Up Table), I/Os are taken by your deign in Device using Design summary. Step 14 - IMPLEMENT DESIGN PLACE & ROUTE ---- BACK ANNOTATE PIN REPORT Process window Implement Design Place & Route Double click Place & Route Report Process window Implement Design Place & Route Back annotate Pin Locations Back annotate Pin Report Process window Implement Design Place & Route Back annotate Pin Locations View Locked Pin Constraints Design Implementation begins with the mapping or fitting of a logical design file to a specific device and is complete when the physical design is successfully routed and a bit stream is generated. Double Click Implementation Design After implementation you see Design Summary, you get the all details about your design. If you want edit the place and route double click View/Edit placed design You see where your I/Os are placed in FPGA. And zoom to view how Pins are placed in FPGA. You can see where your pins are placed
Just double click View/Edit Routed Design to view interconnection wires and blocks Click the pin to see where its placed in FPGA. And Zoom particular area to see Place and Routing. If you want to change the place of the design, click and trace to another slice. See!!! You changed place and route of the design
Double click Back annotated Pin Location. Once back annotation is completed, constraint file is generated.
Step 15-ASSIGN PACKAGE PINS Process window User Constraints Double click Assign package pins click yes
Enter the Pin value for your input and output signals. if you want see your Pin assignment in FPGA zoom in Architecture View or Package View
You see the Pins in FPGA. Save file as XST Default click ok and close the window
Step 16- GENERATE PROGRAMMING FILE
9 Right click the Generate Programming file select properties and then select the startup options change the clock into JTAG clock and then click apply and ok.
Double click the Generate Programming file Double click Configure Device click finish select the bit file and then click ok Right click Xilinx Device click Program ok
Programming is succeeded SPECIFICATIONS: --Design --Lecturer --Author --VMP No --Version --Simulator : 8 BIT ALU : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : Xilinx 7.1i : Model Sim
--Description : To Design and implement ALU in FPGA
--Designation : Student
PROGRAM FOR ALU:
10 VHDL SOURCE CODE-1: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity aluvhdl is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); s : in std_logic_vector(3 downto 0); y : out std_logic_vector(7 downto 0)); end aluvhdl; architecture Behavioral of aluvhdl is begin process(a,b,s) begin case s is when "0000" => y<=a; when "0001" => y<=a+1; when "0010" => y<=a-1; when "0011" => y<=b; when "0100" => y<=b+1; when "0101" => y<=b-1; when "0110" => y<=a+b; when "0111" => y<=a-b; when "1000" => y<= not a; when "1001" => y<=not b; when "1010" => y<=a and b; when "1011" => y<=a or b; when "1100" => y<=a nand b; when "1101" => y<=a nor b; when "1110" => y<=a xor b;
11 when "1111" => y<=a xnor b; when others => null; end case; end process; end Behavioral;
VHDL SOURCE CODE -2: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity aluvhdl is Port ( a : in std_logic_vector(7 downto 0):="00000100"; b : in std_logic_vector(7 downto 0):="00000011"; s : in std_logic_vector(3 downto 0); y : out std_logic_vector(7 downto 0)); end aluvhdl; architecture Behavioral of aluvhdl is begin process(a,b,s) begin case s is when "0000" => y<=a;
12 when "0001" => y<=a+1; when "0010" => y<=a-1; when "0011" => y<=b; when "0100" => y<=b+1; when "0101" => y<=b-1; when "0110" => y<=a+b; when "0111" => y<=a-b; when "1000" => y<= not a; when "1001" => y<=not b; when "1010" => y<=a and b; when "1011" => y<=a or b; when "1100" => y<=a nand b; when "1101" => y<=a nor b; when "1110" => y<=a xor b; when "1111" => y<=a xnor b; when others => null; end case; end process; end Behavioral;
VERILOG SOURCE CODE-1: module alug(a, b, s, y); input [7:0] a; input [7:0] b; input [3:0] s; output [7:0] y; reg [7:0]y; always@(a,b,s) begin
13 case(s) 4'b0000:y=a; 4'b0001:y=a+1; 4'b0010:y=a-1; 4'b0011:y=b; 4'b0100:y=b+1; 4'b0101:y=b-1; 4'b0110:y=a+b; 4'b0111:y=a-b; 4'b1000:y=~a; 4'b1001:y=~b; 4'b1010:y=a & b; 4'b1011:y=a | b; 4'b1100:y=~(a&b); 4'b1101:y=~(a|b); 4'b1110:y=a^b; 4'b1111:y=~(a^b); endcase end endmodule
VERILOG SOURCE CODE-2: module alv( s, y); input [3:0] s; output [7:0] y; reg [7:0]y; wire [7:0]a,b; assign a=8'b00000001,b=8'b00000011; always@(a,b,s) begin
14 case(s) 4'b0000:y=a; 4'b0001:y=a+1; 4'b0010:y=a-1; 4'b0011:y=b; 4'b0100:y=b+1; 4'b0101:y=b-1; 4'b0110:y=a+b; 4'b0111:y=a-b; 4'b1000:y=~a; 4'b1001:y=~b; 4'b1010:y=a & b; 4'b1011:y=a | b; 4'b1100:y=~(a&b); 4'b1101:y=~(a|b); 4'b1110:y=a^b; 4'b1111:y=~(a^b); endcase end endmodule
SYNTHESIS RTL SCHEMATIC:
15
SYNTHESIS TECHNOLOGY SCHEMATIC:
SIMULATION OUTPUT WAVEFORM:
16
SYNTHESIS REPORT; DEVICE UTILIZATION SUMMARY: Selected Device : 3s50pq208-4 Number of Slices: Number of 4 input LUTs: Number of bonded IOBs: TIMING REPORT Clock Information: -----------------------No clock signals found in this design TIMING SUMMARY: 35 out of 768 4% 68 out of 1536 4% 28 out of 124 22%
17 Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 18.843ns Total memory usage is 95352 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 1 ( 0 filtered) PLACE & ROUTE REPORT: Device Utilization Summary: Number of External IOBs Number of LOCed IOBs Number of Slices Number of SLICEMs 28 out of 124 0 out of 28 35 out of 768 0 out of 384 22% 0%
4% 0%
Total REAL time to Router completion: 1 secs Total CPU time to Router completion: 0 secs Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 1 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 69 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1
BACK ANNOTATE- REPORT:
18 # aluvhdl.lpc # The constraints in this file were created simply to be viewed. # If you wish to use these constraints, please copy them into your # project's constraint file. If you do not have a project constraints # file yet, please use the "Project->New Source" menu to create one. #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments #NET "s<0>" LOC = "p34" ; #NET "s<1>" LOC = "p35" ; #NET "s<2>" LOC = "p36" ; #NET "s<3>" LOC = "p37" ; #NET "y<0>" LOC = "p58" ; #NET "y<1>" LOC = "p61" ; #NET "y<2>" LOC = "p62" ; #NET "y<3>" LOC = "p63" ; #NET "y<4>" LOC = "p64" ; #NET "y<5>" LOC = "p65" ; #NET "y<6>" LOC = "p67" ; #NET "y<7>" LOC = "p68" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE #PINLOCK_BEGIN #Tue Apr 27 01:04:34 2010 NET "s<0>" NET "s<1>" NET "s<2>" NET "s<3>" NET "y<0>" NET "y<1>" NET "y<2>" NET "y<3>" NET "y<4>" NET "y<5>" NET "a<0>" NET "y<6>" NET "a<1>" NET "y<7>" NET "a<2>" NET "a<3>" NET "b<0>" NET "a<4>" LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = "P34"; "P35"; "P36"; "P37"; "P58"; "P61"; "P62"; "P63"; "P64"; "P65"; "P43"; "P67"; "P31"; "P68"; "P46"; "P48"; "P33"; "P52";
19 NET "b<1>" NET "a<5>" NET "b<2>" NET "a<6>" NET "a<7>" NET "b<3>" NET "b<4>" NET "b<5>" NET "b<6>" NET "b<7>" #PINLOCK_END LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = "P39"; "P51"; "P44"; "P40"; "P28"; "P45"; "P57"; "P50"; "P42"; "P29";
RESULT: Thus the source code for ALU by using verilog and VHDL was developed and simulation, synthesize, place and route obtained and implemented in FPGA.
20 EX.NO. 2 DATE: 18-2-2010
IMPLEMENTATION OF 4 BIT SLICED PROCESSOR IN FPGA
AIM: To develop the source code for sliced processor by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. TOOLS REQUIRED: Xilinx-7.1 Software package ModelSim XE II 5.7g FPGA kit Power cord
THEORY: Bit slicing is a technique for constructing a processor from modules of smaller bit width. Each of these components processes one bit field or slice of an operand. The grouped processing components would then have the capability to process the chosen full word length of a particular software design. Bit slice processors usually consists of an arithmetic logic unit(ALU) of 1,2,4 or 8 bits and control lines (including carry or overflow signals usually internal to the processor). For example, two 4-bit ALUs could be arranged side by side, with control lines between them, to form an 8-bit ALU. A micro sequencer or control ROM would be used to execute logic to provide data and control signals to regulate function of the component ALUs. Examples of bit-slice microprocessor modules can be seen in the Intel 3000 family, the AMDs Am2900 family or the National Semiconductor IMP-16 and IMP-8 family. PROCEDURE: 1. Start the Xilinx tool 2. Create project using the project wizard 3. Select VHDL module for writing the code in VHDL 4. Initialize the entity declaration by input and output ports entry 5. Write the architecture part o f the coding in VHDL for sliced processor
21 6. Synthesize and rectify the errors 7. Create a test bench waveform for the corresponding VHDL for sliced processor in Modelsim 8. Implement it in FPGA kit by pin assignments 9. Create a bit file for the design and download the same in FPGA 10. Verify the operation of sliced processor in FPGA. BLOCK DIAGRAM:
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SPECEFICATIONS: --Design -- Lecturer --Author --VMP No --Version --Simulator : SLICED PROCESSOR : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : Xilinx 7.1i : Model Sim
--Description : To Design and Implement Sliced Processor
VHDL CODING; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mont_bitslice_setone is port(clk, ena, rst, stream : in std_logic; rsi_p1, rsi_m1, rci_m2 : in std_logic; ai, bi_m1, qi, mi : in std_logic; c1i_m1, c2i_m1 : in std_logic; c1i, c2i : out std_logic; rsi, rci : out std_logic); end mont_bitslice_setone; architecture Behavioral of mont_bitslice_setone is signal rc1, rc2, rc3, rc4 : std_logic; signal rs1, rs2, rs3, rs4 : std_logic; signal c1, c2, c3, c4 : std_logic;
23 signal ab, qm : std_logic; signal a1, a2, a3, a4 : std_logic; begin rs1 <= rsi_m1 when stream = '1' else rsi_p1; ab <= ai and bi_m1; c1i <= rs1 and ab; a1 <= rs1 xor ab; qm <= qi and mi; rc1 <= rci_m2 when stream = '1' else rc3; c1 <= a1 and qm; a2 <= a1 xor qm; c2 <= rc1 or c1i_m1; c3 <= a2 and c2; a3 <= a2 xor c2; c4 <= a3 and c2i_m1; a4 <= a3 xor c2i_m1; c2i <= c1 or c3; rc4 <= rc3 and (not rst); rs4 <= stream when rst = '1' else rs3; rc2 <= c4 when ena = '1' else rc4; rs2 <= a4 when ena = '1' else rs4; operate_reg : process(clk) begin if clk = '1' and clk'event then rc3 <= rc2; rs3 <= rs2; end if; end process operate_reg; rci <= rc3; rsi <= rs3; end Behavioral;
24
SYNTHESIS RTL SCHEMATIC:
SYNTHESIS TECHNOLOGY SCHEMATIC:
25
SYNTHESIS REPORT DEVICE UTILIZATION SUMMARY: Selected Device : 3s400pq208-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs: TIMING REPORT Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |2 | -----------------------------------+------------------------+-------+ 12 out of 3584 0% 2 out of 7168 0% 21 out of 7168 0% 17 out of 141 12% 1 out of 8 12%
26 Timing Summary: --------------Speed Grade: -4 Minimum period: 4.087ns (Maximum Frequency: 244.678MHz) Minimum input arrival time before clock: 9.604ns Maximum output required time after clock: 10.210ns Maximum combinational path delay: 12.532ns PLACE AND ROUTE REPORT: Device speed data version: "PRODUCTION 1.35 2005-01-22". Device Utilization Summary: Number of BUFGMUXs Number of External IOBs Number of LOCed IOBs Number of Slices Number of SLICEMs 1 out of 8 17 out of 141 0 out of 17 12% 12% 0%
11 out of 3584 1% 0 out of 1792 0%
Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Total REAL time to Router completion: 1 secs Total CPU time to Router completion: 0 secs Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 2 | 0.040 | 1.054 | +---------------------+--------------+------+------+------------+-------------+ INFO:Par:340 The Delay report will not be generated when running non-timing driven PAR with effort level Standard or Medium. If a delay report is required please do one of the following: 1) use effort level High, 2) use the following
27 environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing constraints for the design. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 1 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 75 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 BACK ANNOTATE- REPORT: # mont_bitslice_setone.lpc # The constraints in this file were created simply to be viewed. # If you wish to use these constraints, please copy them into your # project's constraint file. If you do not have a project constraints # file yet, please use the "Project->New Source" menu to create one. #PINLOCK_BEGIN #Tue Apr 27 01:24:06 2010 NET "c2i_m1" NET "rsi_m1" NET "rsi_p1" NET "clk" NET "ena" NET "mi" NET "bi_m1" NET "qi" NET "rci" NET "rci_m2" NET "rsi" NET "stream" NET "c1i_m1" NET "c1i" NET "rst" NET "c2i" LOC = "P37"; LOC = "P44"; LOC = "P45"; LOC = "P181"; LOC = "P39"; LOC = "P40"; LOC = "P35"; LOC = "P42"; LOC = "P62"; LOC = "P43"; LOC = "P63"; LOC = "P48"; LOC = "P36"; LOC = "P58"; LOC = "P46"; LOC = "P61";
28 NET "ai" LOC = "P34"; #PINLOCK_END
RESULT: Thus the sliced processor system was designed using Xilinx tool and its operation was verified by implementing it in FPGA and the simulation, synthesis, place and route was obtained.
EX.NO. 3 DATE: 25-2-2010
SYSTEM DESIGN USING PLL
AIM: To develop the source code for a system design using phase locked loop (PLL) by using VHDL and obtain the simulation, synthesis, place and route and implement into FPGA. TOOLS REQUIRED: Xilinx-7.1 Software package ModelSim XE II 5.7g FPGA kit-Spartan-3 Power cord
THEORY:
29 Phase Locked Loop are analog building blocks used extensively in many analog and digital systems. Phase Locked Loop usually consist of phase detector low pass filter gain stage VCO
The phase detector is a circuit that normally has an output voltage with an average value proportional to the phase difference between the input signal and the output of the vco.The low pass filter is used to extract the average value from the output of the phase detector.The average value is then amplified to drive the vco.The negative feedback of the loop results in the output of the vco being synchronized with the input signal. A Phase Locked Loop (PLL) circuit synchronizes to an input waveform within a selected frequency range, returning an output voltage proportional to variations in the input frequency. It has three basic components: a voltage controlled oscillator (VCO), which returns an output waveform proportional to its input voltage, a phase detector which compares the VCO output to the input waveform and returns an output voltage depending on their phase difference, and a loop filter, which filters the phase detector voltage, returning an output voltage which forms the VCO input and the external voltage output of the PLL. The phase locked loop has been found to be a useful element in many types of communication systems. It is used in two fundamentally different ways: (1) as a demodulator, where it is used to follow phase or frequency modulation (2) to track a carrier or synchronizing the signal which may vary in frequency with time. When operating as a demodulator, the phase locked loop may be thought of as a matched filter operating as a coherent detector. When used to track a carrier, it may be thought of as a narrowband filter for removing noise from a signal. DESIGN FORMULA The phase difference = ( in fr ) \ Klp Kpd Kosc.
30 A phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signal, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. This type of mechanism is widely used in radio, telecommunications, computers and other electronics applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete phaselocked loop building block, the technique widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz. PROCEDURE: 1. Start the Xilinx tool ISE. 2. Create a project using the project wizard. 3. Select VHDL Module for writing the code in VHDL. 4. Initialize the entity declaration by input and output ports entry. 5. Write the architecture part of the coding in VHDL for the system of pll. 6. Compile the project 7. Select the simulate options and load the files 8. Select the view signals option and load the necessary signals. 9. Force the clock and data input and run the program. 10. View the simulated result of phase locked loop. 11. For the implementation of the phase locked loop locate the pins in the FPGA. 12. Create a bit file for the phase locked loop and download the same in the FPGA. 13. Verify the operation of phase locked loop in the FPGA.
PLL BLOCK DIAGRAM
31
SPECEFICATIONS: --Design -- Lecturer --Author --VMP No --Version --Simulator : SYSTEM OF PHASE LOCKED LOOP : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : Xilinx 7.1i : Model Sim
--Description : To Design and Implement PLL
VHDL SOUCE CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pll is Port ( datain : in std_logic; -- raw data input clock : in std_logic; -- 64 bit clock clrdcd : in std_logic; -- clear dcd when 8 ones are detected dcd : out std_logic; -- data carrier detect output
32 rx_clock : out std_logic; -- recovered rx clock dataout : out std_logic);-- received data output end pll; architecture Behavioral of pll is signal counter : std_logic_vector(4 downto 0):= "00000"; -- counter 0...31 signal dcd_cntr : std_logic_vector(7 downto 0):= "00000000"; -- counter 0...255 signal edge : std_logic; --- edge detector output : data decision changed signal dly_data : std_logic; -- delayed data for edge detector signal q1 : std_logic; -- late clock signal qe : std_logic; -- early clock signal enable : std_logic; -- gets toggled every clock or when clock has to be adjusted signal increment : std_logic := '0'; signal decrement : std_logic := '0'; signal clear_dcd : std_logic := '0'; signal reset_dcd : std_logic := '0'; begin --- recovered rx clock for following stages rx_clock <= counter(4); process(clock, clrdcd, reset_dcd) begin if(clock'event and clock = '1') then clear_dcd <= reset_dcd or clrdcd; end if; end process; --- clock in new data process(clock, datain) begin if(clock'event and clock = '1') then dataout <= datain; end if; end process; -- rx clock counter process(clock, enable, clrdcd) begin if(clock'event and clock = '1') then if(enable = '1') then counter <= counter + '1'; -- increase counter
33 else counter <= counter; end if; end if; end process; -- set early and late clocks process(counter) begin if(counter = "10000" or counter = "01111") then q1 <= '0'; qe <= '0'; elsif (counter(4) = '1') then --- late clock when counter > 32 q1 <= '1'; qe <= '0'; else q1 <= '0'; --- early clock when counter < 31 qe <= '1'; end if; end process; -- adjust rx clock process(clock, enable, clrdcd) begin if(clock'event and clock = '1') then --- increment clock when edge detect during early clock if(qe = '1' and edge = '1') then increment <= '1'; end if; --- decrement clock when edge detect during late clock if(qe = '1' and edge = '1') then decrement <= '1'; end if; --- clear after one step increment if (enable = '1') then if (increment = '1') then increment <= '0'; enable <= '1'; else enable <= '0'; end if; else
34 --- clear after one step decrement if (decrement = '1') then decrement <= '0'; enable <= '0'; else enable <= '1'; end if; end if; end if; end process; -- dcd detection process(clock, edge, counter, clear_dcd) begin if(clear_dcd = '1') then dcd_cntr <= (others => '0'); dcd <= '0'; reset_dcd <= '0'; elsif(counter(4)'event and counter(4) = '0') then if(edge = '0') then -- sample at rising edge, if no data change increase counter if(dcd_cntr = 255) then dcd <= '1'; -- assert dcd if dcd counter is at max dcd_cntr <= dcd_cntr; else dcd <= '0'; dcd_cntr <= dcd_cntr + '1'; end if; else reset_dcd <= '1'; end if; end if; end process; --- edge detector, input data has changed process(clock, datain) begin if(clock'event and clock ='1') then edge <= dly_data xor datain; dly_data <= datain; end if; end process;
35 end Behavioral;
SYNTHESIZE RTL SCHEMATIC:
SYNTHESIZE TECHNOLOGY SCHEMATIC:
36
SYNTHESIZE REPORT: Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: 17 out of 3584 0% Number of Slice Flip Flops: 22 out of 7168 0% Number of 4 input LUTs: 27 out of 7168 0% Number of bonded IOBs: 6 out of 141 4% Number of GCLKs: 1 out of 8 12% Clock Information: -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clock | BUFGP | 12 | counter_4:Q | NONE | 10 | -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -4 Minimum period: 5.580ns (Maximum Frequency: 179.211MHz) Minimum input arrival time before clock: 2.821ns Maximum output required time after clock: 7.551ns
37 Maximum combinational path delay: No path found PLACE AND ROUTE REPORT: Device Utilization Summary: Number of BUFGMUXs 1 out of 8 12% Number of External IOBs 6 out of 141 4% Number of LOCed IOBs 0 out of 6 0% Number of Slices 18 out of 3584 1% Number of SLICEMs 0 out of 1792 0% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clock_BUFGP | BUFGMUX1| No | 10 | 0.059 | 1.073 | +---------------------+--------------+------+------+------------+-------------+ | counter<4> | Local| | 10 | 2.508 | 3.459 | +---------------------+--------------+------+------+------------+-------------+ All signals are completely routed. Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 74 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1
BACK ANNOTATE- REPORT:
38 # pll.lpc # The constraints in this file were created simply to be viewed. # If you wish to use these constraints, please copy them into your # project's constraint file. If you do not have a project constraints # file yet, please use the "Project->New Source" menu to create one. #PINLOCK_BEGIN #Tue Apr 27 01:30:55 2010 NET "dataout" NET "datain" NET "rx_clock" NET "dcd" NET "clrdcd" NET "clock" #PINLOCK_END SIMULATION: LOC = "P58"; LOC = "P34"; LOC = "P62"; LOC = "P61"; LOC = "P182"; LOC = "P181";
RESULT : Thus the system design using PLL was executed using VHDL coding and the outputs were verified and implemented in FPGA.
39 EX.NO. 4 DATE:11-03-2010
STUDY OF DESIGN OF SIMPLE MICROPROCESSOR
AIM: To develop the source code for simple microprocessor by using VHDL/VEILOG and obtain the simulation, place and route and implementation into FPGA.
ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all the possible combinations of input using test bench.
BLOCK DIAGRAM:
40
BUS
DATA
clk B R0 R3 A
RO in W
ROout . . R3in
R3out
Ain EXT
CONTROL CIRCUIT
FUNC
DONE
41 SPECEFICATIONS: --Design -- Lecturer --Author --VMP No --Version --Simulator : SIMPLE MICROPROCESSOR : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : Xilinx 7.1i : Model Sim
--Description : To Design and implement Simple Microprocessor
VERILOG SOURCE CODE: module processor(data,reset,w,F,clk,Rx,Ry,Done,buswires); input [7:0]data; input reset,w,clk; input [1:0]F,Rx,Ry; output reg [7:0]buswires; output reg Done; reg [7:0]Sum; reg [0:3]Rin,Rout; reg Extern,Ain,Gin,Gout,AddSub; wire [3:0]T; integer k; wire [1:0]count; wire [3:0]I; wire [0:3]Xreg; wire [0:3]Y; wire [7:0]R0,R1,R2,R3,A,G; wire [1:6]Func,FuncReg,Sel; wire clear=reset|Done|(~w & ~count[1] & ~count[0]); upcount counter(clear,clk,count); assign Func={F,Rx,Ry}; wire FRin=w & ~count[1] & ~count[0]; regn functionreg(Func,FRin,clk,FuncReg); defparam functionreg.n=6; assign I=FuncReg[1:2]; dec2to4 decX(FuncReg[3:4],1'b1,Xreg); dec2to4 decY(FuncReg[5:6],1'b1,Y); always @(count,I,Xreg,Y)
42 begin Extern=1'b0; Done =1'b0; Ain =1'b0; Gin =1'b0; Gout =1'b0; AddSub=1'b0; Rin =4'b0; Rout =4'b0; case(count) 2'b00:; 2'b01: case(I) 2'b00:begin//load Extern=1'b1; Rin =Xreg; Done =1'b1; end 2'b01:begin//move Rout=Y; Rin =Xreg; Done=1'b1; end default:begin//add,sub Rout=Xreg; Ain=1'b1; end endcase endcase end
//regctrl always @(I,T,Xreg,Y) begin for(k=0;k<4;k=k+1) begin Rin[k]=((I[0]|I[1])&T[1]& Xreg[k])|((I[2]|I[3])&T[3]&Xreg[0]); Rout[k]=(I[1]&T[1] &Y[k])|(I[2]|I[3])&((T[1] & Xreg[k])|(T[2] & Y[k])); end end trin tri_ext(data,Extern,buswires);
43 regn reg_0(buswires,Rin[0],clk,R0); regn reg_1(buswires,Rin[1],clk,R1); regn reg_2(buswires,Rin[2],clk,R2); regn reg_3(buswires,Rin[3],clk,R3); trin tri_0(R0,Rout[0],buswires); trin tri_1(R1,Rout[1],buswires); trin tri_2(R2,Rout[2],buswires); trin tri_3(R3,Rout[3],buswires); regn reg_A(buswires,Ain,clk,A); //alu always @(AddSub,A,buswires) begin if(!AddSub) Sum=A+buswires; else Sum=A-buswires; end regn reg_G(Sum,Gin,clk,G); trin tri_g(G,Gout,buswires); endmodule module regn(R,Rin,clk,Q); parameter n=8; input [n-1:0]R; input Rin,clk; output reg [n-1:0]Q; always @(posedge clk) if(Rin) Q<=R; endmodule module trin(Y,E,F); parameter n=8; input [n-1:0]Y; input E; output wire [n-1:0]F; assign F=E?Y:'bz; endmodule module upcount(clear,clk,Q); input clear,clk;
44 output reg[1:0]Q; always @(posedge clk) if(clear) Q<=0; else Q<=Q+1; endmodule module dec2to4(W,Y,En); input [1:0]W; input En; output [0:3]Y; reg[0:3]Y; always@(W,En) begin if(En==0) Y=4'b0000; else case(W) 0:Y=4'b1000; 1:Y=4'b0100; 2:Y=4'b0010; 3:Y=4'b00001; endcase end endmodule VHDL SOURCE CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity proc is port ( data : in std_logic_vector(7 downto 0); reset, w, clock : in std_logic; f, rx, ry : in std_logic_vector(1 downto 0); done : buffer std_logic; buswires : inout std_logic_vector(7 downto 0)); end proc; architecture Behavioral of proc is
45 signal x, y, rin, rout : std_logic_vector(0 to 3); signal clear, high, addsub : std_logic; signal extern, ain, gin, gout, frin : std_logic; signal count, zero, t, i : std_logic_vector(1 downto 0); signal r0, r1, r2, r3 : std_logic_vector(7 downto 0); signal a, sum, g : std_logic_vector(7 downto 0); signal s, funcreg, sel : std_logic_vector(1 to 6); begin zero <= "00"; high <= '1'; clear <= reset or done or ((not w) and (not t(1)) and (not t(0))); counter : upcount port map(clear, clock, count); t <= count; func <= f & rx & ry; frin <= w and (not t(1)) and (not t(0)); functionreg : regn generic map(n => 6) port map(func, frin, clock, funcreg); i <= funcreg( 1 to 2); decx : dec2to4 port map(funcreg( 3 to 4), high, x); decy : dec2to4 port map(funcreg( 5 to 6), high, y); controlsignals : process(t, i, x, y) begin extern <= '0'; done <= '0'; ain <= '0'; gin <= '0'; gout <= '0'; addsub <= '0'; rin <= "0000"; rout <= "0000"; case t is when "00" => -- no signals asserted in time step t0 when "01" => -- define signals asserted in time step t1 case i is when "00" => -- load extern <= '1'; rin <= x; done <= '1'; when "01" => -- move rout <= y; rin <= x; done <= '1'; when others => -- add, sub rout <= x; ain <= '1'; end case;
46 when "10" => -- define signals asserted in time step t2 case i is when "10" => -- add rout <= y; gin <= '1'; when "11" => -- sub rout <= y; addsub <= '1'; gin <= '1'; when others => -- load, move rout <= x; ain <= '1'; end case; when others => -- define signals asserted in time step t3 case i is when "00" => -- load when "01" => -- move when others => -- add, sub gout <= '1'; rin <= x; done <= '1'; end case; end case; end process; reg0 : regn port map (buswires, rin(0), clock, r0); reg1 : regn port map (buswires, rin(1), clock, r1); reg2 : regn port map (buswires, rin(2), clock, r2); reg3 : regn port map (buswires, rin(3), clock, r3); rega : regn port map (buswires, ain, clock, a); alu : with addsub select sum <= a + buswires when '0', a - buswires when others; regg : regn port map (sum, gin, clock, g); sel <= rout & gout & extern; with sel select buswires <= r0 when "100000", r1 when "010000", r2 when "001000", r3 when "000100", g when "000010", data when others; end Behavioral; DECODER 2 TO 4
47 entity dec2to4 is Port ( w : in std_logic_vector(1 downto 0); en : in std_logic; y : out std_logic_vector(0 to 3)); end dec2to4; architecture Behavioral of dec2to4 is signal enw : std_logic_vector(2 downto 0); begin enw <= en & w; with enw select y <= "1000" when "100", "0100" when "101", "0010" when "110", "0001" when "111", "0000" when others; end Behavioral; SIMULATION OUTPUT:
REGN entity regn is generic (n : integer := 8); Port ( r : in std_logic_vector(n-1 downto 0); rin, clock : in std_logic; q : out std_logic_vector(n-1 downto 0)); end regn; architecture Behavioral of regn is begin process begin wait until clock'event and clock = '1';
48 if rin = '1' then q <= r; end if; end process; end Behavioral; SIMULATION OUTPUT
UPCOUNT library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity upcount is port ( clear, clock : in std_logic; q : buffer std_logic_vector(1 downto 0)); end upcount; architecture Behavioral of upcount is begin upcount : process(clock) begin if(clock'event and clock = '1') then if clear = '1' then q <= "00"; else q <= q + '1'; end if; end if; end process; end Behavioral; SIMULATION OUTPUT:
49 SYNTHESIZE REPORT: Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of bonded IOBs: Number of GCLKs: Clock Information: -----------------------------------+------------------------+-------+ Clock Signal clock counter_4:Q Timing Summary: --------------Speed Grade: -4 Minimum period: 5.580ns (Maximum Frequency: 179.211MHz) Minimum input arrival time before clock: 2.821ns Maximum output required time after clock: 7.551ns Maximum combinational path delay: No path found | Clock buffer(FF name) | Load | | BUFGP | NONE | 12 | | -----------------------------------+------------------------+-------+ | 10 17 out of 3584 0% 0% 0% 4% 22 out of 7168 27 out of 7168 6 out of 1 out of 141 8
12%
-----------------------------------+------------------------+-------+
RESULT : Thus the source code for simple microprocessor by using VHDL/VERILOG was designed and obtained the simulation, place and route and verified using FPGA.
50
EX.NO. 5 DATE: 18-3-2010 AIM:
DESIGN OF TRAFFIC LIGHT CONTROLLER
To develop the source code for traffic light controller by using VHDL/VERILOG and obtain the simulation, place and route and implementation into FPGA. TOOLS REQUIRED: Xilinx-7.1 Software package ModelSim XE II 5.7g FPGA kit-Spartan-3 Power cord
LOGIC DIAGRAM:
51
ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all the possible combinations of input using test bench. SPECEFICATIONS: --Design -- Lecturer --Author --VMP No --Version --Simulator : TRAFFIC LIGHT CONTROLLER : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : Xilinx 7.1i : Model Sim
--Description : To Design implement Traffic Light Controller
VHDL SOURCE CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
52 entity tlc is port(clk,rst : in std_logic; gr1, gr2, gr3 : out std_logic_vector(1 downto 0); rd1, rd2, rd3, yl1, yl2, yl3 : out std_logic); end tlc; architecture Behavioral of tlc is type state is (s1, s2, s3); signal prstate : state; signal count : integer := 0; begin process (clk, rst) begin if (clk = '1' and clk'event) then if (rst = '1') then prstate <= s1; else case prstate is when s1 => if (count =4) then yl1 <= '1'; yl2 <= '0'; yl3 <= '0'; count <= 0; prstate <= s2; else gr1 <= "11"; gr2 <= "00"; gr3 <= "10"; rd1 <= '0'; rd2 <= '1'; rd3 <= '1'; yl1 <= '0'; yl2 <= '0'; yl3 <= '0'; prstate <= s1; count <= count +1; end if; when s2 => if (count =4) then
53 yl1 <= '0'; yl2 <= '1'; yl3 <= '0'; count <= 0; prstate <= s3; else gr1 <= "10"; gr2 <= "11"; gr3 <= "00"; rd1 <= '1'; rd2 <= '0'; rd3 <= '1'; yl1 <= '0'; yl2 <= '0'; yl3 <= '0'; prstate <= s2; count <= count +1; end if; when s3 => if (count =4) then yl1 <= '0'; yl2 <= '0'; yl3 <= '1'; count <= 0; prstate <= s1; else gr1 <= "00"; gr2 <= "01"; gr3 <= "11"; rd1 <= '1'; rd2 <= '1'; rd3 <= '0'; yl1 <= '0'; yl2 <= '0'; yl3 <= '0'; prstate <= s3; count <= count +1; end if; end case; end if; end if; end process; end Behavioral; VERILOG SOURCE CODE : module traffic(clk, rst, gr1, gr2, gr3, rd1, rd2, rd3, yl1, yl2, yl3); input clk, rst; output[1:0] gr1, gr2, gr3; output rd1, rd2, rd3, yl1, yl2, yl3; reg [1:0] gr1, gr2, gr3;
54 reg rd1, rd2, rd3, yl1, yl2, yl3; parameter s1=0, s2=1, s3=2; reg[0:1] ps; reg [2:0]count ; initial begin ps=s1; end always @ ( clk or rst) begin if ( rst == 1'b1) ps = s1; else case (ps) s1 : if ( count ==3'b100 ) begin yl1 = 1'b1; yl2 = 1'b0; yl3 = 1'b0; count = 3'b000; ps = s2; end else begin gr1 = 2'b11; gr2 = 2'b00; gr3 = 2'b10; rd1 = 1'b0; rd2 = 1'b1; rd3 = 1'b1; yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0; ps = s1; count = count + 3'b001; end s2 : if ( count ==3'b100 ) begin yl1 = 1'b0; yl2 = 1'b1; yl3 = 1'b0; count = 3'b000; ps = s3; end else begin gr1 = 2'b10; gr2 = 2'b11; gr3 = 2'b00; rd1 = 1'b1; rd2 = 1'b0; rd3 = 1'b1; yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0; ps = s2; count = count + 3'b001; end s3 : if ( count ==3'b100 ) begin yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b1; count = 3'b000;
55 ps = s1; end else begin gr1 = 2'b00; gr2 = 2'b01; gr3 = 2'b11; rd1 = 1'b1; rd2 = 1'b1; rd3 = 1'b0; yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0; ps = s3; count = count + 3'b001; end endcase end endmodule
SYNTHESIS RTL SCHEMATIC :
SYNTHESIS TECHNOLOGY SCHEMATIC :
56
OUTPUT SIMULATION WAVEFORM:
57 SYNTHESIS REPORT : Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: 46 out of 3584 1% Number of Slice Flip Flops: 46 out of 7168 0% Number of 4 input LUTs: 61 out of 7168 0% Number of bonded IOBs: 14 out of 141 9% Number of GCLKs: 1 out of 8 12% Selected Device : 3s400tq144-5 TIMING REPORT Clock Information: -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 46 | -----------------------------------+------------------------+-------+ Timing Summary: Speed Grade: -5 Minimum period: 6.767ns (Maximum Frequency: 147.767MHz) Minimum input arrival time before clock: 5.509ns Maximum output required time after clock: 6.280ns Maximum combinational path delay: No path found PLACE AND ROUTE REPORT: Device Utilization Summary: Number of BUFGMUXs Number of External IOBs Number of LOCed IOBs 1 out of 8 12% 14 out of 141 9% 0 out of 14 0%
Number of Slices 37 out of 3584 1% Number of SLICEMs 0 out of 1792 0% All signals are completely routed. Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage: 75 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1
58
RESULT : Thus the traffic light controller was designed and executed using VHDL & Verilog coding and the outputs were verified by implementing in FPGA kit.
59
EX.NO. 6 DATE:25-3-2010 AIM:
IMPLEMENTATION OF ELEVATOR CONTROLLER USING EMBEDDED MICROCONTROLLER
To develop the source code for elevator by using C/ Assembly language using RIDE IDE and to verify its operation and implementing into microcontroller. TOOLS REQUIRED: Elevator kit Keyboard Interfacing bus 8051-Microcontroller Power cord
PROCEDURE: Step 1: Connect the microcontroller device with the keyboard and elevator kit. Step 2: Design a program for the following condition using 8051 microcontroller. i.Lift 1 moves from ground floor to fourth floor . ii.lift 2 position in the seventh floor iii. After reaching its position doors should be opened. Step 3: Type the corresponding code by initializing with starting address(4100) Step 4: Execute the program by RST GO-->Starting address(4100)Execute Step 5: Observe the movement of lift through the LED and door opening condition using buzzer.
60
FLOW CHART
START
KEEP THE LIFT IN UNKNOWN POSITION A

IS THRE ANY VALID INPUT
NO
YES GET THE INPUT
MOVE THE LIFT TO THE REQUIRE FLOOR FROM CURRENT FLOOR
NO
YES
GET THE DESTINATION FLOOR NO.
NO
INDICATE ERROR YES
UPDATE THE LIFT POSITIOM
MOVE THE LIFT TO THE DESTINATION FLOOR
61
PROGRAM: --Design : ELEVATOR CONTROLLER --Description : To implement Elevator Controller -- Lecturer : P.Karpagam --Author --VMP No --Tool : K.SANGEETHA LAKSHMI : VMP-66 : 8051-Micro-controller
org mov mov movx call movx mov mov movx mov mov movx call mov mov movx call mov movx call mov movx call
4100h a,#03h dptr,#0ffcch @dptr,a delay @dptr,a a,#80h dptr,#0ffc0h @dptr,a a,#01h dptr,#0ffc4h @dptr,a delay dptr,#0ffc0h a,#40h @dptr,a delay a,#20h @dptr,a delay a,#10h @dptr,a delay
62 mov a,#08h movx @dptr,a call delay mov a,#0bh mov dptr,#0ffcch movx @dptr,a call delay mov a,#03h movx @dptr,a here: sjmp here delay: mov 31h,#0ffh mov 30h,#0ffh d12: call delay1ms d2: djnz 30h,d2 djnz 31h,d12 ret delay1ms:mov tl0,#17h mov th0,#0fch call t0delay ret t0delay: mov a,tmod anl a,#0f0h orl a,#01 mov tmod,a setb tr0 jnb tf0,$ clr tr0 clr tf0 ret end
63
ADDRESS 4100 4100 4102 4105 4106 4109 410B 410C 410E 4111 4112 4114 4117 4118 411B 411E 4120 4121 4124 4126 4127 412A 412C 412D 4130 4132 4133 4135 4138 4139 413C 413E 413F 413F 4141 4141 4144
OP-CODE 74 03 90 FF CC F0 12 41 41 74 02 F0 7480 90 FF C0 F0 74 01 90 FF C4 F0 12 41 41 90 FF C0 74 40 F0 12 41 41 74 20 F0 12 41 41 74 10 F0 12 41 41 74 08 F0 74 0B 90 FF CC F0 12 41 41 74 03 F0 80 FE 75 31 0A 75 30 64
MNEMONICS org 4100H start: mov a,#03h mov dptr,#stat_ou movx @dptr,a call delay mov a,#02h movx @dptr,a mov a,#80h mov dptr,#lift1 movx @dptr,a mov a,#01h mov dptr,#lift2 movx @dptr,a call delay mov dptr,#lift1 mov a,#40h movx @dptr,a call delay mov a,#20h movx @dptr,a call delay mov a,#10h movx @dptr,a call delay mov a,#08h movx @dptr,a mov a,#0bh mov dptr,#stat_ou movx @dptr,a call delay mov a,#03h movx @dptr,a here: sjmp here delay: mov count1,#10 mov count,#100
DESCRIPTION ;default open doors ;of lift1 & lift2 ;close door of lift1 ;indicates lift1 is ;in gnd floor ;indicates lift2 is ;in 7th floor
;beep for door open
;open doors
;for 1 seconds delay
64 4144 4147 4147 414A 414D 4150 4151 4151 4154 4157 415A 415B 415B 415D 415F 4161 4163 4165 12 41 51 D5 30 FA D5 31 F4 22 75 8A 17 75 8C FC 12 41 5B 22 E5 89 54 F0 44 01 F5 89 D2 8C 30 8D FD t0delay: mov a,tmod anl a,#0f0h orl a,#t0_m1 mov tmod,a setb tr0 jnb tf0,$ d12: call delay1ms d2: djnz count,d2 djnz count1,d12 ret delay 1 ms: mov t10,#017h mov th0,#0fch call t0delay
1 Milli second ;TL0=17h, The low byte of timer() ;TH0=FCh, The high byte of timer() ;Activate the timer0, ;and wait upto
; 2 Timer 0, mode 1 ; 1 Start the timer 0 ;OFFFF-(16 BIT TIMER VALUE)+1
4168 416A 416C
C2 8C C2 8D 22
clr tr0 clr tf0 ret end
;Monitor timer flag 0 ;1 Stop the timer 0 ;1 Clear timer flag 0 ;1 Return from subroutine
RESULT: Thus the program for elevator was written using RIDE IDE and the program was loaded successfully and implemented in the kit and LED indication is verified by using PIC Embedded Trainer. EX.NO. 7 DATE: 1-4-2010
IMPLEMENTATION OF MODEL TRAIN CONTROLLER USING EMBEDDED MICROCONTROLLER
AIM:
65 To develop the source code for model train by using C/ Assembly language using RIDE IDE and to verify its operation and implementing into microcontroller. TOOLS REQUIRED: PIC-Microcontroller kit MPLAB-IDE 7.41 Win talk PIC-ISP Data cable Power cord
PROCEDURE: Step 1: Start MPLAB IDE by double clicking that icon.
Step 2: Select PIC 16F877A as target device in MPLAB device selection.
Step 3: Select MPLAB CCS C compiler as the language tool. C:\ Program files PICC CCS C (Code Composer Studio) Step 4: Create a project using the project wizard
66 Project Project Wizard Next Next Finish.
Step 5: Create a new C file and write the coding for RTC and add it to the project.
Step 6: Save the program or file with extension .c eg: me.c
Step 7: Add Library file and linker file for the corresponding PIC in the project. Right click in Source file Add file Open me.c
67
Step 8: Project Select Language Tool Suite Ok Project Select Language Tool Location Ok Project Build options Click file name me.c
Step 9: Enable Alternate settings + pe Ok
68 Project Compile Build all Ok
Step 10: Verify the output in MPLAB IDE through its registers and ports options.
Step 11: Connect the target device with PIC 16F877A to the COM port in the system. Step 12: Program the Hex file in the target device. Step 13: Double click the icon PIC ISP
69 COM Port COM 1 Communication Port Browse Select file (me) Download Up Direction Reset Download Succeeded
70 FLOW CHART:
START
TRAIN IN STARTING POINT TRAIN MOVES FROM STATION 2 TO STATION 1 NO
IF SWITH 1 IS UP DIRECTION
YES
TRAIN MOVES FROM STATION 1 TO STATION 2
IF SIGNAL IS YELLOW OR GREEN
NO
TRAIN STOPS
YES
TRAIN MOVES
LEVEL CROSSING
NO YES
GATE OPENED
GATE CLOSED
71
PROGRAM: --Design : MODEL TRAIN CONTROLLER
--Description : To implement Model Train Controller -- Lecturer --Author --VMP No : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66
--Designation : Student --Version : MPLAB IDE -7.41
--THIS PROGRAM GET THE DATA FROM THE SW1(UP FOR ON, DOWN FOR OFF) & SW2(UP FOR FORWARD, DOWN FOR REVERSE) AND RORATE THE TRAIN. ALSO GET THE DATA FROM THE SENSOR AND PUT THE SIGNALS--
#include <16F877A.H> #include <stdio.h> #use delay(clock=20000000) #use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7) #use I2C(MASTER,sda=PIN_C4,scl=PIN_C3) unsigned char data,a,b,c; unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55}; //led0-led3 selector for forward direction. unsigned char ls1[]={0x55,0x15,0x05,0x01,0x00,0x00,0x40,0x50,0x54,0x55}; //led0-led3 selector for reverse direction. unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce,0x0c0}; unsigned char sel1[]={0x0ce,0xcc,0xca,0xc8,0xc6,0xc4,0xc2,0x0c0,0xce};
72 unsigned char i,i1,j,k=0x15,senout=0x00,senout1=0x00,senout2,senout3,buzzon=0; void crossingon(); void crossingoff(); void init(); void initbuf(); void sensor(); void sensor1(); void station1forward(); void station2forward(); void station1reverse(); void station2reverse(); void sw(); void sw1(); void reverse(); void forward(); void main() { init(); initbuf(); while(1) { start1: for(j=0x00;j<0x09;j++) { i1=0x05; for(i=0x00;i<0x09;i++) { start: if(i<=0x04)
73 { i2c_start(); i2c_write(sel[j]); //write the address for the device selection. i2c_write(k); i2c_write(ls0[i]); i2c_write(ls0[i1]); i1++; printf("Rotate movement here\n"); } if(j==0x08) goto start1; stoptrain: sw(); if(c != 0x0) goto stoptrain; if(i>=0x05) { i2c_start(); i2c_write(sel[j]); i2c_write(k+1); i2c_write(ls0[i-0x04]); i2c_stop(); i2c_start(); i2c_write(sel[j+1]); i2c_write(k); i2c_write(ls0[i1-0x04]); i1++; printf("Rotate movement here\n"); } i2c_stop(); stoptrain1: //read the data from the buffer.// //check for sw1 & sw2 is high.// //start the next rotation in the train. //write the register address. //write the data for lso register. //write the data for ls1 register.
74 sw(); if((c != 0x0)) goto stoptrain1; sensor(); if(senout == 0x00) goto stop1; senout++; if(senout < 0x06) delay_ms(200); else if(senout == 0x06) { delay_ms(0x2000); initbuf(); output_d(0x10); //glow the yellow led for station1 in forward. output_low(PIN_E2); output_high(PIN_E2); delay_ms(1000); initbuf(); output_d(0x08); //glow the green led for station1 in forward. output_low(PIN_E2); output_high(PIN_E2); delay_ms(100); } if((senout > 0x06) && (senout <=0x0a)) delay_ms(200); stop1: if(senout1 == 0x00) //wait some delay in station1. //check the station1. //read the data from the buffer.// //check for sw1 & sw2 is high.//
75 goto stop2; senout1++; if(senout1 < 0x06) delay_ms(200); else if(senout1 == 0x06) { delay_ms(0x2000); initbuf(); output_d(0x04);//glow the yellow led for station2 in forward. output_low(PIN_E1); output_high(PIN_E1); delay_ms(1000); initbuf(); output_d(0x02); //glow the green led for station2 in forward. output_low(PIN_E1); output_high(PIN_E1); delay_ms(100); } if((senout1 > 0x06) && (senout1 <=0x0a)) delay_ms(200); stop2: if(i != 0x08) delay_ms(200); /* if(buzzon == 0x01) { output_low(PIN_E0); delay_ms(10); output_high(PIN_E0); //wait some delay in station2. //check the station2.
76 delay_ms(10); }*/ } } } } void init() { for(i=0;i<0x08;i++) { i2c_start(); i2c_write(sel[i]); i2c_write(0x15); i2c_write(0x00); i2c_write(0x00); i2c_stop(); printf("Clear the display here\n"); } } void sensor() { output_low(PIN_B4); a=input_d(); output_high(PIN_B4); b = a; b = b & 0x02; if(b == 0x02) crossing. { //sensor3 is set to low(enable) for close the level //get the data from the buffer.
77 do{ output_low(PIN_B4); a=input_d(); output_high(PIN_B4); c = a; c = (c & 0x80); }while(c != 0x0); crossingon(); } b = a; b = b & 0x04; if(b == 0x04) crossing. crossingoff(); b = a; b = b & 0x08; if(b == 0x08) station2forward(); b = a; b = b & 0x20; if(b == 0x20) station1forward(); } void crossingon() { output_low(PIN_B3); //sensor1 is set to low(enable). //sensor5 is set to low(enable). //sensor4 is set to low(enable) for open the level //get the data from the buffer.
78 output_d(0xF0); output_low(PIN_E1); output_high(PIN_E1); output_d(0xFF); output_low(PIN_E0); output_high(PIN_E0); output_d(0x00); output_low(PIN_E2); output_high(PIN_E2); output_low(PIN_B3); buzzon = 0x01; } void crossingoff() { initbuf(); buzzon = 0x0; } void station1forward() { initbuf(); output_d(0x20); output_low(PIN_E2); output_high(PIN_E2); //glow the red led for station1 in forward.
79 delay_ms(100); station1. senout=0x01; } void station2forward() { initbuf(); output_d(0x08); output_low(PIN_E1); output_high(PIN_E1); delay_ms(100); station1. senout1 = 0x01; } void sw() { output_low(PIN_B4); a=input_d(); output_high(PIN_B4); b=a; b= b & 0x40; c=a; c= (c & 0x80); if(b == 0x40) //check for switch2. //check for switch1. //get the data from the buffer. //decrement the speed for stop the train in //glow the red led for statio2 in forward. //decrement the speed for stop the train in
80 reverse(); } void reverse() { senout2 = 0x00, senout3 = 0x00; init(); initbuf(); buzzon = 0x0; while(1) { start3: for(j=0x00;j<0x09;j++) { i1=0x05; for(i=0x00;i<0x09;i++) { start4: if(i<=0x04) { i2c_start(); i2c_write(sel1[j]); //write the address for the device selection. i2c_write(0x06);//write the register address. i2c_write(ls1[i]);//write the data for lso register. i2c_start(); i2c_write(sel1[j]); /write the address for the device selection. i2c_write(0x05); i2c_write(ls1[i1]); i1++; printf("Rotate one movement here\n"); }
//write the register address. //write the data for ls1 register.
81 if(j==0x08) goto start3; stoptrain2: sw1(); // // if(c != 0x0) goto stoptrain2; if(i>=0x05) { i2c_start(); i2c_write(sel1[j]); i2c_write(0x05); i2c_write(ls1[i-0x04]); i2c_stop(); i2c_start(); i2c_write(sel1[j+1]); i2c_write(0x06); i2c_write(ls1[i1-0x04]); i1++; printf("Rotate one movement here\n"); } stoptrain3: sw1(); if((c != 0x0)) goto stoptrain3; sensor1(); if(senout2 == 0x00) goto stop3; senout2++;
//read the data from the buffer.// //read the data from the buffer. //start the next rotation in the train.
//check for sw1 & sw2 is high.
//check for sw1 & sw2 is high.//
82 if(senout2 < 0x06) delay_ms(200); else if(senout2 == 0x06) { delay_ms(0x2000); initbuf(); output_d(0x80);//glow the yellow led for station2 in reverse. output_low(PIN_E2); output_high(PIN_E2); delay_ms(1000); initbuf(); output_d(0x40);//glow the green led for station2 in reverse. output_low(PIN_E2); output_high(PIN_E2); delay_ms(100); } if((senout2 > 0x06) && (senout2 <=0x0a)) delay_ms(200); stop3: if(senout3 == 0x00) goto stop4; senout3++; if(senout3 < 0x06) delay_ms(200); else if(senout3 == 0x06) { delay_ms(0x2000); //wait some delay in station1. //check the station1.
//wait some delay in station2 in reverse direction.
//check the station2 in reverse direction.
83 initbuf(); output_d(0x02);//glow the yellow led for station1 in reverse. output_low(PIN_E2); output_high(PIN_E2); delay_ms(1000); initbuf(); output_d(0x01); //glow the green led for station1 in reverse. output_low(PIN_E2); output_high(PIN_E2); delay_ms(100); } if((senout3 > 0x06) && (senout3 <=0x0a)) delay_ms(200); stop4: if(i != 0x08) delay_ms(200); /* if(buzzon == 0x01) { output_low(PIN_E0); delay_ms(10); output_high(PIN_E0); delay_ms(10); }*/ } } } } void sensor1()
84 { output_low(PIN_B4); a=input_d(); output_high(PIN_B4); b = a; b = b & 0x10; if(b == 0x10) station2reverse(); b = a; b = b & 0x04; if(b == 0x04) crossing. { do{ output_low(PIN_B4); a=input_d(); output_high(PIN_B4); c = a; c = (c & 0x80); }while(c != 0x0); crossingon(); } b = a; b = b & 0x02; if(b == 0x02) crossingoff(); b = a; //sensor4 is set to low(enable) for open the level crossing. //get the data from the buffer. //sensor3 is set to low(enable) for close the level //sensor6 is set to low(enable). //get the data from the buffer.
85 b = b & 0x01; if(b == 0x01) station1reverse(); } void station1reverse() { initbuf(); output_d(0x04); output_low(PIN_E2); output_high(PIN_E2); delay_ms(100); senout3=0x01; } void station2reverse() { initbuf(); output_d(0x01); output_low(PIN_E1); output_high(PIN_E1); delay_ms(100); senout2=0x01; } void sw1() { output_low(PIN_B4); a=input_d(); //get the data from the buffer. //decrement the speed for stop the train in station1. //glow the red led for statio2 in forward. //decrement the speed for stop the train in station1. //glow the red led for station1 in forward. //sensor2 is set to low(enable).
86 output_high(PIN_B4); b=a; b= b & 0x40; c=a; c= c & 0x80; } void initbuf() { output_d(0x00); output_low(PIN_E1); output_high(PIN_E1); output_d(0x00); output_low(PIN_E2); output_high(PIN_E2); output_d(0x00); output_low(PIN_E0); output_high(PIN_E0); output_low(PIN_B3); } //noy glow the station2 signal. //noy glow the station2 signal. //noy glow the station2 signal. //check for switch2. //check for switch1.
PROGRAM FOR STATION1 TO STATION 2; /***************************************************************************** THIS PROGRAM MOVE THE TRAIN FROM THE STATION1 TO STATION2. IF THE SWITCH1 IS OFF POSITION, THE TRAIN IS STOP.
87 ***************************************************************************** * #include <16F877A.H> #use delay(clock=20000000) #use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7) #use I2C(MASTER,sda=PIN_C4,scl=PIN_C3) unsigned char data,a,b,c; int i,j,i1,k=0x15,j1,j2; unsigned char ls0[]={0x55,0x54,0x50,0x40,0x00,0x00,0x01,0x05,0x15,0x55}; //led0-led3 selector for forward direction. unsigned char sel[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0x0c0}; unsigned char sel1[]={0x0c0,0x0c2,0xc4,0xc6,0xc8,0xca,0xcc,0xce}; void init(); void initbuf(); void sensor(); void station2forward(); void crossingon(); void crossingoff(); void main() { init(); initbuf(); while(1) { start1: for(j=0X00;j<0X07;j++) { i1=0x05;
88 for(i=0x00;i<0x09;i++) { start: if(i<=0x04) { i2c_start(); i2c_write(sel[j]); //write the address for the device selection. i2c_write(k); i2c_write(ls0[i]); i2c_write(ls0[i1]); i1++; } if((j == 0x05) && (i >= 0x00)) //start the next rotation in the train. station2forward(); sensor(); if((b != 0x0)) goto start; start3: if(i>=0x05) { i2c_start(); i2c_write(sel[j]); i2c_write(k+1); i2c_write(ls0[i-0x04]); i2c_stop(); i2c_start(); i2c_write(sel[j+1]); i2c_write(k); i2c_write(ls0[i1-0x04]); i1++; } //check for sw1 & sw2 is high. || (c == 0x80) //write the register address. //write the data for lso register. //write the data for ls1 register.
89 if((j == 0x05) && (i == 0x04)) //start the next rotation in the train. goto start3; sensor(); if((b != 0x0)) goto start; if(i != 0x08) delay_ms(200); } } } } void init() { for(i=0;i<0x08;i++) { i2c_start(); i2c_write(sel1[i]); i2c_write(0x15); i2c_write(0x00); i2c_write(0x00); i2c_stop(); } } void initbuf() { output_d(0x00); output_low(PIN_E1); output_high(PIN_E1); output_d(0x00); output_low(PIN_E2); //noy glow the station2 signal. //noy glow the station2 signal. //check for sw1 & sw2 is high. || (c == 0x80)
90 output_high(PIN_E2); output_d(0x00); output_low(PIN_E0); output_high(PIN_E0); } void station2forward() { output_d(0x08); output_low(PIN_E1); output_high(PIN_E1); delay_ms(600); } void sensor() { output_low(PIN_B4); a=input_d(); output_high(PIN_B4); b = a; b = b & 0x02; if(b == 0x02) crossingon(); b = a; b = b & 0x04; if(b == 0x04) crossingoff(); b=a; b= b & 0x80; } void crossingon() //check for switch1. //sensor4 is set to low(enable) for open the level crossing. //sensor3 is set to low(enable) for close the level crossing. //get the data from the buffer. //decrement the speed for stop the train in station1. //glow the red led for statio2 in forward. //noy glow the station2 signal.
91 { output_d(0xF0); output_low(PIN_E1); output_high(PIN_E1); output_d(0xFF); output_low(PIN_E0); output_high(PIN_E0); output_d(0x00); output_low(PIN_E2); output_high(PIN_E2); } void crossingoff() { initbuf(); }
RESULT: Thus the program for MODEL TRAIN CONTROLLER was written using MP-LAB IDE and the program was loaded successfully and implemented in the kit and verified by using PIC Embedded Trainer.
92 EX.NO. 8 DATE:8-4-2010
IMPLEMENTATION OF ALARM CLOCK CONTROLLER USING EMBEDDED MICROCONTROLLER
AIM: To write a program for designing a real time clock by using PIC 16F877A device using MPLAB IDE and implementing the same to display in LCD with alarm buzzer and LED indication. TOOLS REQUIRED: PIC-Microcontroller kit MPLAB-IDE 7.41 Win talk PIC-ISP Data cable Power cord
PROCEDURE: Step 1: Start MPLAB IDE by double clicking that icon. Step 2: Select PIC 16F877A as target device in MPLAB device selection. Step 3: Select MPLAB CCS C compiler as the language tool. C:\ Program files PICC CCS C (Code Composer Studio) Step 4: Create a project using the project wizard Project Project Wizard Next Next Finish. Step 5: Create a new C file and write the coding for RTC and add it to the project. Step 6: Save the program or file with extension .c eg: ka.c Step 7: Add Library file and linker file for the corresponding PIC in the project.
93 Right click in Source file Add file Open ka.c Step 8: Project Select Language Tool Suite Ok Project Select Language Tool Location Ok Project Build options Click file name ka.c Step 9: Enable Alternate settings + pe Ok Project Compile Build all Ok Step 10: Verify the output in MPLAB IDE through its registers and ports options. Step 11: Connect the target device with PIC 16F877A to the COM port in the system. Step 12: Program the Hex file in the target device.
Step 13: Double click the icon PIC ISP COM Port COM 1 Communication Port Browse Select file (ka) Download Up Direction Reset Download Succeeded Step 14: Double click the icon WINX TALK Open Port Talk Talk Window Down Direction Reset Output. Serial no: 101101 Step 15: Verify the real time clock output in the kit and notice the alarm (LED indication)
94
FLOWCHART: START
INITIATE THE CLOCK TIME
SET THE TIME FOR ALARM
WHEN TIME=ALARM TIME
ALARM ON
STOP
PROGRAM: --Design -- Lecturer --Author --VMP No : ALARM CLOCK CONTROLLER : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 --Description : To implement Alarm Clock Controller
95 --Version : MPLAB IDE -7.41
# include<16F877A.H> # use delay(clock=20000000) #use rs232(baud=9600,xmit=PIN_C6, rcv=PIN_C7) #use I2C(MASTER, sda=PIN_C4, scl=PIN_C3) unsigned int time[]={0x30,0x55,0x12}; unsigned int readtime[0x03]; unsigned long int hour,second,minute; int i,j; void set_rtc_time() { for(i=2;i<=4;i++) { i2c_start(); i2c_write(0xa0 | 0x00); i2c_write(i); i2c_write(time[(i-2)]); i2c_stop(); } } void get_rtc_time() { for(i=2;i<=4;i++) { i2c_start(); i2c_write(0xa0); i2c_write(i); i2c_start(); i2c_write(0xa0 | 0x01); readtime[(i-2)]=i2c_read(0); i2c_stop(); } } void alarm_set() {
96 output_b(0xff); if(minute==0x56) { if((second>=0x05) && (second<=0x20)) { output_high(PIN_B0); delay_ms(10); output_low(PIN_B0); delay_ms(10); } } } void main() { set_rtc_time(); while(1) { get_rtc_time(); alarm_set(); hour=readtime[2]; delay_ms(10); minute=readtime[1]; delay_ms(10); second=readtime[0]; delay_ms(10); printf("Time:%x:%x:%x\n\r", readtime[2],readtime[1],readtime[0]); } }
RESULT:
97 Thus the program for PIC16F877A device was written using MPLAB IDE for the design of real time clock and the same was verified by display in LCD with alarm buzzer and LED indication using PIC Embedded Trainer. EX.NO. 9 DATE:15-4-2010
IMPLEMENTATION OF LCD DISPLAY USING PIC MICROCONTROLLER
AIM: To write a program for LCD display by using PIC 16F877A device using MPLAB IDE and implementing it in microcontroller kit. TOOLS REQUIRED: PIC-Microcontroller kit MPLAB-IDE 7.41 Win talk PIC-ISP Data cable Power cord
PROCEDURE: Step 1: Start MPLAB IDE by double clicking that icon. Step 2: Select PIC 16F877A as target device in MPLAB device selection. Step 3: Select MPLAB CCS C compiler as the language tool. C:\ Program files PICC CCS C (Code Composer Studio) Step 4: Create a project using the project wizard Project Project Wizard Next Next Finish. Step 5: Create a new C file and write the coding for RTC and add it to the project.
98 Step 6: Save the program or file with extension .c eg: ka.c Step 7: Add Library file and linker file for the corresponding PIC in the project. Right click in Source file Add file Open ka.c Step 8: Project Select Language Tool Suite Ok Project Select Language Tool Location Ok Project Build options Click file name ka.c Step 9: Enable Alternate settings + pe Ok Project Compile Build all Ok Step 10: Verify the output in MPLAB IDE through its registers and ports options. Step 11: Connect the target device with PIC 16F877A to the COM port in the system. Step 12: Program the Hex file in the target device. Step 13: Double click the icon PIC ISP COM Port COM 1 Communication Port Browse Select file (ka) Download Up Direction Reset Download Succeeded Step 14: Double click the icon WINX TALK Open Port Talk Talk Window Down Direction Reset Output. Serial no: 101101 Step 15: Verify the real time clock output in the kit and notice the alarm (LED indication)
99
FLOW CHART:
START
SPECIFY THE DATA TO BE DISPLAY
IF DISPLA Y IS IDLE
YES
NO
CLEAR THE DATA IN DISPLAY
INCREMENT THE CURSOR TO DISPLAY DATA
VL9255 VLSI STOP DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66
100
PROGRAM: --Design -- Lecturer --Author --VMP No --Version : LCD DISPLAY : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : MPLAB IDE -7.41 --Description : To implement LCD Display
//This Program for display the string via character based LCD #include <16F877A.H> #use delay(clock=20000000) #use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7) void busycheck( ); unsigned int array[19] = {VLSI DESIGN LAB}; unsigned char a, i, b; void main( ) { While(1) { output_low(PIN_B3); output_high(PIN_B1);
101 busycheck( ); output_d(0x38); output_low(PIN_B3); busycheck( ); output_d(0x06); output_low(PIN_B3); busycheck( ); output_d(0x01); output_low(PIN_B3); busycheck( ); output_d(0x0f); output_low(PIN_B3); busycheck( ); output_d(0x80); output_low(PIN_B3); for (i=0; i<15; i++) { busycheck( ); output_d(0x01); output_low(PIN_B1); output_high(PIN_B1); b=array[i]; output_d(b); output_high(PIN_B3); /* Starting address */ output_high(PIN_B3); /* Cursor on */ output_high(PIN_B3); /* Clear display */ output_high(PIN_B3); /* Function set */ output_high(PIN_B3); /* Entry mode set */ output_high(PIN_B3);
102 output_low(PIN_B3); } } stop: goto stop; } void busycheck( ) { output_d(0x02); output_low(PIN_B1); output_high(PIN_B1); delay_ms(2); busy: output_high(PIN_B3); output_low(PIN_B3); a=input_d( ); if ((a&0x80) = =0x80) goto busy; output_d(0x0); output_low(PIN_B1); output_high(PIN_B1); delay_us(10); }
103
RESULT: Thus the program for PIC16F877A device was written using MPLAB IDE for LCD display by using PIC Embedded Trainer. EX.NO. 10 DATE:22-4-2010
IMPLEMENTATION OF SEVEN SEGMENT DISPLAY USING PIC MICROCONTROLLER
AIM: To write a program for seven segment display by using PIC 16F877A device using MPLAB IDE and implementing the same in kit. TOOLS REQUIRED: PIC-Microcontroller kit MPLAB-IDE 7.41 Win talk PIC-ISP Data cable Power cord
PROCEDURE: Step 1: Start MPLAB IDE by double clicking that icon. Step 2: Select PIC 16F877A as target device in MPLAB device selection. Step 3: Select MPLAB CCS C compiler as the language tool. C:\ Program files PICC CCS C (Code Composer Studio)
104 Step 4: Create a project using the project wizard Project Project Wizard Next Next Finish. Step 5: Create a new C file and write the coding for RTC and add it to the project. Step 6: Save the program or file with extension .c eg: ka.c Step 7: Add Library file and linker file for the corresponding PIC in the project. Right click in Source file Add file Open ka.c Step 8: Project Select Language Tool Suite Ok Project Select Language Tool Location Ok Project Build options Click file name ka.c Step 9: Enable Alternate settings + pe Ok Project Compile Build all Ok Step 10: Verify the output in MPLAB IDE through its registers and ports options. Step 11: Connect the target device with PIC 16F877A to the COM port in the system. Step 12: Program the Hex file in the target device. Step 13: Double click the icon PIC ISP COM Port COM 1 Communication Port Browse Select file (ka) Download Up Direction Reset Download Succeeded Step 14: Double click the icon WINX TALK Open Port Talk Talk Window Down Direction Reset Output. Serial no: 101101 Step 15: Verify the real time clock output in the kit and notice the alarm (LED indication)
105
FLOW CHART
START
SPECIFY THE DATA NO I2C IDL E YES TRANSMIT THE DATA FROM MASTER
RECEIVE THE DATA IN SLAVE
CONFIGURE I2C FOR 7 BIT ADDRESS

DISPLAY OUTPUT STOP
106
PROGRAM: --Design -- Lecturer --Author --VMP No --Version : SEVEN SEGMENT DISPLAY : P.Karpagam : K.SANGEETHA LAKSHMI : VMP-66 : MPLAB IDE -7.41 --Description : To implement Seven Segment Display
// 7-segment display #include <16F877A.H> #use delay(clock=20000000) #use I2C(MASTER,sda=PIN_C4,scl=PIN_C3) void IC_Config( ); unsigned long int c; void main() { IC_Config(); while(1) { delay_ms(8);
107 i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x77); i2c_write(0xfe); i2c_stop(); delay_ms(8); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x7f); i2c_write(0xfd); i2c_stop(); delay_ms(8); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x39); i2c_write(0xfb); i2c_stop(); delay_ms(8); i2c_start(); i2c_write(0x44); i2c_write(0x00); i2c_write(0x3f); i2c_write(0xf7); i2c_stop(); } } void IC_Config() { delay_us(1000);
108 i2c_start(); i2c_write(0x44); i2c_write(0x04); i2c_write(0x00); i2c_write(0x00); i2c_stop(); delay_us(1000); i2c_start(); i2c_write(0x44); i2c_write(0x06); i2c_write(0x00); i2c_write(0x00); i2c_stop(); delay_us(1000); i2c_start(); i2c_write(0x44); i2c_write(0x0a); i2c_write(0x01); i2c_write(0x01); i2c_stop(); delay_us(1000); } //GPIO Register //GPIO Register //GPIO Register
109
RESULT: Thus the program for PIC16F877A device was written using MPLAB IDE for the seven segment display and the same was verified by display in 7segment display by using PIC Embedded Trainer.

Implementation of 8 Bit Alu in Fpga: EX - NO. 1 DATE: 11-2-2010

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Implementation of 8 Bit Alu in Fpga: EX - NO. 1 DATE: 11-2-2010

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1 EX.NO.

IMPLEMENTATION OF 8 BIT ALU IN FPGA

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

Step 3: File New project

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

Step6: Double click on create new source

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

Step 16- GENERATE PROGRAMMING FILE

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

--Description : To Design and implement ALU in FPGA

PROGRAM FOR ALU:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

SYNTHESIS RTL SCHEMATIC:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

SYNTHESIS TECHNOLOGY SCHEMATIC:

SIMULATION OUTPUT WAVEFORM:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

BACK ANNOTATE- REPORT:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

20 EX.NO. 2 DATE: 18-2-2010

IMPLEMENTATION OF 4 BIT SLICED PROCESSOR IN FPGA

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

--Description : To Design and Implement Sliced Processor

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

SYNTHESIS RTL SCHEMATIC:

SYNTHESIS TECHNOLOGY SCHEMATIC:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

11 out of 3584 1% 0 out of 1792 0%

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

28 NET "ai" LOC = "P34"; #PINLOCK_END

EX.NO. 3 DATE: 25-2-2010

SYSTEM DESIGN USING PLL

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

PLL BLOCK DIAGRAM

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

--Description : To Design and Implement PLL

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

SYNTHESIZE RTL SCHEMATIC:

SYNTHESIZE TECHNOLOGY SCHEMATIC:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

BACK ANNOTATE- REPORT:

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66

VL9255 VLSI DESIGN LAB II K.SANGEETHA LAKSHMI, VMP-66